23 #define RP_TX_REG0			0x2000
24 #define RP_TX_REG1			0x2004
25 #define RP_TX_CNTRL			0x2008
26 #define RP_TX_EOP			0x2
27 #define RP_TX_SOP			0x1
28 #define RP_RXCPL_STATUS			0x2010
29 #define RP_RXCPL_EOP			0x2
30 #define RP_RXCPL_SOP			0x1
31 #define RP_RXCPL_REG0			0x2014
32 #define RP_RXCPL_REG1			0x2018
33 #define P2A_INT_STATUS			0x3060
34 #define P2A_INT_STS_ALL			0xf
35 #define P2A_INT_ENABLE			0x3070
36 #define P2A_INT_ENA_ALL			0xf
37 #define RP_LTSSM			0x3c64
38 #define RP_LTSSM_MASK			0x1f
39 #define LTSSM_L0			0xf
41 #define S10_RP_TX_CNTRL			0x2004
42 #define S10_RP_RXCPL_REG		0x2008
43 #define S10_RP_RXCPL_STATUS		0x200C
49 /* TLP configuration type 0 and 1 */
50 #define TLP_FMTTYPE_CFGRD0		0x04	/* Configuration Read Type 0 */
51 #define TLP_FMTTYPE_CFGWR0		0x44	/* Configuration Write Type 0 */
52 #define TLP_FMTTYPE_CFGRD1		0x05	/* Configuration Read Type 1 */
53 #define TLP_FMTTYPE_CFGWR1		0x45	/* Configuration Write Type 1 */
54 #define TLP_PAYLOAD_SIZE		0x01
55 #define TLP_READ_TAG			0x1d
56 #define TLP_WRITE_TAG			0x10
57 #define RP_DEVFN			0
66 #define TLP_BYTE_COUNT(s)		(((s) >> 0) & 0xfff)
75 #define S10_TLP_FMTTYPE_CFGRD0		0x05
76 #define S10_TLP_FMTTYPE_CFGRD1		0x04
77 #define S10_TLP_FMTTYPE_CFGWR0		0x45
78 #define S10_TLP_FMTTYPE_CFGWR1		0x44
81 	ALTERA_PCIE_V1 = 0,
160 	if (pci_is_root_bus(bus) && (devfn == 0) &&  in altera_pcie_hide_rc_bar()
191 	if (bus->number == pcie->root_bus_nr && dev > 0)  in altera_pcie_valid_device()
209 	for (i = 0; i < TLP_LOOP; i++) {  in tlp_read_packet()
244 	for (count = 0; count < TLP_LOOP; count++) {  in s10_tlp_read_packet()
248 			dw[0] = cra_readl(pcie, S10_RP_RXCPL_REG);  in s10_tlp_read_packet()
288 	tlp_rp_regdata.reg0 = headers[0];  in tlp_write_packet()
295 		tlp_rp_regdata.reg1 = 0;  in tlp_write_packet()
296 		tlp_rp_regdata.ctrl = 0;  in tlp_write_packet()
300 		tlp_rp_regdata.reg1 = 0;  in tlp_write_packet()
313 	s10_tlp_write_tx(pcie, headers[0], RP_TX_SOP);  in s10_tlp_write_packet()
314 	s10_tlp_write_tx(pcie, headers[1], 0);  in s10_tlp_write_packet()
315 	s10_tlp_write_tx(pcie, headers[2], 0);  in s10_tlp_write_packet()
332 	headers[0] = TLP_CFG_DW0(pcie, cfg);  in get_tlp_header()
345 	pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 0, false);  in tlp_cfg_dword_read()
360 	if ((where & 0x7) == 0)  in tlp_cfg_dword_write()
423 		pcie->root_bus_nr = value & 0xff;  in s10_rp_write_cfg()
448 		byte_en = 0xf;  in _altera_pcie_cfg_read()
459 		*value = (data >> (8 * (where & 0x3))) & 0xff;  in _altera_pcie_cfg_read()
462 		*value = (data >> (8 * (where & 0x2))) & 0xffff;  in _altera_pcie_cfg_read()
486 		data32 = (value & 0xff) << shift;  in _altera_pcie_cfg_write()
490 		data32 = (value & 0xffff) << shift;  in _altera_pcie_cfg_write()
495 		byte_en = 0xf;  in _altera_pcie_cfg_write()
630 	return 0;  in altera_pcie_intx_map()
652 		& P2A_INT_STS_ALL) != 0) {  in altera_pcie_isr()
679 	return 0;  in altera_pcie_init_irq_domain()
705 	pcie->irq = platform_get_irq(pdev, 0);  in altera_pcie_parse_dt()
706 	if (pcie->irq < 0)  in altera_pcie_parse_dt()
710 	return 0;  in altera_pcie_parse_dt()
734 	.cap_offset = 0x80,
745 	.cap_offset = 0x70,