Lines Matching +full:0 +full:x3060
26 #define CG_SPLL_FUNC_CNTL 0x600
27 # define SPLL_RESET (1 << 0)
33 # define SPLL_FB_DIV_MASK (0xff << 2)
39 # define SPLL_SW_HILEN_MASK (0xf << 16)
42 # define SPLL_SW_LOLEN_MASK (0xf << 20)
51 #define FVTHROT_CNTRL_REG 0x3000
52 #define DONT_WAIT_FOR_FBDIV_WRAP (1 << 0)
55 #define MINIMUM_CIP_MASK 0x1fffffe
58 #define REFRESH_RATE_DIVISOR_MASK (0x3 << 25)
64 #define FVTHROT_TARGET_REG 0x3004
65 #define TARGET_IDLE_COUNT(x) ((x) << 0)
66 #define TARGET_IDLE_COUNT_MASK 0xffffff
67 #define TARGET_IDLE_COUNT_SHIFT 0
68 #define FVTHROT_CB1 0x3008
69 #define FVTHROT_CB2 0x300c
70 #define FVTHROT_CB3 0x3010
71 #define FVTHROT_CB4 0x3014
72 #define FVTHROT_UTC0 0x3018
73 #define FVTHROT_UTC1 0x301c
74 #define FVTHROT_UTC2 0x3020
75 #define FVTHROT_UTC3 0x3024
76 #define FVTHROT_UTC4 0x3028
77 #define FVTHROT_DTC0 0x302c
78 #define FVTHROT_DTC1 0x3030
79 #define FVTHROT_DTC2 0x3034
80 #define FVTHROT_DTC3 0x3038
81 #define FVTHROT_DTC4 0x303c
82 #define FVTHROT_FBDIV_REG0 0x3040
83 #define MIN_FEEDBACK_DIV(x) ((x) << 0)
84 #define MIN_FEEDBACK_DIV_MASK 0xfff
85 #define MIN_FEEDBACK_DIV_SHIFT 0
87 #define MAX_FEEDBACK_DIV_MASK (0xfff << 12)
89 #define FVTHROT_FBDIV_REG1 0x3044
90 #define MAX_FEEDBACK_STEP(x) ((x) << 0)
91 #define MAX_FEEDBACK_STEP_MASK 0xfff
92 #define MAX_FEEDBACK_STEP_SHIFT 0
94 #define STARTING_FEEDBACK_DIV_MASK (0xfff << 12)
97 #define FVTHROT_FBDIV_REG2 0x3048
98 #define FORCED_FEEDBACK_DIV(x) ((x) << 0)
99 #define FORCED_FEEDBACK_DIV_MASK 0xfff
100 #define FORCED_FEEDBACK_DIV_SHIFT 0
102 #define FB_DIV_TIMER_VAL_MASK (0xffff << 12)
104 #define FVTHROT_FB_US_REG0 0x304c
105 #define FVTHROT_FB_US_REG1 0x3050
106 #define FVTHROT_FB_DS_REG0 0x3054
107 #define FVTHROT_FB_DS_REG1 0x3058
108 #define FVTHROT_PWM_CTRL_REG0 0x305c
109 #define STARTING_PWM_HIGHTIME(x) ((x) << 0)
110 #define STARTING_PWM_HIGHTIME_MASK 0xfff
111 #define STARTING_PWM_HIGHTIME_SHIFT 0
113 #define NUMBER_OF_CYCLES_IN_PERIOD_MASK (0xfff << 12)
117 #define FVTHROT_PWM_CTRL_REG1 0x3060
118 #define MIN_PWM_HIGHTIME(x) ((x) << 0)
119 #define MIN_PWM_HIGHTIME_MASK 0xfff
120 #define MIN_PWM_HIGHTIME_SHIFT 0
122 #define MAX_PWM_HIGHTIME_MASK (0xfff << 12)
124 #define FVTHROT_PWM_US_REG0 0x3064
125 #define FVTHROT_PWM_US_REG1 0x3068
126 #define FVTHROT_PWM_DS_REG0 0x306c
127 #define FVTHROT_PWM_DS_REG1 0x3070
128 #define FVTHROT_STATUS_REG0 0x3074
129 #define CURRENT_FEEDBACK_DIV_MASK 0xfff
130 #define CURRENT_FEEDBACK_DIV_SHIFT 0
131 #define FVTHROT_STATUS_REG1 0x3078
132 #define FVTHROT_STATUS_REG2 0x307c
133 #define CG_INTGFX_MISC 0x3080
135 #define FVTHROT_PWM_FEEDBACK_DIV_REG1 0x308c
136 #define RANGE0_PWM_FEEDBACK_DIV(x) ((x) << 0)
137 #define RANGE0_PWM_FEEDBACK_DIV_MASK 0xfff
138 #define RANGE0_PWM_FEEDBACK_DIV_SHIFT 0
140 #define FVTHROT_PWM_FEEDBACK_DIV_REG2 0x3090
141 #define RANGE1_PWM_FEEDBACK_DIV(x) ((x) << 0)
142 #define RANGE1_PWM_FEEDBACK_DIV_MASK 0xfff
143 #define RANGE1_PWM_FEEDBACK_DIV_SHIFT 0
145 #define RANGE2_PWM_FEEDBACK_DIV_MASK (0xfff << 12)
147 #define FVTHROT_PWM_FEEDBACK_DIV_REG3 0x3094
148 #define RANGE0_PWM(x) ((x) << 0)
149 #define RANGE0_PWM_MASK 0xfff
150 #define RANGE0_PWM_SHIFT 0
152 #define RANGE1_PWM_MASK (0xfff << 12)
154 #define FVTHROT_PWM_FEEDBACK_DIV_REG4 0x3098
155 #define RANGE2_PWM(x) ((x) << 0)
156 #define RANGE2_PWM_MASK 0xfff
157 #define RANGE2_PWM_SHIFT 0
159 #define RANGE3_PWM_MASK (0xfff << 12)
161 #define FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1 0x30ac
162 #define RANGE0_SLOW_CLK_FEEDBACK_DIV(x) ((x) << 0)
163 #define RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK 0xfff
164 #define RANGE0_SLOW_CLK_FEEDBACK_DIV_SHIFT 0
167 #define GFX_MACRO_BYPASS_CNTL 0x30c0
168 #define SPLL_BYPASS_CNTL (1 << 0)