Lines Matching +full:0 +full:x3060
31 #define AR0521_MIN_X_ADDR_START 0u
32 #define AR0521_MIN_Y_ADDR_START 0u
46 #define AR0521_ANA_GAIN_MIN 0x00
47 #define AR0521_ANA_GAIN_MAX 0x3f
48 #define AR0521_ANA_GAIN_STEP 0x01
49 #define AR0521_ANA_GAIN_DEFAULT 0x00
52 #define AR0521_REG_VT_PIX_CLK_DIV 0x0300
53 #define AR0521_REG_FRAME_LENGTH_LINES 0x0340
55 #define AR0521_REG_CHIP_ID 0x3000
56 #define AR0521_REG_COARSE_INTEGRATION_TIME 0x3012
57 #define AR0521_REG_ROW_SPEED 0x3016
58 #define AR0521_REG_EXTRA_DELAY 0x3018
59 #define AR0521_REG_RESET 0x301A
60 #define AR0521_REG_RESET_DEFAULTS 0x0238
61 #define AR0521_REG_RESET_GROUP_PARAM_HOLD 0x8000
64 #define AR0521_REG_RESET_INIT BIT(0)
66 #define AR0521_REG_ANA_GAIN_CODE_GLOBAL 0x3028
68 #define AR0521_REG_GREEN1_GAIN 0x3056
69 #define AR0521_REG_BLUE_GAIN 0x3058
70 #define AR0521_REG_RED_GAIN 0x305A
71 #define AR0521_REG_GREEN2_GAIN 0x305C
72 #define AR0521_REG_GLOBAL_GAIN 0x305E
74 #define AR0521_REG_HISPI_TEST_MODE 0x3066
75 #define AR0521_REG_HISPI_TEST_MODE_LP11 0x0004
77 #define AR0521_REG_TEST_PATTERN_MODE 0x3070
79 #define AR0521_REG_SERIAL_FORMAT 0x31AE
80 #define AR0521_REG_SERIAL_FORMAT_MIPI 0x0200
82 #define AR0521_REG_HISPI_CONTROL_STATUS 0x31C6
83 #define AR0521_REG_HISPI_CONTROL_STATUS_FRAMER_TEST_MODE_ENABLE 0x80
184 if (ret < 0) { in ar0521_write_regs()
189 return 0; in ar0521_write_regs()
226 int red = max(green + sensor->ctrls.red_balance->val, 0); in ar0521_set_gains()
227 int blue = max(green + sensor->ctrls.blue_balance->val, 0); in ar0521_set_gains()
229 unsigned int analog = min(gain, 64u); /* range is 0 - 127 */ in ar0521_set_gains()
235 regs[0] = be(AR0521_REG_GREEN1_GAIN); in ar0521_set_gains()
347 /* 0x300 */ be(sensor->pll.vt_pix), /* vt_pix_clk_div = bpp / 2 */ in ar0521_pll_config()
348 /* 0x302 */ be(1), /* vt_sys_clk_div */ in ar0521_pll_config()
349 /* 0x304 */ be((sensor->pll.pre2 << 8) | sensor->pll.pre), in ar0521_pll_config()
350 /* 0x306 */ be((sensor->pll.mult2 << 8) | sensor->pll.mult), in ar0521_pll_config()
351 /* 0x308 */ be(sensor->pll.vt_pix * 2), /* op_pix_clk_div = 2 * vt_pix_clk_div */ in ar0521_pll_config()
352 /* 0x30A */ be(1) /* op_sys_clk_div */ in ar0521_pll_config()
365 if (ret < 0) in ar0521_set_stream()
388 0); in ar0521_set_stream()
399 return 0; in ar0521_set_stream()
410 ret = ar0521_write_reg(sensor, AR0521_REG_GLOBAL_GAIN, 0x2000); in ar0521_set_stream()
421 return 0; in ar0521_set_stream()
449 fmt = v4l2_subdev_state_get_format(sd_state, 0); in ar0521_get_fmt()
456 return 0; in ar0521_get_fmt()
474 fmt = v4l2_subdev_state_get_format(sd_state, 0); in ar0521_set_fmt()
479 return 0; in ar0521_set_fmt()
548 return 0; in ar0521_s_ctrl()
615 ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN, 0, 511, 1, 0); in ar0521_init_controls()
617 -512, 511, 1, 0); in ar0521_init_controls()
619 -512, 511, 1, 0); in ar0521_init_controls()
644 ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE, 0, in ar0521_init_controls()
645 exposure_max, 1, 0x70); in ar0521_init_controls()
649 0, ar0521_link_frequencies); in ar0521_init_controls()
656 0, 0, test_pattern_menu); in ar0521_init_controls()
664 return 0; in ar0521_init_controls()
675 const __be16 *data; /* data[0] is register address */
678 REGS(be(0x0112), be(0x0808)), /* 8-bit/8-bit mode */
681 REGS(be(0x301E), be(0x00AA)),
684 REGS(be(0x3042),
685 be(0x0004), /* 3042: RNC: enable b/w rnc mode */
686 be(0x4580)), /* 3044: RNC: enable row noise correction */
688 REGS(be(0x30D2),
689 be(0x0000), /* 30D2: CRM/CC: enable crm on Visible and CC rows */
690 be(0x0000), /* 30D4: CC: CC enabled with 16 samples per column */
692 be(0x2FFF)),
694 REGS(be(0x30DA),
695 be(0x0FFF), /* 30DA: CC: column correction clip level 2 is 0 */
696 be(0x0FFF), /* 30DC: CC: column correction clip level 3 is 0 */
697 be(0x0000)), /* 30DE: CC: Group FPN correction */
700 REGS(be(0x30EE), be(0x1136)),
701 REGS(be(0x30FA), be(0xFD00)), /* GPIO0 = flash, GPIO1 = shutter */
702 REGS(be(0x3120), be(0x0005)), /* p1 dither enabled for 10bit mode */
703 REGS(be(0x3172), be(0x0206)), /* txlo clk divider options */
705 REGS(be(0x3180), be(0x9434)),
707 REGS(be(0x31B0),
708 be(0x008B), /* 31B0: frame_preamble - FIXME check WRT lanes# */
709 be(0x0050)), /* 31B2: line_preamble - FIXME check WRT lanes# */
712 REGS(be(0x31BC), be(0x068C)),
713 REGS(be(0x31E0), be(0x0781)), /* Fuse/2DDC: enable 2ddc */
716 REGS(be(0x341A), be(0x4735)), /* Samp&Hold pulse in ADC */
717 REGS(be(0x3420), be(0x4735)), /* Samp&Hold pulse in ADC */
718 REGS(be(0x3426), be(0x8A1A)), /* ADC offset distribution pulse */
719 REGS(be(0x342A), be(0x0018)), /* pulse_config */
722 REGS(be(0x3D00),
723 /* 3D00 */ be(0x043E), be(0x4760), be(0xFFFF), be(0xFFFF),
724 /* 3D08 */ be(0x8000), be(0x0510), be(0xAF08), be(0x0252),
725 /* 3D10 */ be(0x486F), be(0x5D5D), be(0x8056), be(0x8313),
726 /* 3D18 */ be(0x0087), be(0x6A48), be(0x6982), be(0x0280),
727 /* 3D20 */ be(0x8359), be(0x8D02), be(0x8020), be(0x4882),
728 /* 3D28 */ be(0x4269), be(0x6A95), be(0x5988), be(0x5A83),
729 /* 3D30 */ be(0x5885), be(0x6280), be(0x6289), be(0x6097),
730 /* 3D38 */ be(0x5782), be(0x605C), be(0xBF18), be(0x0961),
731 /* 3D40 */ be(0x5080), be(0x2090), be(0x4390), be(0x4382),
732 /* 3D48 */ be(0x5F8A), be(0x5D5D), be(0x9C63), be(0x8063),
733 /* 3D50 */ be(0xA960), be(0x9757), be(0x8260), be(0x5CFF),
734 /* 3D58 */ be(0xBF10), be(0x1681), be(0x0802), be(0x8000),
735 /* 3D60 */ be(0x141C), be(0x6000), be(0x6022), be(0x4D80),
736 /* 3D68 */ be(0x5C97), be(0x6A69), be(0xAC6F), be(0x4645),
737 /* 3D70 */ be(0x4400), be(0x0513), be(0x8069), be(0x6AC6),
738 /* 3D78 */ be(0x5F95), be(0x5F70), be(0x8040), be(0x4A81),
739 /* 3D80 */ be(0x0300), be(0xE703), be(0x0088), be(0x4A83),
740 /* 3D88 */ be(0x40FF), be(0xFFFF), be(0xFD70), be(0x8040),
741 /* 3D90 */ be(0x4A85), be(0x4FA8), be(0x4F8C), be(0x0070),
742 /* 3D98 */ be(0xBE47), be(0x8847), be(0xBC78), be(0x6B89),
743 /* 3DA0 */ be(0x6A80), be(0x6986), be(0x6B8E), be(0x6B80),
744 /* 3DA8 */ be(0x6980), be(0x6A88), be(0x7C9F), be(0x866B),
745 /* 3DB0 */ be(0x8765), be(0x46FF), be(0xE365), be(0xA679),
746 /* 3DB8 */ be(0x4A40), be(0x4580), be(0x44BC), be(0x7000),
747 /* 3DC0 */ be(0x8040), be(0x0802), be(0x10EF), be(0x0104),
748 /* 3DC8 */ be(0x3860), be(0x5D5D), be(0x5682), be(0x1300),
749 /* 3DD0 */ be(0x8648), be(0x8202), be(0x8082), be(0x598A),
750 /* 3DD8 */ be(0x0280), be(0x2048), be(0x3060), be(0x8042),
751 /* 3DE0 */ be(0x9259), be(0x865A), be(0x8258), be(0x8562),
752 /* 3DE8 */ be(0x8062), be(0x8560), be(0x9257), be(0x8221),
753 /* 3DF0 */ be(0x10FF), be(0xB757), be(0x9361), be(0x1019),
754 /* 3DF8 */ be(0x8020), be(0x9043), be(0x8E43), be(0x845F),
755 /* 3E00 */ be(0x835D), be(0x805D), be(0x8163), be(0x8063),
756 /* 3E08 */ be(0xA060), be(0x9157), be(0x8260), be(0x5CFF),
757 /* 3E10 */ be(0xFFFF), be(0xFFE5), be(0x1016), be(0x2048),
758 /* 3E18 */ be(0x0802), be(0x1C60), be(0x0014), be(0x0060),
759 /* 3E20 */ be(0x2205), be(0x8120), be(0x908F), be(0x6A80),
760 /* 3E28 */ be(0x6982), be(0x5F9F), be(0x6F46), be(0x4544),
761 /* 3E30 */ be(0x0005), be(0x8013), be(0x8069), be(0x6A80),
762 /* 3E38 */ be(0x7000), be(0x0000), be(0x0000), be(0x0000),
763 /* 3E40 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
764 /* 3E48 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
765 /* 3E50 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
766 /* 3E58 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
767 /* 3E60 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
768 /* 3E68 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
769 /* 3E70 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
770 /* 3E78 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
771 /* 3E80 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
772 /* 3E88 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
773 /* 3E90 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
774 /* 3E98 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
775 /* 3EA0 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
776 /* 3EA8 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
777 /* 3EB0 */ be(0x0000), be(0x0000), be(0x0000)),
779 REGS(be(0x3EB6), be(0x004C)), /* ECL */
781 REGS(be(0x3EBA),
782 be(0xAAAD), /* 3EBA */
783 be(0x0086)), /* 3EBC: Bias currents for FSC/ECL */
785 REGS(be(0x3EC0),
786 be(0x1E00), /* 3EC0: SFbin/SH mode settings */
787 be(0x100A), /* 3EC2: CLK divider for ramp for 10 bit 400MH */
789 be(0x3300),
790 be(0xEA44), /* 3EC6: VLN and clk gating controls */
791 be(0x6F6F), /* 3EC8: Txl0 and Txlo1 settings for normal mode */
792 be(0x2F4A), /* 3ECA: CDAC/Txlo2/RSTGHI/RSTGLO settings */
793 be(0x0506), /* 3ECC: RSTDHI/RSTDLO/CDAC/TXHI settings */
794 /* 3ECE: Ramp buffer settings and Booster enable (bits 0-5) */
795 be(0x203B),
796 be(0x13F0), /* 3ED0: TXLO from atest/sf bin settings */
797 be(0xA53D), /* 3ED2: Ramp offset */
798 be(0x862F), /* 3ED4: TXLO open loop/row driver settings */
799 be(0x4081), /* 3ED6: Txlatch fr cfpn rows/vln bias */
800 be(0x8003), /* 3ED8: Ramp step setting for 10 bit 400 Mhz */
801 be(0xA580), /* 3EDA: Ramp Offset */
802 be(0xC000), /* 3EDC: over range for rst and under range for sig */
803 be(0xC103)), /* 3EDE: over range for sig and col dec clk settings */
806 REGS(be(0x3F00),
807 be(0x0017), /* 3F00: BM_T0 */
808 be(0x02DD), /* 3F02: BM_T1 */
810 be(0x0020),
812 be(0x0040),
814 be(0x0070),
816 be(0x0101),
817 be(0x0302)), /* 3F0C: Define noise_floor2 and noise_floor3 */
819 REGS(be(0x3F10),
820 be(0x0505), /* 3F10: single k factor 0 */
821 be(0x0505), /* 3F12: single k factor 1 */
822 be(0x0505), /* 3F14: single k factor 2 */
823 be(0x01FF), /* 3F16: cross factor 0 */
824 be(0x01FF), /* 3F18: cross factor 1 */
825 be(0x01FF), /* 3F1A: cross factor 2 */
826 be(0x0022)), /* 3F1E */
829 REGS(be(0x3F2C), be(0x442E)),
831 REGS(be(0x3F3E),
832 be(0x0000), /* 3F3E: Switch ADC from 12 bit to 10 bit mode */
833 be(0x1511), /* 3F40: couple k factor 0 */
834 be(0x1511), /* 3F42: couple k factor 1 */
835 be(0x0707)), /* 3F44: couple k factor 2 */
848 for (i = ARRAY_SIZE(ar0521_supply_names) - 1; i >= 0; i--) { in __ar0521_power_off()
862 return 0; in ar0521_power_off()
872 for (cnt = 0; cnt < ARRAY_SIZE(ar0521_supply_names); cnt++) in ar0521_power_on()
875 if (ret < 0) in ar0521_power_on()
882 if (ret < 0) { in ar0521_power_on()
890 gpiod_set_value_cansleep(sensor->reset_gpio, 0); in ar0521_power_on()
893 for (cnt = 0; cnt < ARRAY_SIZE(initial_regs); cnt++) { in ar0521_power_on()
908 ((0x40 << sensor->lane_count) - 0x40) | in ar0521_power_on()
913 ret = ar0521_write_reg(sensor, AR0521_REG_ROW_SPEED, 0x110 | in ar0521_power_on()
918 return 0; in ar0521_power_on()
935 return 0; in ar0521_enum_mbus_code()
953 return 0; in ar0521_enum_frame_size()
965 if (ret < 0) in ar0521_pre_streamon()
980 return 0; in ar0521_pre_streamon()
992 return 0; in ar0521_post_streamoff()
1049 endpoint = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0, in ar0521_probe()
1108 for (cnt = 0; cnt < ARRAY_SIZE(ar0521_supply_names); cnt++) { in ar0521_probe()
1139 return 0; in ar0521_probe()