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/linux-6.12.1/Documentation/devicetree/bindings/media/
Dqcom,sdm845-venus.yaml105 reg = <0x0aa00000 0xff000>;
112 iommus = <&apps_smmu 0x10a0 0x8>,
113 <&apps_smmu 0x10b0 0x0>;
Dqcom,sdm845-venus-v2.yaml103 reg = <0x0aa00000 0xff000>;
119 iommus = <&apps_smmu 0x10a0 0x8>,
120 <&apps_smmu 0x10b0 0x0>;
/linux-6.12.1/drivers/net/can/m_can/
Dtcan4x5x-regmap.c12 #define TCAN4X5X_SPI_INSTRUCTION_WRITE (0x61 << 24)
13 #define TCAN4X5X_SPI_INSTRUCTION_READ (0x41 << 24)
15 #define TCAN4X5X_MAX_REGISTER 0x87fc
63 spi_message_add_tail(&xfer[0], &msg); in tcan4x5x_regmap_read()
70 xfer[0].len = sizeof(buf_tx->cmd); in tcan4x5x_regmap_read()
76 xfer[0].rx_buf = buf_rx; in tcan4x5x_regmap_read()
77 xfer[0].len = sizeof(buf_tx->cmd) + val_len; in tcan4x5x_regmap_read()
80 memset(buf_tx->data, 0x0, val_len); in tcan4x5x_regmap_read()
90 return 0; in tcan4x5x_regmap_read()
95 regmap_reg_range(0x000c, 0x0010),
[all …]
/linux-6.12.1/drivers/gpu/drm/lima/
Dlima_regs.h14 #define LIMA_PMU_POWER_UP 0x00
15 #define LIMA_PMU_POWER_DOWN 0x04
16 #define LIMA_PMU_POWER_GP0_MASK BIT(0)
29 #define LIMA_PMU_STATUS 0x08
30 #define LIMA_PMU_INT_MASK 0x0C
31 #define LIMA_PMU_INT_RAWSTAT 0x10
32 #define LIMA_PMU_INT_CLEAR 0x18
33 #define LIMA_PMU_INT_CMD_MASK BIT(0)
34 #define LIMA_PMU_SW_DELAY 0x1C
37 #define LIMA_L2_CACHE_SIZE 0x0004
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_dkl_phy_regs.h16 #define _DKL_PHY1_BASE 0x168000
17 #define _DKL_PHY2_BASE 0x169000
18 #define _DKL_PHY3_BASE 0x16A000
19 #define _DKL_PHY4_BASE 0x16B000
20 #define _DKL_PHY5_BASE 0x16C000
21 #define _DKL_PHY6_BASE 0x16D000
37 (((phy_offset) >> _DKL_BANK_SHIFT) & 0xf)
49 #define _DKL_PCS_DW5_LN0 0x0014
50 #define _DKL_PCS_DW5_LN1 0x1014
56 #define _DKL_PLL_DIV0 0x2200
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/mxs/
Dimx23-pinfunc.h13 #define MX23_PAD_GPMI_D00__GPMI_D00 0x0000
14 #define MX23_PAD_GPMI_D01__GPMI_D01 0x0010
15 #define MX23_PAD_GPMI_D02__GPMI_D02 0x0020
16 #define MX23_PAD_GPMI_D03__GPMI_D03 0x0030
17 #define MX23_PAD_GPMI_D04__GPMI_D04 0x0040
18 #define MX23_PAD_GPMI_D05__GPMI_D05 0x0050
19 #define MX23_PAD_GPMI_D06__GPMI_D06 0x0060
20 #define MX23_PAD_GPMI_D07__GPMI_D07 0x0070
21 #define MX23_PAD_GPMI_D08__GPMI_D08 0x0080
22 #define MX23_PAD_GPMI_D09__GPMI_D09 0x0090
[all …]
Dimx28-pinfunc.h13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
/linux-6.12.1/arch/m68k/include/asm/
Dmac_psc.h37 #define PSC_BASE (0x50F31000)
44 * To access a particular set of registers, add 0xn0 to the base
48 #define pIFRbase 0x100
49 #define pIERbase 0x104
55 #define PSC_MYSTERY 0x804
57 #define PSC_CTL_BASE 0xC00
59 #define PSC_SCSI_CTL 0xC00
60 #define PSC_ENETRD_CTL 0xC10
61 #define PSC_ENETWR_CTL 0xC20
62 #define PSC_FDC_CTL 0xC30
[all …]
/linux-6.12.1/drivers/clk/qcom/
Dgpucc-sm8250.c22 #define CX_GMU_CBCR_SLEEP_MASK 0xf
24 #define CX_GMU_CBCR_WAKE_MASK 0xf
36 { 249600000, 2000000000, 0 },
40 .l = 0x1a,
41 .alpha = 0xaaa,
42 .config_ctl_val = 0x20485699,
43 .config_ctl_hi_val = 0x00002261,
44 .config_ctl_hi1_val = 0x029a699c,
45 .user_ctl_val = 0x00000000,
46 .user_ctl_hi_val = 0x00000805,
[all …]
Dgpucc-sm8350.c38 { 249600000, 1750000000, 0 },
42 .l = 0x18,
43 .alpha = 0x6000,
44 .config_ctl_val = 0x20485699,
45 .config_ctl_hi_val = 0x00002261,
46 .config_ctl_hi1_val = 0x2a9a699c,
47 .test_ctl_val = 0x00000000,
48 .test_ctl_hi_val = 0x00000000,
49 .test_ctl_hi1_val = 0x01800000,
50 .user_ctl_val = 0x00000000,
[all …]
/linux-6.12.1/arch/powerpc/kvm/
Dmpic.c44 #define VID 0x03 /* MPIC version ID */
47 #define OPENPIC_FLAG_IDR_CRIT (1 << 0)
48 #define OPENPIC_FLAG_ILR (2 << 0)
51 #define OPENPIC_REG_SIZE 0x40000
52 #define OPENPIC_GLB_REG_START 0x0
53 #define OPENPIC_GLB_REG_SIZE 0x10F0
54 #define OPENPIC_TMR_REG_START 0x10F0
55 #define OPENPIC_TMR_REG_SIZE 0x220
56 #define OPENPIC_MSI_REG_START 0x1600
57 #define OPENPIC_MSI_REG_SIZE 0x200
[all …]
/linux-6.12.1/include/media/
Ddvb-usb-ids.h23 #define USB_VID_774 0x7a69
24 #define USB_VID_ADSTECH 0x06e1
25 #define USB_VID_AFATECH 0x15a4
26 #define USB_VID_ALCOR_MICRO 0x058f
27 #define USB_VID_ALINK 0x05e3
28 #define USB_VID_AME 0x06be
29 #define USB_VID_AMT 0x1c73
30 #define USB_VID_ANCHOR 0x0547
31 #define USB_VID_ANSONIC 0x10b9
32 #define USB_VID_ANUBIS_ELECTRONIC 0x10fd
[all …]
/linux-6.12.1/drivers/clk/stm32/
Dstm32mp25_rcc.h10 #define RCC_SECCFGR0 0x0
11 #define RCC_SECCFGR1 0x4
12 #define RCC_SECCFGR2 0x8
13 #define RCC_SECCFGR3 0xC
14 #define RCC_PRIVCFGR0 0x10
15 #define RCC_PRIVCFGR1 0x14
16 #define RCC_PRIVCFGR2 0x18
17 #define RCC_PRIVCFGR3 0x1C
18 #define RCC_RCFGLOCKR0 0x20
19 #define RCC_RCFGLOCKR1 0x24
[all …]
/linux-6.12.1/include/linux/soc/samsung/
Dexynos-regs-pmu.h17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all …]
/linux-6.12.1/drivers/net/ethernet/cavium/liquidio/
Dcn66xx_regs.h26 #define CN6XXX_XPANSION_BAR 0x30
28 #define CN6XXX_MSI_CAP 0x50
29 #define CN6XXX_MSI_ADDR_LO 0x54
30 #define CN6XXX_MSI_ADDR_HI 0x58
31 #define CN6XXX_MSI_DATA 0x5C
33 #define CN6XXX_PCIE_CAP 0x70
34 #define CN6XXX_PCIE_DEVCAP 0x74
35 #define CN6XXX_PCIE_DEVCTL 0x78
36 #define CN6XXX_PCIE_LINKCAP 0x7C
37 #define CN6XXX_PCIE_LINKCTL 0x80
[all …]
/linux-6.12.1/drivers/char/
Dsonypi.c54 module_param(minor, int, 0);
58 static int verbose; /* = 0 */
60 MODULE_PARM_DESC(verbose, "be verbose, default is 0 (no)");
62 static int fnkeyinit; /* = 0 */
67 static int camera; /* = 0 */
72 static int compat; /* = 0 */
77 static unsigned long mask = 0xffffffff;
90 "set this to 0 if you think the automatic ioport check for sony-laptop is wrong");
97 #define SONYPI_IRQ_PORT 0x8034
99 #define SONYPI_TYPE1_BASE 0x50
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/keystone/
Dkeystone-k2g-evm.dts17 reg = <0x00000008 0x00000000 0x00000000 0x80000000>;
27 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
72 #clock-cells = <0>;
76 sound0: sound@0 {
88 simple-audio-card,dai-link@0 {
94 clocks = <&k2g_clks 0x6 1>;
110 clocks = <&k2g_clks 0x6 1>;
125 K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
126 K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
132 K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */
[all …]
/linux-6.12.1/drivers/phy/freescale/
Dphy-fsl-lynx-28g.c15 #define LYNX_28G_PCC8 0x10a0
16 #define LYNX_28G_PCC8_SGMII 0x1
17 #define LYNX_28G_PCC8_SGMII_DIS 0x0
19 #define LYNX_28G_PCCC 0x10b0
20 #define LYNX_28G_PCCC_10GBASER 0x9
21 #define LYNX_28G_PCCC_USXGMII 0x1
22 #define LYNX_28G_PCCC_SXGMII_DIS 0x0
27 #define LYNX_28G_PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
31 #define LYNX_28G_PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4)
33 #define LYNX_28G_PLLnCR0_REFCLK_SEL_100MHZ 0x0
[all …]
/linux-6.12.1/arch/sparc/kernel/
Dpci_sabre.c35 #define SABRE_UE_AFSR 0x0030UL
36 #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
37 #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
38 #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
39 #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
40 #define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */
41 #define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */
42 #define SABRE_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */
43 #define SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */
44 #define SABRE_UEAFSR_BLK 0x0000000000800000UL /* Was block operation */
[all …]
/linux-6.12.1/drivers/net/ethernet/atheros/alx/
Dreg.h38 #define ALX_DEV_ID_AR8161 0x1091
39 #define ALX_DEV_ID_E2200 0xe091
40 #define ALX_DEV_ID_E2400 0xe0a1
41 #define ALX_DEV_ID_E2500 0xe0b1
42 #define ALX_DEV_ID_AR8162 0x1090
43 #define ALX_DEV_ID_AR8171 0x10A1
44 #define ALX_DEV_ID_AR8172 0x10A0
47 * bit(0): with xD support
52 #define ALX_REV_A0 0
57 #define ALX_DEV_CTRL 0x0060
[all …]
/linux-6.12.1/drivers/gpu/drm/bridge/synopsys/
Ddw-hdmi.h10 #define HDMI_DESIGN_ID 0x0000
11 #define HDMI_REVISION_ID 0x0001
12 #define HDMI_PRODUCT_ID0 0x0002
13 #define HDMI_PRODUCT_ID1 0x0003
14 #define HDMI_CONFIG0_ID 0x0004
15 #define HDMI_CONFIG1_ID 0x0005
16 #define HDMI_CONFIG2_ID 0x0006
17 #define HDMI_CONFIG3_ID 0x0007
20 #define HDMI_IH_FC_STAT0 0x0100
21 #define HDMI_IH_FC_STAT1 0x0101
[all …]
/linux-6.12.1/drivers/usb/misc/
Dldusb.c33 #define USB_VENDOR_ID_LD 0x0f11 /* USB Vendor ID of LD Didactic GmbH */
34 #define USB_DEVICE_ID_LD_CASSY 0x1000 /* USB Product ID of CASSY-S modules with 8 bytes endpoint s…
35 #define USB_DEVICE_ID_LD_CASSY2 0x1001 /* USB Product ID of CASSY-S modules with 64 bytes endpoint…
36 #define USB_DEVICE_ID_LD_POCKETCASSY 0x1010 /* USB Product ID of Pocket-CASSY */
37 #define USB_DEVICE_ID_LD_POCKETCASSY2 0x1011 /* USB Product ID of Pocket-CASSY 2 (reserved) */
38 #define USB_DEVICE_ID_LD_MOBILECASSY 0x1020 /* USB Product ID of Mobile-CASSY */
39 #define USB_DEVICE_ID_LD_MOBILECASSY2 0x1021 /* USB Product ID of Mobile-CASSY 2 (reserved) */
40 #define USB_DEVICE_ID_LD_MICROCASSYVOLTAGE 0x1031 /* USB Product ID of Micro-CASSY Voltage */
41 #define USB_DEVICE_ID_LD_MICROCASSYCURRENT 0x1032 /* USB Product ID of Micro-CASSY Current */
42 #define USB_DEVICE_ID_LD_MICROCASSYTIME 0x1033 /* USB Product ID of Micro-CASSY Time (reserved) */
[all …]
/linux-6.12.1/drivers/clk/samsung/
Dclk-exynosautov920.c25 /* Register Offset definitions for CMU_TOP (0x11000000) */
26 #define PLL_LOCKTIME_PLL_MMC 0x0004
27 #define PLL_LOCKTIME_PLL_SHARED0 0x0008
28 #define PLL_LOCKTIME_PLL_SHARED1 0x000c
29 #define PLL_LOCKTIME_PLL_SHARED2 0x0010
30 #define PLL_LOCKTIME_PLL_SHARED3 0x0014
31 #define PLL_LOCKTIME_PLL_SHARED4 0x0018
32 #define PLL_LOCKTIME_PLL_SHARED5 0x0018
33 #define PLL_CON0_PLL_MMC 0x0140
34 #define PLL_CON3_PLL_MMC 0x014c
[all …]
/linux-6.12.1/drivers/hid/
Dhid-ids.h17 #define USB_VENDOR_ID_258A 0x258a
18 #define USB_DEVICE_ID_258A_6A88 0x6a88
20 #define USB_VENDOR_ID_3M 0x0596
21 #define USB_DEVICE_ID_3M1968 0x0500
22 #define USB_DEVICE_ID_3M2256 0x0502
23 #define USB_DEVICE_ID_3M3266 0x0506
25 #define USB_VENDOR_ID_A4TECH 0x09da
26 #define USB_DEVICE_ID_A4TECH_WCP32PU 0x0006
27 #define USB_DEVICE_ID_A4TECH_X5_005D 0x000a
28 #define USB_DEVICE_ID_A4TECH_RP_649 0x001a
[all …]
/linux-6.12.1/drivers/media/dvb-frontends/
Ds5h1411.c42 } while (0)
50 { S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, },
51 { S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, },
52 { S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, },
53 { S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, },
54 { S5H1411_I2C_TOP_ADDR, 0x1f, 0x342c, },
55 { S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, },
56 { S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, },
57 { S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, },
58 { S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, },
[all …]

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