Lines Matching +full:0 +full:x10a0
38 { 249600000, 1750000000, 0 },
42 .l = 0x18,
43 .alpha = 0x6000,
44 .config_ctl_val = 0x20485699,
45 .config_ctl_hi_val = 0x00002261,
46 .config_ctl_hi1_val = 0x2a9a699c,
47 .test_ctl_val = 0x00000000,
48 .test_ctl_hi_val = 0x00000000,
49 .test_ctl_hi1_val = 0x01800000,
50 .user_ctl_val = 0x00000000,
51 .user_ctl_hi_val = 0x00000805,
52 .user_ctl_hi1_val = 0x00000000,
60 .offset = 0x0,
75 .l = 0x1a,
76 .alpha = 0xaaa,
77 .config_ctl_val = 0x20485699,
78 .config_ctl_hi_val = 0x00002261,
79 .config_ctl_hi1_val = 0x2a9a699c,
80 .test_ctl_val = 0x00000000,
81 .test_ctl_hi_val = 0x00000000,
82 .test_ctl_hi1_val = 0x01800000,
83 .user_ctl_val = 0x00000000,
84 .user_ctl_hi_val = 0x00000805,
85 .user_ctl_hi1_val = 0x00000000,
89 .offset = 0x100,
104 { P_BI_TCXO, 0 },
120 { P_BI_TCXO, 0 },
134 F(19200000, P_BI_TCXO, 1, 0, 0),
135 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
136 F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
141 .cmd_rcgr = 0x1120,
142 .mnd_width = 0,
156 F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0),
157 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
158 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
163 .cmd_rcgr = 0x117c,
164 .mnd_width = 0,
178 .reg = 0x11c0,
179 .shift = 0,
193 .reg = 0x11bc,
194 .shift = 0,
208 .halt_reg = 0x1078,
211 .enable_reg = 0x1078,
212 .enable_mask = BIT(0),
226 .halt_reg = 0x1170,
229 .enable_reg = 0x1170,
230 .enable_mask = BIT(0),
239 .halt_reg = 0x107c,
242 .enable_reg = 0x107c,
243 .enable_mask = BIT(0),
257 .halt_reg = 0x1088,
260 .enable_reg = 0x1088,
261 .enable_mask = BIT(0),
270 .halt_reg = 0x1098,
273 .enable_reg = 0x1098,
274 .enable_mask = BIT(0),
288 .halt_reg = 0x1080,
291 .enable_reg = 0x1080,
292 .enable_mask = BIT(0),
301 .halt_reg = 0x1094,
304 .enable_reg = 0x1094,
305 .enable_mask = BIT(0),
314 .halt_reg = 0x1084,
317 .enable_reg = 0x1084,
318 .enable_mask = BIT(0),
327 .halt_reg = 0x108c,
330 .enable_reg = 0x108c,
331 .enable_mask = BIT(0),
340 .halt_reg = 0x1004,
343 .enable_reg = 0x1004,
344 .enable_mask = BIT(0),
353 .halt_reg = 0x109c,
356 .enable_reg = 0x109c,
357 .enable_mask = BIT(0),
366 .halt_reg = 0x120c,
369 .enable_reg = 0x120c,
370 .enable_mask = BIT(0),
379 .halt_reg = 0x1064,
382 .enable_reg = 0x1064,
383 .enable_mask = BIT(0),
397 .halt_reg = 0x105c,
400 .enable_reg = 0x105c,
401 .enable_mask = BIT(0),
410 .halt_reg = 0x1058,
413 .enable_reg = 0x1058,
414 .enable_mask = BIT(0),
423 .halt_reg = 0x5000,
426 .enable_reg = 0x5000,
427 .enable_mask = BIT(0),
436 .halt_reg = 0x1178,
439 .enable_reg = 0x1178,
440 .enable_mask = BIT(0),
454 .halt_reg = 0x1204,
457 .enable_reg = 0x1204,
458 .enable_mask = BIT(0),
472 .halt_reg = 0x802c,
475 .enable_reg = 0x802c,
476 .enable_mask = BIT(0),
485 .halt_reg = 0x8030,
488 .enable_reg = 0x8030,
489 .enable_mask = BIT(0),
498 .halt_reg = 0x1090,
501 .enable_reg = 0x1090,
502 .enable_mask = BIT(0),
511 .gdscr = 0x106c,
512 .gds_hw_ctrl = 0x1540,
521 .gdscr = 0x100c,
522 .clamp_io_ctrl = 0x1508,
562 [GPUCC_GPU_CC_ACD_BCR] = { 0x1160 },
563 [GPUCC_GPU_CC_CB_BCR] = { 0x116c },
564 [GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
565 [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x1174 },
566 [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 },
567 [GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
568 [GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
569 [GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
581 .max_register = 0x8030,