Lines Matching +full:0 +full:x10a0
44 #define VID 0x03 /* MPIC version ID */
47 #define OPENPIC_FLAG_IDR_CRIT (1 << 0)
48 #define OPENPIC_FLAG_ILR (2 << 0)
51 #define OPENPIC_REG_SIZE 0x40000
52 #define OPENPIC_GLB_REG_START 0x0
53 #define OPENPIC_GLB_REG_SIZE 0x10F0
54 #define OPENPIC_TMR_REG_START 0x10F0
55 #define OPENPIC_TMR_REG_SIZE 0x220
56 #define OPENPIC_MSI_REG_START 0x1600
57 #define OPENPIC_MSI_REG_SIZE 0x200
58 #define OPENPIC_SUMMARY_REG_START 0x3800
59 #define OPENPIC_SUMMARY_REG_SIZE 0x800
60 #define OPENPIC_SRC_REG_START 0x10000
61 #define OPENPIC_SRC_REG_SIZE (MAX_SRC * 0x20)
62 #define OPENPIC_CPU_REG_START 0x20000
63 #define OPENPIC_CPU_REG_SIZE (0x100 + ((MAX_CPU - 1) * 0x1000))
79 #define FRR_VID_SHIFT 0
84 #define VIR_GENERIC 0x00000000 /* Generic Vendor ID */
86 #define GCR_RESET 0x80000000
87 #define GCR_MODE_PASS 0x00000000
88 #define GCR_MODE_MIXED 0x20000000
89 #define GCR_MODE_PROXY 0x60000000
91 #define TBCR_CI 0x80000000 /* count inhibit */
92 #define TCCR_TOG 0x80000000 /* toggles when decrement to zero */
99 #define IDR_P0_SHIFT 0
101 #define ILR_INTTGT_MASK 0x000000ff
102 #define ILR_INTTGT_INT 0x00
103 #define ILR_INTTGT_CINT 0x01 /* critical */
104 #define ILR_INTTGT_MCP 0x02 /* machine check */
107 #define MSIIR_OFFSET 0x140
109 #define MSIIR_SRS_MASK (0x7 << MSIIR_SRS_SHIFT)
111 #define MSIIR_IBS_MASK (0x1f << MSIIR_IBS_SHIFT)
132 IRQ_TYPE_NORMAL = 0,
169 #define IVPR_PRIORITY_MASK (0xF << 16)
173 /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */
174 #define IDR_EP 0x80000000 /* external pin */
175 #define IDR_CI 0x40000000 /* critical interrupt */
250 __func__, (int)(dst - &opp->dst[0])); in mpic_irq_raise()
268 __func__, (int)(dst - &opp->dst[0])); in mpic_irq_lower()
347 dst->outputs_active[src->output]++ == 0) { in IRQ_local_pipe()
354 --dst->outputs_active[src->output] == 0) { in IRQ_local_pipe()
379 active = 0; in IRQ_local_pipe()
383 if (IRQ_get_next(opp, &dst->servicing) >= 0 && in IRQ_local_pipe()
442 if (src->destmask == 0) { in openpic_update_irq()
453 for (i = 0; i < opp->nb_cpus; i++) { in openpic_update_irq()
463 i = 0; in openpic_update_irq()
486 pr_debug("openpic: set irq %d = %d ivpr=0x%08x\n", in openpic_set_irq()
506 src->pending = 0; in openpic_set_irq()
521 opp->pir = 0; in openpic_reset()
525 for (i = 0; i < opp->max_irq; i++) { in openpic_reset()
545 for (i = 0; i < MAX_CPU; i++) { in openpic_reset()
547 memset(&opp->dst[i].raised, 0, sizeof(struct irq_queue)); in openpic_reset()
549 memset(&opp->dst[i].servicing, 0, sizeof(struct irq_queue)); in openpic_reset()
553 for (i = 0; i < MAX_TMR; i++) { in openpic_reset()
554 opp->timers[i].tccr = 0; in openpic_reset()
558 opp->gcr = 0; in openpic_reset()
571 return 0xffffffff; in read_IRQreg_ilr()
584 uint32_t crit_mask = 0; in write_IRQreg_idr()
595 pr_debug("Set IDR %d to 0x%08x\n", n_IRQ, src->idr); in write_IRQreg_idr()
606 src->destmask = 0; in write_IRQreg_idr()
608 for (i = 0; i < opp->nb_cpus; i++) { in write_IRQreg_idr()
631 pr_debug("Set ILR %d to 0x%08x, output %d\n", n_IRQ, src->idr, in write_IRQreg_ilr()
634 /* TODO: on MPIC v4.0 only, set nomask for non-INT */ in write_IRQreg_ilr()
643 /* NOTE when implementing newer FSL MPIC models: starting with v4.0, in write_IRQreg_ivpr()
673 pr_debug("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val, in write_IRQreg_ivpr()
691 int err = 0; in openpic_gbl_write()
694 if (addr & 0xF) in openpic_gbl_write()
695 return 0; in openpic_gbl_write()
698 case 0x00: /* Block Revision Register1 (BRR1) is Readonly */ in openpic_gbl_write()
700 case 0x40: in openpic_gbl_write()
701 case 0x50: in openpic_gbl_write()
702 case 0x60: in openpic_gbl_write()
703 case 0x70: in openpic_gbl_write()
704 case 0x80: in openpic_gbl_write()
705 case 0x90: in openpic_gbl_write()
706 case 0xA0: in openpic_gbl_write()
707 case 0xB0: in openpic_gbl_write()
711 case 0x1000: /* FRR */ in openpic_gbl_write()
713 case 0x1020: /* GCR */ in openpic_gbl_write()
716 case 0x1080: /* VIR */ in openpic_gbl_write()
718 case 0x1090: /* PIR */ in openpic_gbl_write()
725 case 0x10A0: /* IPI_IVPR */ in openpic_gbl_write()
726 case 0x10B0: in openpic_gbl_write()
727 case 0x10C0: in openpic_gbl_write()
728 case 0x10D0: { in openpic_gbl_write()
730 idx = (addr - 0x10A0) >> 4; in openpic_gbl_write()
734 case 0x10E0: /* SPVE */ in openpic_gbl_write()
748 int err = 0; in openpic_gbl_read()
751 retval = 0xFFFFFFFF; in openpic_gbl_read()
752 if (addr & 0xF) in openpic_gbl_read()
756 case 0x1000: /* FRR */ in openpic_gbl_read()
760 case 0x1020: /* GCR */ in openpic_gbl_read()
763 case 0x1080: /* VIR */ in openpic_gbl_read()
766 case 0x1090: /* PIR */ in openpic_gbl_read()
767 retval = 0x00000000; in openpic_gbl_read()
769 case 0x00: /* Block Revision Register1 (BRR1) */ in openpic_gbl_read()
772 case 0x40: in openpic_gbl_read()
773 case 0x50: in openpic_gbl_read()
774 case 0x60: in openpic_gbl_read()
775 case 0x70: in openpic_gbl_read()
776 case 0x80: in openpic_gbl_read()
777 case 0x90: in openpic_gbl_read()
778 case 0xA0: in openpic_gbl_read()
779 case 0xB0: in openpic_gbl_read()
783 case 0x10A0: /* IPI_IVPR */ in openpic_gbl_read()
784 case 0x10B0: in openpic_gbl_read()
785 case 0x10C0: in openpic_gbl_read()
786 case 0x10D0: in openpic_gbl_read()
789 idx = (addr - 0x10A0) >> 4; in openpic_gbl_read()
793 case 0x10E0: /* SPVE */ in openpic_gbl_read()
801 pr_debug("%s: => 0x%08x\n", __func__, retval); in openpic_gbl_read()
811 addr += 0x10f0; in openpic_tmr_write()
814 if (addr & 0xF) in openpic_tmr_write()
815 return 0; in openpic_tmr_write()
817 if (addr == 0x10f0) { in openpic_tmr_write()
820 return 0; in openpic_tmr_write()
823 idx = (addr >> 6) & 0x3; in openpic_tmr_write()
824 addr = addr & 0x30; in openpic_tmr_write()
826 switch (addr & 0x30) { in openpic_tmr_write()
827 case 0x00: /* TCCR */ in openpic_tmr_write()
829 case 0x10: /* TBCR */ in openpic_tmr_write()
830 if ((opp->timers[idx].tccr & TCCR_TOG) != 0 && in openpic_tmr_write()
831 (val & TBCR_CI) == 0 && in openpic_tmr_write()
832 (opp->timers[idx].tbcr & TBCR_CI) != 0) in openpic_tmr_write()
837 case 0x20: /* TVPR */ in openpic_tmr_write()
840 case 0x30: /* TDR */ in openpic_tmr_write()
845 return 0; in openpic_tmr_write()
855 if (addr & 0xF) in openpic_tmr_read()
858 idx = (addr >> 6) & 0x3; in openpic_tmr_read()
859 if (addr == 0x0) { in openpic_tmr_read()
865 switch (addr & 0x30) { in openpic_tmr_read()
866 case 0x00: /* TCCR */ in openpic_tmr_read()
869 case 0x10: /* TBCR */ in openpic_tmr_read()
872 case 0x20: /* TIPV */ in openpic_tmr_read()
875 case 0x30: /* TIDE (TIDR) */ in openpic_tmr_read()
881 pr_debug("%s: => 0x%08x\n", __func__, retval); in openpic_tmr_read()
883 return 0; in openpic_tmr_read()
893 addr = addr & 0xffff; in openpic_src_write()
896 switch (addr & 0x1f) { in openpic_src_write()
897 case 0x00: in openpic_src_write()
900 case 0x10: in openpic_src_write()
903 case 0x18: in openpic_src_write()
908 return 0; in openpic_src_write()
918 retval = 0xFFFFFFFF; in openpic_src_read()
920 addr = addr & 0xffff; in openpic_src_read()
923 switch (addr & 0x1f) { in openpic_src_read()
924 case 0x00: in openpic_src_read()
927 case 0x10: in openpic_src_read()
930 case 0x18: in openpic_src_read()
935 pr_debug("%s: => 0x%08x\n", __func__, retval); in openpic_src_read()
937 return 0; in openpic_src_read()
946 pr_debug("%s: addr %#llx <= 0x%08x\n", __func__, addr, val); in openpic_msi_write()
947 if (addr & 0xF) in openpic_msi_write()
948 return 0; in openpic_msi_write()
963 return 0; in openpic_msi_write()
969 uint32_t r = 0; in openpic_msi_read()
973 if (addr & 0xF) in openpic_msi_read()
979 case 0x00: in openpic_msi_read()
980 case 0x10: in openpic_msi_read()
981 case 0x20: in openpic_msi_read()
982 case 0x30: in openpic_msi_read()
983 case 0x40: in openpic_msi_read()
984 case 0x50: in openpic_msi_read()
985 case 0x60: in openpic_msi_read()
986 case 0x70: /* MSIRs */ in openpic_msi_read()
989 opp->msi[srs].msir = 0; in openpic_msi_read()
990 openpic_set_irq(opp, opp->irq_msi + srs, 0); in openpic_msi_read()
992 case 0x120: /* MSISR */ in openpic_msi_read()
993 for (i = 0; i < MAX_MSI; i++) in openpic_msi_read()
994 r |= (opp->msi[i].msir ? 1 : 0) << i; in openpic_msi_read()
998 pr_debug("%s: => 0x%08x\n", __func__, r); in openpic_msi_read()
1000 return 0; in openpic_msi_read()
1005 uint32_t r = 0; in openpic_summary_read()
1012 return 0; in openpic_summary_read()
1017 pr_debug("%s: addr %#llx <= 0x%08x\n", __func__, addr, val); in openpic_summary_write()
1020 return 0; in openpic_summary_write()
1031 pr_debug("%s: cpu %d addr %#llx <= 0x%08x\n", __func__, idx, in openpic_cpu_write_internal()
1034 if (idx < 0) in openpic_cpu_write_internal()
1035 return 0; in openpic_cpu_write_internal()
1037 if (addr & 0xF) in openpic_cpu_write_internal()
1038 return 0; in openpic_cpu_write_internal()
1041 addr &= 0xFF0; in openpic_cpu_write_internal()
1043 case 0x40: /* IPIDR */ in openpic_cpu_write_internal()
1044 case 0x50: in openpic_cpu_write_internal()
1045 case 0x60: in openpic_cpu_write_internal()
1046 case 0x70: in openpic_cpu_write_internal()
1047 idx = (addr - 0x40) >> 4; in openpic_cpu_write_internal()
1051 openpic_set_irq(opp, opp->irq_ipi0 + idx, 0); in openpic_cpu_write_internal()
1053 case 0x80: /* CTPR */ in openpic_cpu_write_internal()
1054 dst->ctpr = val & 0x0000000F; in openpic_cpu_write_internal()
1071 case 0x90: /* WHOAMI */ in openpic_cpu_write_internal()
1074 case 0xA0: /* IACK */ in openpic_cpu_write_internal()
1077 case 0xB0: { /* EOI */ in openpic_cpu_write_internal()
1083 if (s_IRQ < 0) { in openpic_cpu_write_internal()
1106 kvm_notify_acked_irq(opp->kvm, 0, notify_eoi); in openpic_cpu_write_internal()
1115 return 0; in openpic_cpu_write_internal()
1123 (addr & 0x1f000) >> 12); in openpic_cpu_write()
1145 pr_err("%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n", in openpic_iack()
1158 src->pending = 0; in openpic_iack()
1167 openpic_set_irq(opp, irq, 0); in openpic_iack()
1198 retval = 0xFFFFFFFF; in openpic_cpu_read_internal()
1200 if (idx < 0) in openpic_cpu_read_internal()
1203 if (addr & 0xF) in openpic_cpu_read_internal()
1207 addr &= 0xFF0; in openpic_cpu_read_internal()
1209 case 0x80: /* CTPR */ in openpic_cpu_read_internal()
1212 case 0x90: /* WHOAMI */ in openpic_cpu_read_internal()
1215 case 0xA0: /* IACK */ in openpic_cpu_read_internal()
1218 case 0xB0: /* EOI */ in openpic_cpu_read_internal()
1219 retval = 0; in openpic_cpu_read_internal()
1224 pr_debug("%s: => 0x%08x\n", __func__, retval); in openpic_cpu_read_internal()
1228 return 0; in openpic_cpu_read_internal()
1236 (addr & 0x1f000) >> 12); in openpic_cpu_read()
1308 opp->vector_mask = 0xFFFF; in fsl_common_init()
1309 opp->tfrr_reset = 0; in fsl_common_init()
1311 opp->idr_reset = 1 << 0; in fsl_common_init()
1323 for (i = 0; i < opp->fsl->max_ext; i++) in fsl_common_init()
1343 for (i = 0; i < opp->num_mmio_regions; i++) { in kvm_mpic_read_internal()
1359 for (i = 0; i < opp->num_mmio_regions; i++) { in kvm_mpic_write_internal()
1466 if (base & 0x3ffff) { in set_base_addr()
1473 return 0; in set_base_addr()
1483 if (base == 0) in set_base_addr()
1490 return 0; in set_base_addr()
1493 #define ATTR_SET 0
1544 if (attr32 != 0 && attr32 != 1) in mpic_set_attr()
1550 return 0; in mpic_set_attr()
1575 return 0; in mpic_get_attr()
1588 return 0; in mpic_get_attr()
1601 return 0; in mpic_get_attr()
1613 return 0; in mpic_has_attr()
1619 return 0; in mpic_has_attr()
1625 return 0; in mpic_has_attr()
1649 kvm_set_irq_routing(opp->kvm, routing, 0, 0); in mpic_set_default_irq_routing()
1652 return 0; in mpic_set_default_irq_routing()
1682 opp->brr1 = 0x00400200; in mpic_create()
1693 opp->brr1 = 0x00400402; in mpic_create()
1716 return 0; in mpic_create()
1736 int ret = 0; in kvmppc_mpic_connect_vcpu()
1742 if (cpu < 0 || cpu >= MAX_CPU) in kvmppc_mpic_connect_vcpu()
1786 * < 0 Interrupt was ignored (masked or not delivered for other reasons)
1787 * = 0 Interrupt was coalesced (previous irq is still pending)
1788 * > 0 Number of CPUs interrupt was delivered to
1803 return 0; in mpic_set_irq()
1822 return 0; in kvm_set_msi()
1849 r = 0; in kvm_set_routing_entry()