Lines Matching +full:0 +full:x10a0
16 #define _DKL_PHY1_BASE 0x168000
17 #define _DKL_PHY2_BASE 0x169000
18 #define _DKL_PHY3_BASE 0x16A000
19 #define _DKL_PHY4_BASE 0x16B000
20 #define _DKL_PHY5_BASE 0x16C000
21 #define _DKL_PHY6_BASE 0x16D000
37 (((phy_offset) >> _DKL_BANK_SHIFT) & 0xf)
49 #define _DKL_PCS_DW5_LN0 0x0014
50 #define _DKL_PCS_DW5_LN1 0x1014
56 #define _DKL_PLL_DIV0 0x2200
62 #define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16)
64 #define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12)
67 #define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
68 #define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
69 #define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0)
75 #define _DKL_PLL_DIV1 0x2204
79 #define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16)
80 #define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0)
81 #define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0)
83 #define _DKL_PLL_SSC 0x2210
87 #define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29)
89 #define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16)
91 #define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11)
94 #define _DKL_PLL_BIAS 0x2214
100 #define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT)
102 #define _DKL_PLL_TDC_COLDST_BIAS 0x2218
106 #define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8)
107 #define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0)
108 #define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0)
110 #define _DKL_REFCLKIN_CTL 0x212C
115 #define _DKL_CLKTOP2_HSCLKCTL 0x20D4
120 #define _DKL_CLKTOP2_CORECLKCTL1 0x20D8
125 #define _DKL_TX_DPCNTL0_LN0 0x02C0
126 #define _DKL_TX_DPCNTL0_LN1 0x12C0
131 #define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13)
133 #define DKL_TX_DE_EMPAHSIS_COEFF_MASK (0x1f << 8)
134 #define DKL_TX_VSWING_CONTROL(x) ((x) << 0)
135 #define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0)
137 #define _DKL_TX_DPCNTL1_LN0 0x02C4
138 #define _DKL_TX_DPCNTL1_LN1 0x12C4
144 #define _DKL_TX_DPCNTL2_LN0 0x02C8
145 #define _DKL_TX_DPCNTL2_LN1 0x12C8
155 #define _DKL_TX_FW_CALIB_LN0 0x02F8
156 #define _DKL_TX_FW_CALIB_LN1 0x12F8
162 #define _DKL_TX_PMD_LANE_SUS_LN0 0x0D00
163 #define _DKL_TX_PMD_LANE_SUS_LN1 0x1D00
168 #define _DKL_TX_DW17_LN0 0x0DC4
169 #define _DKL_TX_DW17_LN1 0x1DC4
174 #define _DKL_TX_DW18_LN0 0x0DC8
175 #define _DKL_TX_DW18_LN1 0x1DC8
180 #define _DKL_DP_MODE_LN0 0x00A0
181 #define _DKL_DP_MODE_LN1 0x10A0
186 #define _DKL_CMN_UC_DW27 0x236C
189 #define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15)
197 #define _HIP_INDEX_REG0 0x1010A0
198 #define _HIP_INDEX_REG1 0x1010A4