Lines Matching +full:0 +full:x10a0
35 #define SABRE_UE_AFSR 0x0030UL
36 #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
37 #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
38 #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
39 #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
40 #define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */
41 #define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */
42 #define SABRE_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */
43 #define SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */
44 #define SABRE_UEAFSR_BLK 0x0000000000800000UL /* Was block operation */
45 #define SABRE_UECE_AFAR 0x0038UL
46 #define SABRE_CE_AFSR 0x0040UL
47 #define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
48 #define SABRE_CEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
49 #define SABRE_CEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
50 #define SABRE_CEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
51 #define SABRE_CEAFSR_ESYND 0x00ff000000000000UL /* ECC Syndrome */
52 #define SABRE_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */
53 #define SABRE_CEAFSR_OFF 0x00000000e0000000UL /* Offset */
54 #define SABRE_CEAFSR_BLK 0x0000000000800000UL /* Was block operation */
55 #define SABRE_UECE_AFAR_ALIAS 0x0048UL /* Aliases to 0x0038 */
56 #define SABRE_IOMMU_CONTROL 0x0200UL
57 #define SABRE_IOMMUCTRL_ERRSTS 0x0000000006000000UL /* Error status bits */
58 #define SABRE_IOMMUCTRL_ERR 0x0000000001000000UL /* Error present in IOTLB */
59 #define SABRE_IOMMUCTRL_LCKEN 0x0000000000800000UL /* IOTLB lock enable */
60 #define SABRE_IOMMUCTRL_LCKPTR 0x0000000000780000UL /* IOTLB lock pointer */
61 #define SABRE_IOMMUCTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
62 #define SABRE_IOMMU_TSBSZ_1K 0x0000000000000000
63 #define SABRE_IOMMU_TSBSZ_2K 0x0000000000010000
64 #define SABRE_IOMMU_TSBSZ_4K 0x0000000000020000
65 #define SABRE_IOMMU_TSBSZ_8K 0x0000000000030000
66 #define SABRE_IOMMU_TSBSZ_16K 0x0000000000040000
67 #define SABRE_IOMMU_TSBSZ_32K 0x0000000000050000
68 #define SABRE_IOMMU_TSBSZ_64K 0x0000000000060000
69 #define SABRE_IOMMU_TSBSZ_128K 0x0000000000070000
70 #define SABRE_IOMMUCTRL_TBWSZ 0x0000000000000004UL /* TSB assumed page size */
71 #define SABRE_IOMMUCTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
72 #define SABRE_IOMMUCTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
73 #define SABRE_IOMMU_TSBBASE 0x0208UL
74 #define SABRE_IOMMU_FLUSH 0x0210UL
75 #define SABRE_IMAP_A_SLOT0 0x0c00UL
76 #define SABRE_IMAP_B_SLOT0 0x0c20UL
77 #define SABRE_IMAP_SCSI 0x1000UL
78 #define SABRE_IMAP_ETH 0x1008UL
79 #define SABRE_IMAP_BPP 0x1010UL
80 #define SABRE_IMAP_AU_REC 0x1018UL
81 #define SABRE_IMAP_AU_PLAY 0x1020UL
82 #define SABRE_IMAP_PFAIL 0x1028UL
83 #define SABRE_IMAP_KMS 0x1030UL
84 #define SABRE_IMAP_FLPY 0x1038UL
85 #define SABRE_IMAP_SHW 0x1040UL
86 #define SABRE_IMAP_KBD 0x1048UL
87 #define SABRE_IMAP_MS 0x1050UL
88 #define SABRE_IMAP_SER 0x1058UL
89 #define SABRE_IMAP_UE 0x1070UL
90 #define SABRE_IMAP_CE 0x1078UL
91 #define SABRE_IMAP_PCIERR 0x1080UL
92 #define SABRE_IMAP_GFX 0x1098UL
93 #define SABRE_IMAP_EUPA 0x10a0UL
94 #define SABRE_ICLR_A_SLOT0 0x1400UL
95 #define SABRE_ICLR_B_SLOT0 0x1480UL
96 #define SABRE_ICLR_SCSI 0x1800UL
97 #define SABRE_ICLR_ETH 0x1808UL
98 #define SABRE_ICLR_BPP 0x1810UL
99 #define SABRE_ICLR_AU_REC 0x1818UL
100 #define SABRE_ICLR_AU_PLAY 0x1820UL
101 #define SABRE_ICLR_PFAIL 0x1828UL
102 #define SABRE_ICLR_KMS 0x1830UL
103 #define SABRE_ICLR_FLPY 0x1838UL
104 #define SABRE_ICLR_SHW 0x1840UL
105 #define SABRE_ICLR_KBD 0x1848UL
106 #define SABRE_ICLR_MS 0x1850UL
107 #define SABRE_ICLR_SER 0x1858UL
108 #define SABRE_ICLR_UE 0x1870UL
109 #define SABRE_ICLR_CE 0x1878UL
110 #define SABRE_ICLR_PCIERR 0x1880UL
111 #define SABRE_WRSYNC 0x1c20UL
112 #define SABRE_PCICTRL 0x2000UL
113 #define SABRE_PCICTRL_MRLEN 0x0000001000000000UL /* Use MemoryReadLine for block loads/stores */
114 #define SABRE_PCICTRL_SERR 0x0000000400000000UL /* Set when SERR asserted on PCI bus */
115 #define SABRE_PCICTRL_ARBPARK 0x0000000000200000UL /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
116 #define SABRE_PCICTRL_CPUPRIO 0x0000000000100000UL /* Ultra-IIi granted every other bus cycle */
117 #define SABRE_PCICTRL_ARBPRIO 0x00000000000f0000UL /* Slot which is granted every other bus cycle…
118 #define SABRE_PCICTRL_ERREN 0x0000000000000100UL /* PCI Error Interrupt Enable */
119 #define SABRE_PCICTRL_RTRYWE 0x0000000000000080UL /* DMA Flow Control 0=wait-if-possible 1=retry …
120 #define SABRE_PCICTRL_AEN 0x000000000000000fUL /* Slot PCI arbitration enables */
121 #define SABRE_PIOAFSR 0x2010UL
122 #define SABRE_PIOAFSR_PMA 0x8000000000000000UL /* Primary Master Abort */
123 #define SABRE_PIOAFSR_PTA 0x4000000000000000UL /* Primary Target Abort */
124 #define SABRE_PIOAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
125 #define SABRE_PIOAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
126 #define SABRE_PIOAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort */
127 #define SABRE_PIOAFSR_STA 0x0400000000000000UL /* Secondary Target Abort */
128 #define SABRE_PIOAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
129 #define SABRE_PIOAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
130 #define SABRE_PIOAFSR_BMSK 0x0000ffff00000000UL /* Byte Mask */
131 #define SABRE_PIOAFSR_BLK 0x0000000080000000UL /* Was Block Operation */
132 #define SABRE_PIOAFAR 0x2018UL
133 #define SABRE_PCIDIAG 0x2020UL
134 #define SABRE_PCIDIAG_DRTRY 0x0000000000000040UL /* Disable PIO Retry Limit */
135 #define SABRE_PCIDIAG_IPAPAR 0x0000000000000008UL /* Invert PIO Address Parity */
136 #define SABRE_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO Data Parity */
137 #define SABRE_PCIDIAG_IDDPAR 0x0000000000000002UL /* Invert DMA Data Parity */
138 #define SABRE_PCIDIAG_ELPBK 0x0000000000000001UL /* Loopback Enable - not supported */
139 #define SABRE_PCITASR 0x2028UL
140 #define SABRE_PCITASR_EF 0x0000000000000080UL /* Respond to 0xe0000000-0xffffffff */
141 #define SABRE_PCITASR_CD 0x0000000000000040UL /* Respond to 0xc0000000-0xdfffffff */
142 #define SABRE_PCITASR_AB 0x0000000000000020UL /* Respond to 0xa0000000-0xbfffffff */
143 #define SABRE_PCITASR_89 0x0000000000000010UL /* Respond to 0x80000000-0x9fffffff */
144 #define SABRE_PCITASR_67 0x0000000000000008UL /* Respond to 0x60000000-0x7fffffff */
145 #define SABRE_PCITASR_45 0x0000000000000004UL /* Respond to 0x40000000-0x5fffffff */
146 #define SABRE_PCITASR_23 0x0000000000000002UL /* Respond to 0x20000000-0x3fffffff */
147 #define SABRE_PCITASR_01 0x0000000000000001UL /* Respond to 0x00000000-0x1fffffff */
148 #define SABRE_PIOBUF_DIAG 0x5000UL
149 #define SABRE_DMABUF_DIAGLO 0x5100UL
150 #define SABRE_DMABUF_DIAGHI 0x51c0UL
151 #define SABRE_IMAP_GFX_ALIAS 0x6000UL /* Aliases to 0x1098 */
152 #define SABRE_IMAP_EUPA_ALIAS 0x8000UL /* Aliases to 0x10a0 */
153 #define SABRE_IOMMU_VADIAG 0xa400UL
154 #define SABRE_IOMMU_TCDIAG 0xa408UL
155 #define SABRE_IOMMU_TAG 0xa580UL
156 #define SABRE_IOMMUTAG_ERRSTS 0x0000000001800000UL /* Error status bits */
157 #define SABRE_IOMMUTAG_ERR 0x0000000000400000UL /* Error present */
158 #define SABRE_IOMMUTAG_WRITE 0x0000000000200000UL /* Page is writable */
159 #define SABRE_IOMMUTAG_STREAM 0x0000000000100000UL /* Streamable bit - unused */
160 #define SABRE_IOMMUTAG_SIZE 0x0000000000080000UL /* 0=8k 1=16k */
161 #define SABRE_IOMMUTAG_VPN 0x000000000007ffffUL /* Virtual Page Number [31:13] */
162 #define SABRE_IOMMU_DATA 0xa600UL
163 #define SABRE_IOMMUDATA_VALID 0x0000000040000000UL /* Valid */
164 #define SABRE_IOMMUDATA_USED 0x0000000020000000UL /* Used (for LRU algorithm) */
165 #define SABRE_IOMMUDATA_CACHE 0x0000000010000000UL /* Cacheable */
166 #define SABRE_IOMMUDATA_PPN 0x00000000001fffffUL /* Physical Page Number [33:13] */
167 #define SABRE_PCI_IRQSTATE 0xa800UL
168 #define SABRE_OBIO_IRQSTATE 0xa808UL
169 #define SABRE_FFBCFG 0xf000UL
170 #define SABRE_FFBCFG_SPRQS 0x000000000f000000 /* Slave P_RQST queue size */
171 #define SABRE_FFBCFG_ONEREAD 0x0000000000004000 /* Slave supports one outstanding read */
172 #define SABRE_MCCTRL0 0xf010UL
173 #define SABRE_MCCTRL0_RENAB 0x0000000080000000 /* Refresh Enable */
174 #define SABRE_MCCTRL0_EENAB 0x0000000010000000 /* Enable all ECC functions */
175 #define SABRE_MCCTRL0_11BIT 0x0000000000001000 /* Enable 11-bit column addressing */
176 #define SABRE_MCCTRL0_DPP 0x0000000000000f00 /* DIMM Pair Present Bits */
177 #define SABRE_MCCTRL0_RINTVL 0x00000000000000ff /* Refresh Interval */
178 #define SABRE_MCCTRL1 0xf018UL
179 #define SABRE_MCCTRL1_AMDC 0x0000000038000000 /* Advance Memdata Clock */
180 #define SABRE_MCCTRL1_ARDC 0x0000000007000000 /* Advance DRAM Read Data Clock */
181 #define SABRE_MCCTRL1_CSR 0x0000000000e00000 /* CAS to RAS delay for CBR refresh */
182 #define SABRE_MCCTRL1_CASRW 0x00000000001c0000 /* CAS length for read/write */
183 #define SABRE_MCCTRL1_RCD 0x0000000000038000 /* RAS to CAS delay */
184 #define SABRE_MCCTRL1_CP 0x0000000000007000 /* CAS Precharge */
185 #define SABRE_MCCTRL1_RP 0x0000000000000e00 /* RAS Precharge */
186 #define SABRE_MCCTRL1_RAS 0x00000000000001c0 /* Length of RAS for refresh */
187 #define SABRE_MCCTRL1_CASRW2 0x0000000000000038 /* Must be same as CASRW */
188 #define SABRE_MCCTRL1_RSC 0x0000000000000007 /* RAS after CAS hold time */
189 #define SABRE_RESETCTRL 0xf020UL
191 #define SABRE_CONFIGSPACE 0x001000000UL
192 #define SABRE_IOSPACE 0x002000000UL
193 #define SABRE_IOSPACE_SIZE 0x000ffffffUL
194 #define SABRE_MEMSPACE 0x100000000UL
195 #define SABRE_MEMSPACE_SIZE 0x07fffffffUL
234 ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0)); in sabre_ue_intr()
237 reported = 0; in sabre_ue_intr()
297 ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0)); in sabre_ce_intr()
300 reported = 0; in sabre_ce_intr()
332 * 0: PCI ERR in sabre_register_error_handlers()
349 err = request_irq(op->archdata.irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm); in sabre_register_error_handlers()
359 err = request_irq(op->archdata.irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm); in sabre_register_error_handlers()
363 err = request_irq(op->archdata.irqs[0], psycho_pcierr_intr, 0, in sabre_register_error_handlers()
390 pci_write_config_word(pdev, PCI_STATUS, 0xffff); in apb_init()
391 pci_write_config_word(pdev, PCI_SEC_STATUS, 0xffff); in apb_init()
424 pbm->is_66mhz_capable = 0; in sabre_scan_bus()
430 * to live at bus 0. in sabre_scan_bus()
432 if (once != 0) { in sabre_scan_bus()
499 upa_portid = of_getintprop_default(dp, "upa-portid", 0xff); in sabre_probe()
517 pbm->controller_regs = pr_regs[0].phys_addr; in sabre_probe()
522 for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8) in sabre_probe()
523 upa_writeq(0x0UL, pbm->controller_regs + clear_irq); in sabre_probe()
526 for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8) in sabre_probe()
527 upa_writeq(0x0UL, pbm->controller_regs + clear_irq); in sabre_probe()
543 dma_mask = vdma[0]; in sabre_probe()
545 case 0x20000000: in sabre_probe()
546 dma_mask |= 0x1fffffff; in sabre_probe()
549 case 0x40000000: in sabre_probe()
550 dma_mask |= 0x3fffffff; in sabre_probe()
554 case 0x80000000: in sabre_probe()
555 dma_mask |= 0x7fffffff; in sabre_probe()
563 err = psycho_iommu_init(pbm, tsbsize, vdma[0], dma_mask, SABRE_WRSYNC); in sabre_probe()
577 return 0; in sabre_probe()