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/linux-6.12.1/arch/sh/boards/mach-se/7206/
Dirq.c16 #define INTSTS0 0x31800000
17 #define INTSTS1 0x31800002
18 #define INTMSK0 0x31800004
19 #define INTMSK1 0x31800006
20 #define INTSEL 0x31800008
26 #define INTC_IPR01 0xfffe0818
27 #define INTC_ICR1 0xfffe0802
33 unsigned short mask = 0xffff ^ (0x0f << 4 * (3 - (IRQ0_IRQ - irq))); in disable_se7206_irq()
36 /* Set the priority in IPR to 0 */ in disable_se7206_irq()
46 msk0 |= 0x0010; in disable_se7206_irq()
[all …]
/linux-6.12.1/arch/arm/boot/dts/broadcom/
Dbcm11351.dtsi21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
33 secondary-boot-reg = <0x3500417c>;
41 #address-cells = <0>;
43 reg = <0x3ff01000 0x1000>,
44 <0x3ff00100 0x100>;
49 reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
54 reg = <0x3e000000 0x1000>;
64 reg = <0x3e001000 0x1000>;
[all …]
Dbcm2166x-common.dtsi22 ranges = <0 0x34000000 0x102f83ac>;
28 reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
33 reg = <0x01001f00 0x24>;
38 reg = <0x01003000 0x524>;
51 reg = <0x01006000 0x1c>;
60 ranges = <0 0x3e000000 0x0001c070>;
64 uartb: serial@0 {
66 reg = <0x00000000 0x118>;
76 reg = <0x00001000 0x118>;
86 reg = <0x00002000 0x118>;
[all …]
/linux-6.12.1/include/linux/mfd/wm8350/
Dgpio.h16 #define WM8350_GPIO_DEBOUNCE 0x80
17 #define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81
18 #define WM8350_GPIO_PULL_DOWN_CONTROL 0x82
19 #define WM8350_GPIO_INT_MODE 0x83
20 #define WM8350_GPIO_CONTROL 0x85
21 #define WM8350_GPIO_CONFIGURATION_I_O 0x86
22 #define WM8350_GPIO_PIN_POLARITY_TYPE 0x87
23 #define WM8350_GPIO_FUNCTION_SELECT_1 0x8C
24 #define WM8350_GPIO_FUNCTION_SELECT_2 0x8D
25 #define WM8350_GPIO_FUNCTION_SELECT_3 0x8E
[all …]
Dsupply.h17 #define WM8350_BATTERY_CHARGER_CONTROL_1 0xA8
18 #define WM8350_BATTERY_CHARGER_CONTROL_2 0xA9
19 #define WM8350_BATTERY_CHARGER_CONTROL_3 0xAA
22 * R168 (0xA8) - Battery Charger Control 1
24 #define WM8350_CHG_ENA_R168 0x8000
25 #define WM8350_CHG_THR 0x2000
26 #define WM8350_CHG_EOC_SEL_MASK 0x1C00
27 #define WM8350_CHG_TRICKLE_TEMP_CHOKE 0x0200
28 #define WM8350_CHG_TRICKLE_USB_CHOKE 0x0100
29 #define WM8350_CHG_RECOVER_T 0x0080
[all …]
/linux-6.12.1/drivers/net/wireless/broadcom/b43/
Dwa.c24 b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9); in b43_wa_initgains()
25 b43_phy_mask(dev, B43_PHY_LPFGAINCTL, 0xFF0F); in b43_wa_initgains()
27 b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF); in b43_wa_initgains()
28 b43_radio_write16(dev, 0x0002, 0x1FBF); in b43_wa_initgains()
30 b43_phy_write(dev, 0x0024, 0x4680); in b43_wa_initgains()
31 b43_phy_write(dev, 0x0020, 0x0003); in b43_wa_initgains()
32 b43_phy_write(dev, 0x001D, 0x0F40); in b43_wa_initgains()
33 b43_phy_write(dev, 0x001F, 0x1C00); in b43_wa_initgains()
35 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x0400); in b43_wa_initgains()
37 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x1A00); in b43_wa_initgains()
[all …]
/linux-6.12.1/arch/x86/boot/
Dvideo.h25 * of compatibility when extending the table. These are between 0x00 and 0xff.
27 #define VIDEO_FIRST_MENU 0x0000
29 /* Standard BIOS video modes (BIOS number + 0x0100) */
30 #define VIDEO_FIRST_BIOS 0x0100
32 /* VESA BIOS video modes (VESA number + 0x0200) */
33 #define VIDEO_FIRST_VESA 0x0200
35 /* Video7 special modes (BIOS number + 0x0900) */
36 #define VIDEO_FIRST_V7 0x0900
39 #define VIDEO_FIRST_SPECIAL 0x0f00
40 #define VIDEO_80x25 0x0f00
[all …]
/linux-6.12.1/arch/sh/kernel/
Dtraps_32.c52 if ((count == 1) && dst[0] & 0x80) { in sign_extend()
53 dst[1] = 0xff; in sign_extend()
54 dst[2] = 0xff; in sign_extend()
55 dst[3] = 0xff; in sign_extend()
57 if ((count == 2) && dst[1] & 0x80) { in sign_extend()
58 dst[2] = 0xff; in sign_extend()
59 dst[3] = 0xff; in sign_extend()
62 if ((count == 1) && dst[3] & 0x80) { in sign_extend()
63 dst[2] = 0xff; in sign_extend()
64 dst[1] = 0xff; in sign_extend()
[all …]
/linux-6.12.1/Documentation/admin-guide/
Dsvga.rst37 0..35 - Menu item number (when you have used the menu to view the list of
39 to use). 0..9 correspond to "0".."9", 10..35 to "a".."z". Warning: the
44 0x.... - Hexadecimal video mode ID (also displayed on the menu, see below
61 0 0F00 80x25
62 1 0F01 80x50
63 2 0F02 80x43
64 3 0F03 80x26
74 "0 0F00 80x25" means that the first menu item (the menu items are numbered
75 from "0" to "9" and from "a" to "z") is a 80x25 mode with ID=0x0f00 (see the
112 expressed in a hexadecimal notation (starting with "0x"). You can set a mode
[all …]
/linux-6.12.1/lib/
Dbitfield_kunit.c17 "u" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != " #res "\n", \
22 } while (0)
31 "le" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != 0x%llx",\
37 } while (0)
46 "be" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != 0x%llx", \
52 } while (0)
58 } while (0)
68 CHECK_ENC_GET(16, 1, 0x000f, 0x0001); in test_bitfields_constants()
69 CHECK_ENC_GET(16, 3, 0x00f0, 0x0030); in test_bitfields_constants()
70 CHECK_ENC_GET(16, 5, 0x0f00, 0x0500); in test_bitfields_constants()
[all …]
/linux-6.12.1/drivers/net/dsa/mv88e6xxx/
Dglobal2.h16 /* Offset 0x00: Interrupt Source Register */
17 #define MV88E6XXX_G2_INT_SRC 0x00
18 #define MV88E6XXX_G2_INT_SRC_WDOG 0x8000
19 #define MV88E6XXX_G2_INT_SRC_JAM_LIMIT 0x4000
20 #define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH 0x2000
21 #define MV88E6XXX_G2_INT_SRC_WAKE_EVENT 0x1000
22 #define MV88E6352_G2_INT_SRC_SERDES 0x0800
23 #define MV88E6352_G2_INT_SRC_PHY 0x001f
24 #define MV88E6390_G2_INT_SRC_PHY 0x07fe
28 /* Offset 0x01: Interrupt Mask Register */
[all …]
Dport.h16 /* Offset 0x00: Port Status Register */
17 #define MV88E6XXX_PORT_STS 0x00
18 #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
19 #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
20 #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
21 #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
22 #define MV88E6250_PORT_STS_LINK 0x1000
23 #define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00
24 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800
25 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
[all …]
/linux-6.12.1/drivers/video/backlight/
Dlms283gf05.c33 { 0x07, 0x0000, 0 },
34 { 0x13, 0x0000, 10 },
36 { 0x11, 0x3004, 0 },
37 { 0x14, 0x200F, 0 },
38 { 0x10, 0x1a20, 0 },
39 { 0x13, 0x0040, 50 },
41 { 0x13, 0x0060, 0 },
42 { 0x13, 0x0070, 200 },
44 { 0x01, 0x0127, 0 },
45 { 0x02, 0x0700, 0 },
[all …]
/linux-6.12.1/drivers/phy/cadence/
Dphy-cadence-torrent.c36 #define DP_PLL0 BIT(0)
39 #define TORRENT_COMMON_CDB_OFFSET 0x0
42 ((0x4000 << (block_offset)) + \
46 ((0x8000 << (block_offset)) + \
50 (0xC000 << (block_offset))
53 ((0xD000 << (block_offset)) + \
57 (0xE000 << (block_offset))
59 #define TORRENT_DPTX_PHY_OFFSET 0x0
63 * register base + 0x30a00)
65 #define PHY_AUX_CTRL 0x04
[all …]
/linux-6.12.1/drivers/staging/rtl8712/
Drtl8712_debugctrl_bitdef.h11 #define _BIST_RST BIT(0)
14 #define _LMS_MSK 0x03
17 #define _OVSEL_MSK 0x0600
20 #define _WDGEN_MSK 0x00FF
21 #define _WDGEN_SHT 0
24 #define _TXTIMER_MSK 0xF000
26 #define _TXNUM_MSK 0x0F00
28 #define _RXTIMER_MSK 0x00F0
30 #define _RXNUM_MSK 0x000F
31 #define _RXNUM_SHT 0
[all …]
/linux-6.12.1/arch/arm/mach-omap2/
Dcm2_7xx.h23 #define DRA7XX_CM_CORE_BASE 0x4a008000
29 #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_CKGEN_INST 0x0104
31 #define DRA7XX_CM_CORE_COREAON_INST 0x0600
32 #define DRA7XX_CM_CORE_CORE_INST 0x0700
33 #define DRA7XX_CM_CORE_IVA_INST 0x0f00
34 #define DRA7XX_CM_CORE_CAM_INST 0x1000
35 #define DRA7XX_CM_CORE_DSS_INST 0x1100
36 #define DRA7XX_CM_CORE_GPU_INST 0x1200
37 #define DRA7XX_CM_CORE_L3INIT_INST 0x1300
[all …]
Dcm2_44xx.h26 #define OMAP4430_CM2_BASE 0x4a008000
32 #define OMAP4430_CM2_OCP_SOCKET_INST 0x0000
33 #define OMAP4430_CM2_CKGEN_INST 0x0100
34 #define OMAP4430_CM2_ALWAYS_ON_INST 0x0600
35 #define OMAP4430_CM2_CORE_INST 0x0700
36 #define OMAP4430_CM2_IVAHD_INST 0x0f00
37 #define OMAP4430_CM2_CAM_INST 0x1000
38 #define OMAP4430_CM2_DSS_INST 0x1100
39 #define OMAP4430_CM2_GFX_INST 0x1200
40 #define OMAP4430_CM2_L3INIT_INST 0x1300
[all …]
Dprm7xx.h26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x1000
[all …]
Dprm33xx.h14 #define AM33XX_PRM_BASE 0x44E00000
21 #define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
22 #define AM33XX_PRM_PER_MOD 0x0C00
23 #define AM33XX_PRM_WKUP_MOD 0x0D00
24 #define AM33XX_PRM_MPU_MOD 0x0E00
25 #define AM33XX_PRM_DEVICE_MOD 0x0F00
26 #define AM33XX_PRM_RTC_MOD 0x1000
27 #define AM33XX_PRM_GFX_MOD 0x1100
28 #define AM33XX_PRM_CEFUSE_MOD 0x1200
31 #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
[all …]
Dprm44xx.h28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
/linux-6.12.1/drivers/staging/media/av7110/
Dsp8870.c49 } while (0)
55 #define SP8870_FIRMWARE_OFFSET 0x0A
59 u8 buf[] = { reg >> 8, reg & 0xff, data >> 8, data & 0xff }; in sp8870_writereg()
62 .flags = 0, in sp8870_writereg()
71 dprintk("writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", err, reg, data); in sp8870_writereg()
75 return 0; in sp8870_writereg()
81 u8 b0[] = { reg >> 8, reg & 0xff }; in sp8870_readreg()
82 u8 b1[] = { 0, 0 }; in sp8870_readreg()
84 { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 }, in sp8870_readreg()
95 return (b1[0] << 8 | b1[1]); in sp8870_readreg()
[all …]
/linux-6.12.1/drivers/tty/serial/
Dsh-sci.h43 #define SCSMR_ASYNC 0 /* - Asynchronous mode */
48 #define SCSMR_CKS 0x0003 /* Clock Select */
52 #define SCSMR_SRC_MASK 0x0700 /* Sampling Control */
53 #define SCSMR_SRC_16 0x0000 /* Sampling rate 1/16 */
54 #define SCSMR_SRC_5 0x0100 /* Sampling rate 1/5 */
55 #define SCSMR_SRC_7 0x0200 /* Sampling rate 1/7 */
56 #define SCSMR_SRC_11 0x0300 /* Sampling rate 1/11 */
57 #define SCSMR_SRC_13 0x0400 /* Sampling rate 1/13 */
58 #define SCSMR_SRC_17 0x0500 /* Sampling rate 1/17 */
59 #define SCSMR_SRC_19 0x0600 /* Sampling rate 1/19 */
[all …]
/linux-6.12.1/drivers/net/ethernet/chelsio/cxgb4/
Dcxgb4_tc_u32_parse.h48 f->val.tos = (ntohl(val) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_tos()
49 f->mask.tos = (ntohl(mask) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_tos()
51 return 0; in cxgb4_fill_ipv4_tos()
60 frag_val = (ntohl(val) >> 13) & 0x00000007; in cxgb4_fill_ipv4_frag()
61 mask_val = ntohl(mask) & 0x0000FFFF; in cxgb4_fill_ipv4_frag()
63 if (frag_val == 0x1 && mask_val != 0x3FFF) { /* MF set */ in cxgb4_fill_ipv4_frag()
66 } else if (frag_val == 0x2 && mask_val != 0x3FFF) { /* DF set */ in cxgb4_fill_ipv4_frag()
67 f->val.frag = 0; in cxgb4_fill_ipv4_frag()
73 return 0; in cxgb4_fill_ipv4_frag()
79 f->val.proto = (ntohl(val) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_proto()
[all …]
/linux-6.12.1/arch/m68k/include/asm/
Dmcfpit.h18 #define MCFPIT_PCSR 0x0 /* PIT control register */
19 #define MCFPIT_PMR 0x2 /* PIT modulus register */
20 #define MCFPIT_PCNTR 0x4 /* PIT count register */
25 #define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */
26 #define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */
27 #define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */
28 #define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */
29 #define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */
30 #define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */
31 #define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */
[all …]
/linux-6.12.1/sound/soc/codecs/
Dwm9090.h16 #define WM9090_SOFTWARE_RESET 0x00
17 #define WM9090_POWER_MANAGEMENT_1 0x01
18 #define WM9090_POWER_MANAGEMENT_2 0x02
19 #define WM9090_POWER_MANAGEMENT_3 0x03
20 #define WM9090_CLOCKING_1 0x06
21 #define WM9090_IN1_LINE_CONTROL 0x16
22 #define WM9090_IN2_LINE_CONTROL 0x17
23 #define WM9090_IN1_LINE_INPUT_A_VOLUME 0x18
24 #define WM9090_IN1_LINE_INPUT_B_VOLUME 0x19
25 #define WM9090_IN2_LINE_INPUT_A_VOLUME 0x1A
[all …]

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