16 #define INTSTS0 0x31800000
17 #define INTSTS1 0x31800002
18 #define INTMSK0 0x31800004
19 #define INTMSK1 0x31800006
20 #define INTSEL  0x31800008
26 #define INTC_IPR01 0xfffe0818
27 #define INTC_ICR1  0xfffe0802
33 	unsigned short mask = 0xffff ^ (0x0f << 4 * (3 - (IRQ0_IRQ - irq)));  in disable_se7206_irq()
36 	/* Set the priority in IPR to 0 */  in disable_se7206_irq()
46 		msk0 |= 0x0010;  in disable_se7206_irq()
49 		msk0 |= 0x000f;  in disable_se7206_irq()
52 		msk0 |= 0x0f00;  in disable_se7206_irq()
53 		msk1 |= 0x00ff;  in disable_se7206_irq()
64 	unsigned short value = (0x0001 << 4 * (3 - (IRQ0_IRQ - irq)));  in enable_se7206_irq()
78 		msk0 &= ~0x0010;  in enable_se7206_irq()
81 		msk0 &= ~0x000f;  in enable_se7206_irq()
84 		msk0 &= ~0x0f00;  in enable_se7206_irq()
85 		msk1 &= ~0x00ff;  in enable_se7206_irq()
105 		sts0 &= ~0x0010;  in eoi_se7206_irq()
108 		sts0 &= ~0x000f;  in eoi_se7206_irq()
111 		sts0 &= ~0x0f00;  in eoi_se7206_irq()
112 		sts1 &= ~0x00ff;  in eoi_se7206_irq()
143 	__raw_writew(__raw_readw(INTC_ICR1) | 0x000b, INTC_ICR1); /* ICR1 */  in init_se7206_IRQ()
146 	__raw_writew(0x0000,INTSTS0); /* Clear INTSTS0 */  in init_se7206_IRQ()
147 	__raw_writew(0x0000,INTSTS1); /* Clear INTSTS1 */  in init_se7206_IRQ()
150 	__raw_writew(0x0001,INTSEL);  in init_se7206_IRQ()