Lines Matching +full:0 +full:x0f00

43 #define SCSMR_ASYNC	0	/*   - Asynchronous mode */
48 #define SCSMR_CKS	0x0003	/* Clock Select */
52 #define SCSMR_SRC_MASK	0x0700	/* Sampling Control */
53 #define SCSMR_SRC_16	0x0000	/* Sampling rate 1/16 */
54 #define SCSMR_SRC_5	0x0100	/* Sampling rate 1/5 */
55 #define SCSMR_SRC_7	0x0200	/* Sampling rate 1/7 */
56 #define SCSMR_SRC_11	0x0300	/* Sampling rate 1/11 */
57 #define SCSMR_SRC_13	0x0400	/* Sampling rate 1/13 */
58 #define SCSMR_SRC_17	0x0500	/* Sampling rate 1/17 */
59 #define SCSMR_SRC_19	0x0600	/* Sampling rate 1/19 */
60 #define SCSMR_SRC_27	0x0700	/* Sampling rate 1/27 */
79 #define SCI_RESERVED	0x03	/* All reserved bits */
96 #define SCIF_DR		BIT(0)	/* Receive Data Ready */
98 #define SCIF_PERC	0xf000	/* Number of Parity Errors */
99 #define SCIF_FERC	0x0f00	/* Number of Framing Errors */
118 #define SCFCR_LOOP	BIT(0)	/* Loopback Test */
122 #define SCLSR_ORER	BIT(0)	/* Overrun Error */
132 #define SCSPTR_SPB2DT	BIT(0)	/* Serial Port Break Data */
139 #define HSCIF_SRHP_MASK		0x0f00
146 #define SCPCR_TXDC	BIT(0)	/* Serial Port TXD Pin / Output Pin */
153 #define SCPDR_TXDD	BIT(0)	/* Serial Port TXD Output Pin Data */
161 #define SCCKS_CKS	BIT(15)	/* Select (H)SCK (1) or divided SC_CLK (0) */
162 #define SCCKS_XIN	BIT(14)	/* SC_CLK uses bus clock (1) or SCIF_CLK (0) */
169 #define SCxSR_BRK(port)		(((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK)