24 	b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9);  in b43_wa_initgains()
25 	b43_phy_mask(dev, B43_PHY_LPFGAINCTL, 0xFF0F);  in b43_wa_initgains()
27 		b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF);  in b43_wa_initgains()
28 	b43_radio_write16(dev, 0x0002, 0x1FBF);  in b43_wa_initgains()
30 	b43_phy_write(dev, 0x0024, 0x4680);  in b43_wa_initgains()
31 	b43_phy_write(dev, 0x0020, 0x0003);  in b43_wa_initgains()
32 	b43_phy_write(dev, 0x001D, 0x0F40);  in b43_wa_initgains()
33 	b43_phy_write(dev, 0x001F, 0x1C00);  in b43_wa_initgains()
35 		b43_phy_maskset(dev, 0x002A, 0x00FF, 0x0400);  in b43_wa_initgains()
37 		b43_phy_maskset(dev, 0x002A, 0x00FF, 0x1A00);  in b43_wa_initgains()
38 		b43_phy_write(dev, 0x00CC, 0x2121);  in b43_wa_initgains()
41 		b43_phy_write(dev, 0x00BA, 0x3ED5);  in b43_wa_initgains()
48 	if (0 /* FIXME: For APHY.rev=2 this might be needed */) {  in b43_wa_rssi_lt()
49 		for (i = 0; i < 8; i++)  in b43_wa_rssi_lt()
54 		for (i = 0; i < 64; i++)  in b43_wa_rssi_lt()
65 		b43_phy_write(dev, B43_PHY_PWRDOWN, 0x1000);  in b43_wa_analog()
67 		b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 3, 0x1044);  in b43_wa_analog()
68 		b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 4, 0x7201);  in b43_wa_analog()
69 		b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 6, 0x0040);  in b43_wa_analog()
77 	for (i = 0; i < B43_TAB_FINEFREQG_SIZE; i++)  in b43_wa_fft()
88 		for (i = 0; i < B43_TAB_NOISEG1_SIZE; i++)  in b43_wa_nft()
92 		for (i = 0; i < B43_TAB_NOISEG2_SIZE; i++)  in b43_wa_nft()
101 	for (i = 0; i < B43_TAB_ROTOR_SIZE; i++)  in b43_wa_rt()
109 	for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)  in b43_write_nst()
131 	for (i = 0; i < B43_TAB_RETARD_SIZE; i++)  in b43_wa_art()
149 	for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++) {  in b43_wa_msst()
160 		b43_phy_write(dev, B43_PHY_CRSTHRES1_R1, 0x4F19);  in b43_wa_crs_ed()
162 		b43_phy_write(dev, B43_PHY_CRSTHRES1, 0x1861);  in b43_wa_crs_ed()
163 		b43_phy_write(dev, B43_PHY_CRSTHRES2, 0x0271);  in b43_wa_crs_ed()
164 		b43_phy_set(dev, B43_PHY_ANTDWELL, 0x0800);  in b43_wa_crs_ed()
166 		b43_phy_write(dev, B43_PHY_CRSTHRES1, 0x0098);  in b43_wa_crs_ed()
167 		b43_phy_write(dev, B43_PHY_CRSTHRES2, 0x0070);  in b43_wa_crs_ed()
168 		b43_phy_write(dev, B43_PHY_OFDM(0xC9), 0x0080);  in b43_wa_crs_ed()
169 		b43_phy_set(dev, B43_PHY_ANTDWELL, 0x0800);  in b43_wa_crs_ed()
175 	b43_phy_maskset(dev, B43_PHY_CRS0, ~0x03C0, 0xD000);  in b43_wa_crs_thr()
180 	b43_phy_write(dev, B43_PHY_OFDM(0x2C), 0x005A);  in b43_wa_crs_blank()
185 	b43_phy_write(dev, B43_PHY_CCKSHIFTBITS, 0x0026);  in b43_wa_cck_shiftbits()
193 		for (i = 0; i < 16; i++) {  in b43_wa_wrssi_offset()
195 						i, 0x0020);  in b43_wa_wrssi_offset()
198 		for (i = 0; i < 32; i++) {  in b43_wa_wrssi_offset()
200 						i, 0x0820);  in b43_wa_wrssi_offset()
216 		b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 254);  in b43_wa_altagc()
220 		b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 0, 0x2710);  in b43_wa_altagc()
221 		b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 1, 0x9B83);  in b43_wa_altagc()
222 		b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 2, 0x9B83);  in b43_wa_altagc()
223 		b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 3, 0x0F8D);  in b43_wa_altagc()
226 		b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0, 254);  in b43_wa_altagc()
232 	b43_phy_maskset(dev, B43_PHY_CCKSHIFTBITS_WA, 0x00FF, 0x5700);  in b43_wa_altagc()
233 	b43_phy_maskset(dev, B43_PHY_OFDM(0x1A), ~0x007F, 0x000F);  in b43_wa_altagc()
234 	b43_phy_maskset(dev, B43_PHY_OFDM(0x1A), ~0x3F80, 0x2B80);  in b43_wa_altagc()
235 	b43_phy_maskset(dev, B43_PHY_ANTWRSETT, 0xF0FF, 0x0300);  in b43_wa_altagc()
236 	b43_radio_set(dev, 0x7A, 0x0008);  in b43_wa_altagc()
237 	b43_phy_maskset(dev, B43_PHY_N1P1GAIN, ~0x000F, 0x0008);  in b43_wa_altagc()
238 	b43_phy_maskset(dev, B43_PHY_P1P2GAIN, ~0x0F00, 0x0600);  in b43_wa_altagc()
239 	b43_phy_maskset(dev, B43_PHY_N1N2GAIN, ~0x0F00, 0x0700);  in b43_wa_altagc()
240 	b43_phy_maskset(dev, B43_PHY_N1P1GAIN, ~0x0F00, 0x0100);  in b43_wa_altagc()
242 		b43_phy_maskset(dev, B43_PHY_N1N2GAIN, ~0x000F, 0x0007);  in b43_wa_altagc()
244 	b43_phy_maskset(dev, B43_PHY_OFDM(0x88), ~0x00FF, 0x001C);  in b43_wa_altagc()
245 	b43_phy_maskset(dev, B43_PHY_OFDM(0x88), ~0x3F00, 0x0200);  in b43_wa_altagc()
246 	b43_phy_maskset(dev, B43_PHY_OFDM(0x96), ~0x00FF, 0x001C);  in b43_wa_altagc()
247 	b43_phy_maskset(dev, B43_PHY_OFDM(0x89), ~0x00FF, 0x0020);  in b43_wa_altagc()
248 	b43_phy_maskset(dev, B43_PHY_OFDM(0x89), ~0x3F00, 0x0200);  in b43_wa_altagc()
249 	b43_phy_maskset(dev, B43_PHY_OFDM(0x82), ~0x00FF, 0x002E);  in b43_wa_altagc()
250 	b43_phy_maskset(dev, B43_PHY_OFDM(0x96), 0x00FF, 0x1A00);  in b43_wa_altagc()
251 	b43_phy_maskset(dev, B43_PHY_OFDM(0x81), ~0x00FF, 0x0028);  in b43_wa_altagc()
252 	b43_phy_maskset(dev, B43_PHY_OFDM(0x81), 0x00FF, 0x2C00);  in b43_wa_altagc()
254 		b43_phy_write(dev, B43_PHY_PEAK_COUNT, 0x092B);  in b43_wa_altagc()
255 		b43_phy_maskset(dev, B43_PHY_OFDM(0x1B), ~0x001E, 0x0002);  in b43_wa_altagc()
257 		b43_phy_mask(dev, B43_PHY_OFDM(0x1B), ~0x001E);  in b43_wa_altagc()
258 		b43_phy_write(dev, B43_PHY_OFDM(0x1F), 0x287A);  in b43_wa_altagc()
259 		b43_phy_maskset(dev, B43_PHY_LPFGAINCTL, ~0x000F, 0x0004);  in b43_wa_altagc()
261 			b43_phy_write(dev, B43_PHY_OFDM(0x22), 0x287A);  in b43_wa_altagc()
262 			b43_phy_maskset(dev, B43_PHY_LPFGAINCTL, 0x0FFF, 0x3000);  in b43_wa_altagc()
265 	b43_phy_maskset(dev, B43_PHY_DIVSRCHIDX, 0x8080, 0x7874);  in b43_wa_altagc()
266 	b43_phy_write(dev, B43_PHY_OFDM(0x8E), 0x1C00);  in b43_wa_altagc()
268 		b43_phy_maskset(dev, B43_PHY_DIVP1P2GAIN, ~0x0F00, 0x0600);  in b43_wa_altagc()
269 		b43_phy_write(dev, B43_PHY_OFDM(0x8B), 0x005E);  in b43_wa_altagc()
270 		b43_phy_maskset(dev, B43_PHY_ANTWRSETT, ~0x00FF, 0x001E);  in b43_wa_altagc()
271 		b43_phy_write(dev, B43_PHY_OFDM(0x8D), 0x0002);  in b43_wa_altagc()
272 		b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 0, 0);  in b43_wa_altagc()
277 		b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 0, 0);  in b43_wa_altagc()
283 		b43_phy_mask(dev, B43_PHY_OFDM(0x26), ~0x0003);  in b43_wa_altagc()
284 		b43_phy_mask(dev, B43_PHY_OFDM(0x26), ~0x1000);  in b43_wa_altagc()
291 	b43_gtab_write(dev, B43_GTAB_ORIGTR, 0, 0x7654);  in b43_wa_tr_ltov()
296 	b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_11, 0, 0);  in b43_wa_cpll_nonpilot()
297 	b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_11, 1, 0);  in b43_wa_cpll_nonpilot()
307 	    dev->dev->board_rev != 0x17) {  in b43_wa_boards_g()
309 			b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 1, 0x0002);  in b43_wa_boards_g()
310 			b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 2, 0x0001);  in b43_wa_boards_g()
312 			b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 1, 0x0002);  in b43_wa_boards_g()
313 			b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 2, 0x0001);  in b43_wa_boards_g()
316 				b43_phy_mask(dev, B43_PHY_EXTG(0x11), 0xF7FF);  in b43_wa_boards_g()
317 				b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0020, 0x0001);  in b43_wa_boards_g()
318 				b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0021, 0x0001);  in b43_wa_boards_g()
319 				b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0022, 0x0001);  in b43_wa_boards_g()
320 				b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0023, 0x0000);  in b43_wa_boards_g()
321 				b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0000, 0x0000);  in b43_wa_boards_g()
322 				b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0003, 0x0002);  in b43_wa_boards_g()
327 		b43_phy_write(dev, B43_PHY_GTABCTL, 0x3120);  in b43_wa_boards_g()
328 		b43_phy_write(dev, B43_PHY_GTABDATA, 0xC480);  in b43_wa_boards_g()