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/linux-6.12.1/drivers/net/wireless/realtek/rtw89/
Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
Drtw8852a_table.c10 {0xF0FF0001, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03500FF, 0x00000002},
13 {0xF03200FF, 0x00000003},
14 {0xF03400FF, 0x00000004},
15 {0xF03600FF, 0x00000005},
16 {0x704, 0x601E0100},
17 {0x714, 0x00000000},
18 {0x718, 0x13332333},
19 {0x714, 0x00010000},
[all …]
Drtw8852bt_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x0000000f, 0x4),
9 RTW89_DECL_RFK_WM(0x32a8, 0x0000000f, 0x4),
10 RTW89_DECL_RFK_WM(0x12bc, 0x000ffff0, 0x5555),
11 RTW89_DECL_RFK_WM(0x32bc, 0x000ffff0, 0x5555),
12 RTW89_DECL_RFK_WM(0x0300, 0xff000000, 0x16),
13 RTW89_DECL_RFK_WM(0x0304, 0x000000ff, 0x19),
14 RTW89_DECL_RFK_WM(0x0314, 0xffff0000, 0x2041),
15 RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x2041),
16 RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x20012041),
17 RTW89_DECL_RFK_WM(0x0020, 0x00006000, 0x3),
[all …]
Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x0),
18 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x1),
24 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x0),
25 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x1),
31 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
32 RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1),
[all …]
Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
/linux-6.12.1/include/net/
Dieee80211_radiotap.h29 * @it_version: radiotap version, always 0
58 /* version is always 0 */
59 #define PKTHDR_RADIOTAP_VERSION 0
63 IEEE80211_RADIOTAP_TSFT = 0,
102 IEEE80211_RADIOTAP_F_CFP = 0x01,
103 IEEE80211_RADIOTAP_F_SHORTPRE = 0x02,
104 IEEE80211_RADIOTAP_F_WEP = 0x04,
105 IEEE80211_RADIOTAP_F_FRAG = 0x08,
106 IEEE80211_RADIOTAP_F_FCS = 0x10,
107 IEEE80211_RADIOTAP_F_DATAPAD = 0x20,
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dgk110.c38 { 0x40415c, 1, 0x04, 0x00000000 },
39 { 0x404170, 1, 0x04, 0x00000000 },
40 { 0x4041b4, 1, 0x04, 0x00000000 },
46 { 0x405844, 1, 0x04, 0x00ffffff },
47 { 0x405850, 1, 0x04, 0x00000000 },
48 { 0x405900, 1, 0x04, 0x0000ff00 },
49 { 0x405908, 1, 0x04, 0x00000000 },
50 { 0x405928, 2, 0x04, 0x00000000 },
56 { 0x407010, 1, 0x04, 0x00000000 },
57 { 0x407040, 1, 0x04, 0x80440424 },
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_11_0_0_default.h28 #define regSDMA0_DEC_START_DEFAULT 0x00000000
29 #define regSDMA0_F32_MISC_CNTL_DEFAULT 0x00000000
30 #define regSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
31 #define regSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
32 #define regSDMA0_POWER_CNTL_DEFAULT 0x00000000
33 #define regSDMA0_CNTL_DEFAULT 0x00002440
34 #define regSDMA0_CHICKEN_BITS_DEFAULT 0x0107d186
35 #define regSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000545
36 #define regSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00000545
37 #define regSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000
[all …]
/linux-6.12.1/sound/drivers/vx/
Dvx_uer.c27 rmh.Cmd[0] |= CMD_MODIFY_CLOCK_S_BIT; in vx_modify_board_clock()
39 rmh.Cmd[0] |= 1 << 0; /* reference: AUDIO 0 */ in vx_modify_board_inputs()
46 * returns 0 or 1.
56 val = (vx_inb(chip, RUER) >> 7) & 0x01; in vx_read_one_cbit()
60 val = (vx_inl(chip, RUER) >> 7) & 0x01; in vx_read_one_cbit()
69 * @val: bit value, 0 or 1
73 val = !!val; /* 0 or 1 */ in vx_write_one_cbit()
76 vx_outb(chip, CSUER, 0); /* write */ in vx_write_one_cbit()
79 vx_outl(chip, CSUER, 0); /* write */ in vx_write_one_cbit()
89 * returns the frequency of UER, or 0 if not sync,
[all …]
Dvx_cmd.h86 #define CODE_OP_PIPE_TIME 0x004e0000
87 #define CODE_OP_START_STREAM 0x00800000
88 #define CODE_OP_PAUSE_STREAM 0x00810000
89 #define CODE_OP_OUT_STREAM_LEVEL 0x00820000
90 #define CODE_OP_UPDATE_R_BUFFERS 0x00840000
91 #define CODE_OP_OUT_STREAM1_LEVEL_CURVE 0x00850000
92 #define CODE_OP_OUT_STREAM2_LEVEL_CURVE 0x00930000
93 #define CODE_OP_OUT_STREAM_FORMAT 0x00860000
94 #define CODE_OP_STREAM_TIME 0x008f0000
95 #define CODE_OP_OUT_STREAM_EXTRAPARAMETER 0x00910000
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/watchdog/
Dsnps,dw-wdt.yaml70 default: [0x0001000 0x0002000 0x0004000 0x0008000
71 0x0010000 0x0020000 0x0040000 0x0080000
72 0x0100000 0x0200000 0x0400000 0x0800000
73 0x1000000 0x2000000 0x4000000 0x8000000]
88 reg = <0xffd02000 0x1000>;
89 interrupts = <0 171 4>;
97 reg = <0xffd02000 0x1000>;
98 interrupts = <0 171 4>;
101 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
102 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/linux-6.12.1/arch/arm/include/asm/
Dv7m.h5 #define V7M_SCS_ICTR IOMEM(0xe000e004)
6 #define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f
8 #define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
10 #define V7M_SCB_CPUID 0x00
12 #define V7M_SCB_ICSR 0x04
16 #define V7M_SCB_ICSR_VECTACTIVE 0x000001ff
18 #define V7M_SCB_VTOR 0x08
20 #define V7M_SCB_AIRCR 0x0c
21 #define V7M_SCB_AIRCR_VECTKEY (0x05fa << 16)
24 #define V7M_SCB_SCR 0x10
[all …]
/linux-6.12.1/include/linux/mfd/
Dcs42l43-regs.h13 #define CS42L43_GEN_INT_STAT_1 0x000000C0
14 #define CS42L43_GEN_INT_MASK_1 0x000000C1
15 #define CS42L43_DEVID 0x00003000
16 #define CS42L43_REVID 0x00003004
17 #define CS42L43_RELID 0x0000300C
18 #define CS42L43_SFT_RESET 0x00003020
19 #define CS42L43_DRV_CTRL1 0x00006004
20 #define CS42L43_DRV_CTRL3 0x0000600C
21 #define CS42L43_DRV_CTRL4 0x00006010
22 #define CS42L43_DRV_CTRL_5 0x00006014
[all …]
/linux-6.12.1/drivers/net/wireless/mediatek/mt76/mt76x2/
Dinit.c86 (FIELD_PREP(MT_PROT_CFG_RATE, 0x3) | \ in mt76_write_mac_initvals()
88 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
92 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
94 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
98 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
101 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17)) in mt76_write_mac_initvals()
104 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2084) | \ in mt76_write_mac_initvals()
107 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f)) in mt76_write_mac_initvals()
111 { MT_PBF_SYS_CTRL, 0x00080c00 }, in mt76_write_mac_initvals()
112 { MT_PBF_CFG, 0x1efebcff }, in mt76_write_mac_initvals()
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/include/nvhw/class/
Dcl907d.h27 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004
28 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0
29 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000
30 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001
31 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014
32 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0
33 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000
34 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001
36 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000
37 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001
[all …]
/linux-6.12.1/arch/mips/include/asm/mach-au1x00/
Dau1100_mmc.h52 #define SD0_BASE 0xB0600000
53 #define SD1_BASE 0xB0680000
59 #define SD_TXPORT (0x0000)
60 #define SD_RXPORT (0x0004)
61 #define SD_CONFIG (0x0008)
62 #define SD_ENABLE (0x000C)
63 #define SD_CONFIG2 (0x0010)
64 #define SD_BLKSIZE (0x0014)
65 #define SD_STATUS (0x0018)
66 #define SD_DEBUG (0x001C)
[all …]
/linux-6.12.1/sound/pci/pcxhr/
Dpcxhr_core.h26 #define PCXHR_DSP_TIME_MASK 0x00ffffff
27 #define PCXHR_DSP_TIME_INVALID 0x10000000
47 CMD_SEND_IRQA, /* cmd_len = 1 stat_len = 0 */
51 CMD_MODIFY_CLOCK, /* cmd_len = 3 stat_len = 0 */
52 CMD_RESYNC_AUDIO_INPUTS, /* cmd_len = 1 stat_len = 0 */
54 CMD_SET_TIMER_INTERRUPT, /* cmd_len = 1 stat_len = 0 */
55 CMD_RES_PIPE, /* cmd_len >=2 stat_len = 0 */
56 CMD_FREE_PIPE, /* cmd_len = 1 stat_len = 0 */
57 CMD_CONF_PIPE, /* cmd_len = 2 stat_len = 0 */
58 CMD_STOP_PIPE, /* cmd_len = 1 stat_len = 0 */
[all …]
/linux-6.12.1/drivers/net/wireless/mediatek/mt76/mt76x0/
Dinitvals_init.h15 { MT_BCN_OFFSET(0), 0xf8f0e8e0 },
16 { MT_BCN_OFFSET(1), 0x6f77d0c8 },
17 { MT_LEGACY_BASIC_RATE, 0x0000013f },
18 { MT_HT_BASIC_RATE, 0x00008003 },
19 { MT_MAC_SYS_CTRL, 0x00000000 },
20 { MT_RX_FILTR_CFG, 0x00017f97 },
21 { MT_BKOFF_SLOT_CFG, 0x00000209 },
22 { MT_TX_SW_CFG0, 0x00000000 },
23 { MT_TX_SW_CFG1, 0x00080606 },
24 { MT_TX_LINK_CFG, 0x00001020 },
[all …]
/linux-6.12.1/arch/sh/boards/mach-migor/
Dlcd_qvga.c27 * Index 0: "Device Code Read" returns 0x1505.
32 gpio_set_value(GPIO_PTH2, 0); in reset_lcd_module()
44 tmp1 = (data<<1 | 0x00000001) & 0x000001FF; in adjust_reg18()
45 tmp2 = (data<<2 | 0x00000200) & 0x0003FE00; in adjust_reg18()
72 return ((data >> 1) & 0xff) | ((data >> 2) & 0xff00); in read_reg16()
81 for (i = 0; i < no_data; i += 2) in migor_lcd_qvga_seq()
86 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
90 0x0060, 0x2700, 0x0008, 0x0808, 0x0090, 0x001A, 0x0007, 0x0001,
91 0x0017, 0x0001, 0x0019, 0x0000, 0x0010, 0x17B0, 0x0011, 0x0116,
92 0x0012, 0x0198, 0x0013, 0x1400, 0x0029, 0x000C, 0x0012, 0x01B8,
[all …]
/linux-6.12.1/include/video/
Dtgafb.h20 #define TGA_TYPE_8PLANE 0
28 #define TGA_ROM_OFFSET 0x0000000
29 #define TGA_REGS_OFFSET 0x0100000
30 #define TGA_8PLANE_FB_OFFSET 0x0200000
31 #define TGA_24PLANE_FB_OFFSET 0x0804000
32 #define TGA_24PLUSZ_FB_OFFSET 0x1004000
34 #define TGA_FOREGROUND_REG 0x0020
35 #define TGA_BACKGROUND_REG 0x0024
36 #define TGA_PLANEMASK_REG 0x0028
37 #define TGA_PIXELMASK_ONESHOT_REG 0x002c
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/athub/
Dathub_2_0_0_default.h26 #define mmATC_ATS_CNTL_DEFAULT 0x009a0c00
27 #define mmATC_ATS_STATUS_DEFAULT 0x00000000
28 #define mmATC_ATS_FAULT_CNTL_DEFAULT 0x000001ff
29 #define mmATC_ATS_FAULT_STATUS_INFO_DEFAULT 0x00000000
30 #define mmATC_ATS_FAULT_STATUS_ADDR_DEFAULT 0x00000000
31 #define mmATC_ATS_DEFAULT_PAGE_LOW_DEFAULT 0x00000000
32 #define mmATC_TRANS_FAULT_RSPCNTRL_DEFAULT 0xffffffff
33 #define mmATC_ATS_FAULT_STATUS_INFO2_DEFAULT 0x00000000
34 #define mmATHUB_MISC_CNTL_DEFAULT 0x001c0200
35 #define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_DEFAULT 0x00000000
[all …]
/linux-6.12.1/drivers/infiniband/hw/irdma/
Dcm.h17 #define IETF_MPA_V2_FLAG 0x10
18 #define SNDMARKER_SEQNMASK 0x000001ff
22 #define IETF_PEER_TO_PEER 0x8000
23 #define IETF_FLPDU_ZERO_LEN 0x4000
24 #define IETF_RDMA0_WRITE 0x8000
25 #define IETF_RDMA0_READ 0x4000
26 #define IETF_NO_IRD_ORD 0x3fff
30 #define IRDMA_PASSIVE_STATE_INDICATED 0
45 #define IRDMA_DEFAULT_TTL 0x40
47 #define IRDMA_DEFAULT_SS_THRESH 0x3fffffff
[all …]
/linux-6.12.1/drivers/clk/
Dclk-xgene.c17 #define N_DIV_RD(src) ((src) & 0x000001ff)
18 #define SC_N_DIV_RD(src) ((src) & 0x0000007f)
19 #define SC_OUTDIV2(src) (((src) & 0x00000100) >> 8)
22 #define CLKR_RD(src) (((src) & 0x07000000)>>24)
23 #define CLKOD_RD(src) (((src) & 0x00300000)>>20)
24 #define REGSPEC_RESET_F1_MASK 0x00010000
25 #define CLKF_RD(src) (((src) & 0x000001ff))
43 PLL_TYPE_PCP = 0,
67 return data & REGSPEC_RESET_F1_MASK ? 0 : 1; in xgene_clk_pll_is_enabled()
141 init.num_parents = parent_name ? 1 : 0; in xgene_register_clk_pll()
[all …]
/linux-6.12.1/arch/mips/include/asm/sn/
Dioc3.h30 u8 iu_ier; /* DLAB == 0 */
34 u8 iu_rbr; /* read only, DLAB == 0 */
35 u8 iu_thr; /* write only, DLAB == 0 */
45 u8 fill[0x141]; /* starts at 0x141 */
50 u8 fill0[0x151 - 0x142 - 1];
56 u8 fill1[0x159 - 0x153 - 1];
62 u8 fill2[0x16a - 0x15b - 1];
67 u8 fill3[0x170 - 0x16b - 1];
69 struct ioc3_uartregs uartb; /* 0x20170 */
70 struct ioc3_uartregs uarta; /* 0x20178 */
[all …]
/linux-6.12.1/drivers/atm/
Dnicstar.h40 #define NS_VPIBITS 2 /* 0, 1, 2, or 8 */
90 #define NICSTAR_EPROM_MAC_ADDR_OFFSET 0x6C
91 #define NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT 0xF6
102 #define BUF_SM 0x00000000 /* These two are used for push_rxbufs() */
103 #define BUF_LG 0x00000001 /* CMD, Write_FreeBufQ, LBUF bit */
104 #define BUF_NONE 0xffffffff /* Software only: */
135 ((le32_to_cpu((ns_rsqep)->word_1) & 0x00FF0000) >> 16)
137 (le32_to_cpu((ns_rsqep)->word_1) & 0x0000FFFF)
139 #define NS_RSQE_VALID 0x80000000
140 #define NS_RSQE_NZGFC 0x00004000
[all …]

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