Lines Matching +full:0 +full:x000001ff
40 #define NS_VPIBITS 2 /* 0, 1, 2, or 8 */
90 #define NICSTAR_EPROM_MAC_ADDR_OFFSET 0x6C
91 #define NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT 0xF6
102 #define BUF_SM 0x00000000 /* These two are used for push_rxbufs() */
103 #define BUF_LG 0x00000001 /* CMD, Write_FreeBufQ, LBUF bit */
104 #define BUF_NONE 0xffffffff /* Software only: */
135 ((le32_to_cpu((ns_rsqep)->word_1) & 0x00FF0000) >> 16)
137 (le32_to_cpu((ns_rsqep)->word_1) & 0x0000FFFF)
139 #define NS_RSQE_VALID 0x80000000
140 #define NS_RSQE_NZGFC 0x00004000
141 #define NS_RSQE_EOPDU 0x00002000
142 #define NS_RSQE_BUFSIZE 0x00001000
143 #define NS_RSQE_CONGESTION 0x00000800
144 #define NS_RSQE_CLP 0x00000400
145 #define NS_RSQE_CRCERR 0x00000200
147 #define NS_RSQE_BUFSIZE_SM 0x00000000
148 #define NS_RSQE_BUFSIZE_LG 0x00001000
166 (le32_to_cpu((ns_rsqep)->word_4) & 0x000001FF)
168 ((ns_rsqep)->word_4 = cpu_to_le32(0x00000000))
194 (le32_to_cpu((ns_rcqep)->word_2) != 0x00000000)
216 #define NS_SCQE_TYPE_TBD 0x00000000
217 #define NS_SCQE_TYPE_TSR 0x80000000
219 #define NS_TBD_EOPDU 0x40000000
220 #define NS_TBD_AAL0 0x00000000
221 #define NS_TBD_AAL34 0x04000000
222 #define NS_TBD_AAL5 0x08000000
224 #define NS_TBD_VPI_MASK 0x0FF00000
225 #define NS_TBD_VCI_MASK 0x000FFFF0
234 (cpu_to_le32((flags) | (buflen) | 0x00810000))
240 #define NS_TSR_INTENABLE 0x20000000
242 #define NS_TSR_SCDISVBR 0xFFFF /* Use as scdi for VBR SCD */
247 (cpu_to_le32((scdi) << 16 | 0x00008000 | (scqi)))
274 #define NS_TSI_EMPTY 0x80000000
275 #define NS_TSI_TIMESTAMP_MASK 0x00FFFFFF
292 (le32_to_cpu((ns_tsip)->word_1) == 0x00000000)
294 ((le32_to_cpu((ns_tsip)->word_1) & 0xFFFF0000) >> 16)
296 (le32_to_cpu((ns_tsip)->word_1) & 0x00007FFF)
313 #define NS_RCTE_BSFB 0x00200000 /* Rev. D only */
314 #define NS_RCTE_NZGFC 0x00100000
315 #define NS_RCTE_CONNECTOPEN 0x00080000
316 #define NS_RCTE_AALMASK 0x00070000
317 #define NS_RCTE_AAL0 0x00000000
318 #define NS_RCTE_AAL34 0x00010000
319 #define NS_RCTE_AAL5 0x00020000
320 #define NS_RCTE_RCQ 0x00030000
321 #define NS_RCTE_RAWCELLINTEN 0x00008000
322 #define NS_RCTE_RXCONSTCELLADDR 0x00004000
323 #define NS_RCTE_BUFFVALID 0x00002000
324 #define NS_RCTE_FBDSIZE 0x00001000
325 #define NS_RCTE_EFCI 0x00000800
326 #define NS_RCTE_CLP 0x00000400
327 #define NS_RCTE_CRCERROR 0x00000200
328 #define NS_RCTE_CELLCOUNT_MASK 0x000001FF
330 #define NS_RCTE_FBDSIZE_SM 0x00000000
331 #define NS_RCTE_FBDSIZE_LG 0x00001000
357 #define NS_TST_OPCODE_MASK 0x60000000
359 #define NS_TST_OPCODE_NULL 0x00000000 /* Insert null cell */
360 #define NS_TST_OPCODE_FIXED 0x20000000 /* Cell from a fixed rate channel */
361 #define NS_TST_OPCODE_VARIABLE 0x40000000
362 #define NS_TST_OPCODE_END 0x60000000 /* Jump */
389 #define NS_SCD_BASE_MASK_VAR 0xFFFFE000 /* Variable rate */
390 #define NS_SCD_BASE_MASK_FIX 0xFFFFFC00 /* Fixed rate */
391 #define NS_SCD_TAIL_MASK_VAR 0x00001FF0
392 #define NS_SCD_TAIL_MASK_FIX 0x000003F0
393 #define NS_SCD_HEAD_MASK_VAR 0x00001FF0
394 #define NS_SCD_HEAD_MASK_FIX 0x000003F0
395 #define NS_SCD_XMITFOREVER 0x02000000
402 #define NS_RCT 0x00000
403 #define NS_RCT_32_END 0x03FFF
404 #define NS_RCT_128_END 0x0FFFF
405 #define NS_UNUSED_32 0x04000
406 #define NS_UNUSED_128 0x10000
407 #define NS_UNUSED_END 0x1BFFF
408 #define NS_TST_FRSCD 0x1C000
409 #define NS_TST_FRSCD_END 0x1E7DB
410 #define NS_VRSCD2 0x1E7DC
411 #define NS_VRSCD2_END 0x1E7E7
412 #define NS_VRSCD1 0x1E7E8
413 #define NS_VRSCD1_END 0x1E7F3
414 #define NS_VRSCD0 0x1E7F4
415 #define NS_VRSCD0_END 0x1E7FF
416 #define NS_RXFIFO 0x1E800
417 #define NS_RXFIFO_END 0x1F7FF
418 #define NS_SMFBQ 0x1F800
419 #define NS_SMFBQ_END 0x1FBFF
420 #define NS_LGFBQ 0x1FC00
421 #define NS_LGFBQ_END 0x1FFFF
428 DR0 = 0x00, /* Data Register 0 R/W */
429 DR1 = 0x04, /* Data Register 1 W */
430 DR2 = 0x08, /* Data Register 2 W */
431 DR3 = 0x0C, /* Data Register 3 W */
432 CMD = 0x10, /* Command W */
433 CFG = 0x14, /* Configuration R/W */
434 STAT = 0x18, /* Status R/W */
435 RSQB = 0x1C, /* Receive Status Queue Base W */
436 RSQT = 0x20, /* Receive Status Queue Tail R */
437 RSQH = 0x24, /* Receive Status Queue Head W */
438 CDC = 0x28, /* Cell Drop Counter R/clear */
439 VPEC = 0x2C, /* VPI/VCI Lookup Error Count R/clear */
440 ICC = 0x30, /* Invalid Cell Count R/clear */
441 RAWCT = 0x34, /* Raw Cell Tail R */
442 TMR = 0x38, /* Timer R */
443 TSTB = 0x3C, /* Transmit Schedule Table Base R/W */
444 TSQB = 0x40, /* Transmit Status Queue Base W */
445 TSQT = 0x44, /* Transmit Status Queue Tail R */
446 TSQH = 0x48, /* Transmit Status Queue Head W */
447 GP = 0x4C, /* General Purpose R/W */
448 VPM = 0x50 /* VPI/VCI Mask W */
455 #define NS_CMD_NO_OPERATION 0x00000000
456 /* params always 0 */
458 #define NS_CMD_OPENCLOSE_CONNECTION 0x20000000
459 /* b19{1=open,0=close} b18-2{SRAM addr} */
461 #define NS_CMD_WRITE_SRAM 0x40000000
462 /* b18-2{SRAM addr} b1-0{burst size} */
464 #define NS_CMD_READ_SRAM 0x50000000
467 #define NS_CMD_WRITE_FREEBUFQ 0x60000000
470 #define NS_CMD_READ_UTILITY 0x80000000
471 /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
473 #define NS_CMD_WRITE_UTILITY 0x90000000
474 /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
476 #define NS_CMD_OPEN_CONNECTION (NS_CMD_OPENCLOSE_CONNECTION | 0x00080000)
481 #define NS_CFG_SWRST 0x80000000 /* Software Reset */
482 #define NS_CFG_RXPATH 0x20000000 /* Receive Path Enable */
483 #define NS_CFG_SMBUFSIZE_MASK 0x18000000 /* Small Receive Buffer Size */
484 #define NS_CFG_LGBUFSIZE_MASK 0x06000000 /* Large Receive Buffer Size */
485 #define NS_CFG_EFBIE 0x01000000 /* Empty Free Buffer Queue
487 #define NS_CFG_RSQSIZE_MASK 0x00C00000 /* Receive Status Queue Size */
488 #define NS_CFG_ICACCEPT 0x00200000 /* Invalid Cell Accept */
489 #define NS_CFG_IGNOREGFC 0x00100000 /* Ignore General Flow Control */
490 #define NS_CFG_VPIBITS_MASK 0x000C0000 /* VPI/VCI Bits Size Select */
491 #define NS_CFG_RCTSIZE_MASK 0x00030000 /* Receive Connection Table Size */
492 #define NS_CFG_VCERRACCEPT 0x00008000 /* VPI/VCI Error Cell Accept */
493 #define NS_CFG_RXINT_MASK 0x00007000 /* End of Receive PDU Interrupt
495 #define NS_CFG_RAWIE 0x00000800 /* Raw Cell Qu' Interrupt Enable */
496 #define NS_CFG_RSQAFIE 0x00000400 /* Receive Queue Almost Full
498 #define NS_CFG_RXRM 0x00000200 /* Receive RM Cells */
499 #define NS_CFG_TMRROIE 0x00000080 /* Timer Roll Over Interrupt
501 #define NS_CFG_TXEN 0x00000020 /* Transmit Operation Enable */
502 #define NS_CFG_TXIE 0x00000010 /* Transmit Status Interrupt
504 #define NS_CFG_TXURIE 0x00000008 /* Transmit Under-run Interrupt
506 #define NS_CFG_UMODE 0x00000004 /* Utopia Mode (cell/byte) Select */
507 #define NS_CFG_TSQFIE 0x00000002 /* Transmit Status Queue Full
509 #define NS_CFG_PHYIE 0x00000001 /* PHY Interrupt Enable */
511 #define NS_CFG_SMBUFSIZE_48 0x00000000
512 #define NS_CFG_SMBUFSIZE_96 0x08000000
513 #define NS_CFG_SMBUFSIZE_240 0x10000000
514 #define NS_CFG_SMBUFSIZE_2048 0x18000000
516 #define NS_CFG_LGBUFSIZE_2048 0x00000000
517 #define NS_CFG_LGBUFSIZE_4096 0x02000000
518 #define NS_CFG_LGBUFSIZE_8192 0x04000000
519 #define NS_CFG_LGBUFSIZE_16384 0x06000000
521 #define NS_CFG_RSQSIZE_2048 0x00000000
522 #define NS_CFG_RSQSIZE_4096 0x00400000
523 #define NS_CFG_RSQSIZE_8192 0x00800000
525 #define NS_CFG_VPIBITS_0 0x00000000
526 #define NS_CFG_VPIBITS_1 0x00040000
527 #define NS_CFG_VPIBITS_2 0x00080000
528 #define NS_CFG_VPIBITS_8 0x000C0000
530 #define NS_CFG_RCTSIZE_4096_ENTRIES 0x00000000
531 #define NS_CFG_RCTSIZE_8192_ENTRIES 0x00010000
532 #define NS_CFG_RCTSIZE_16384_ENTRIES 0x00020000
534 #define NS_CFG_RXINT_NOINT 0x00000000
535 #define NS_CFG_RXINT_NODELAY 0x00001000
536 #define NS_CFG_RXINT_314US 0x00002000
537 #define NS_CFG_RXINT_624US 0x00003000
538 #define NS_CFG_RXINT_899US 0x00004000
542 #define NS_STAT_SFBQC_MASK 0xFF000000 /* hi 8 bits Small Buffer Queue Count */
543 #define NS_STAT_LFBQC_MASK 0x00FF0000 /* hi 8 bits Large Buffer Queue Count */
544 #define NS_STAT_TSIF 0x00008000 /* Transmit Status Queue Indicator */
545 #define NS_STAT_TXICP 0x00004000 /* Transmit Incomplete PDU */
546 #define NS_STAT_TSQF 0x00001000 /* Transmit Status Queue Full */
547 #define NS_STAT_TMROF 0x00000800 /* Timer Overflow */
548 #define NS_STAT_PHYI 0x00000400 /* PHY Device Interrupt */
549 #define NS_STAT_CMDBZ 0x00000200 /* Command Busy */
550 #define NS_STAT_SFBQF 0x00000100 /* Small Buffer Queue Full */
551 #define NS_STAT_LFBQF 0x00000080 /* Large Buffer Queue Full */
552 #define NS_STAT_RSQF 0x00000040 /* Receive Status Queue Full */
553 #define NS_STAT_EOPDU 0x00000020 /* End of PDU */
554 #define NS_STAT_RAWCF 0x00000010 /* Raw Cell Flag */
555 #define NS_STAT_SFBQE 0x00000008 /* Small Buffer Queue Empty */
556 #define NS_STAT_LFBQE 0x00000004 /* Large Buffer Queue Empty */
557 #define NS_STAT_RSQAF 0x00000002 /* Receive Status Queue Almost Full */
605 #if (NS_VPIBITS == 0)
620 #define NS_CFG_RAWIE_OPT 0x00000000
626 #define NS_CFG_TSQFIE_OPT 0x00000000
632 #define PCI_VENDOR_ID_IDT 0x111D
636 #define PCI_DEVICE_ID_IDT_IDT77201 0x0001
704 SCD. 0x00000000 for UBR/VBR/ABR */