86 	(FIELD_PREP(MT_PROT_CFG_RATE, 0x3) |		\  in mt76_write_mac_initvals()
88 	 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) |	\  in mt76_write_mac_initvals()
92 	(FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) |		\  in mt76_write_mac_initvals()
94 	 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) |	\  in mt76_write_mac_initvals()
98 	(FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) |		\  in mt76_write_mac_initvals()
101 	 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17))  in mt76_write_mac_initvals()
104 	(FIELD_PREP(MT_PROT_CFG_RATE, 0x2084) |		\  in mt76_write_mac_initvals()
107 	 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f))  in mt76_write_mac_initvals()
111 		{ MT_PBF_SYS_CTRL,		0x00080c00 },  in mt76_write_mac_initvals()
112 		{ MT_PBF_CFG,			0x1efebcff },  in mt76_write_mac_initvals()
113 		{ MT_FCE_PSE_CTRL,		0x00000001 },  in mt76_write_mac_initvals()
114 		{ MT_MAC_SYS_CTRL,		0x00000000 },  in mt76_write_mac_initvals()
115 		{ MT_MAX_LEN_CFG,		0x003e3f00 },  in mt76_write_mac_initvals()
116 		{ MT_AMPDU_MAX_LEN_20M1S,	0xaaa99887 },  in mt76_write_mac_initvals()
117 		{ MT_AMPDU_MAX_LEN_20M2S,	0x000000aa },  in mt76_write_mac_initvals()
118 		{ MT_XIFS_TIME_CFG,		0x33a40d0a },  in mt76_write_mac_initvals()
119 		{ MT_BKOFF_SLOT_CFG,		0x00000209 },  in mt76_write_mac_initvals()
120 		{ MT_TBTT_SYNC_CFG,		0x00422010 },  in mt76_write_mac_initvals()
121 		{ MT_PWR_PIN_CFG,		0x00000000 },  in mt76_write_mac_initvals()
122 		{ 0x1238,			0x001700c8 },  in mt76_write_mac_initvals()
123 		{ MT_TX_SW_CFG0,		0x00101001 },  in mt76_write_mac_initvals()
124 		{ MT_TX_SW_CFG1,		0x00010000 },  in mt76_write_mac_initvals()
125 		{ MT_TX_SW_CFG2,		0x00000000 },  in mt76_write_mac_initvals()
126 		{ MT_TXOP_CTRL_CFG,		0x0400583f },  in mt76_write_mac_initvals()
127 		{ MT_TX_RTS_CFG,		0x00ffff20 },  in mt76_write_mac_initvals()
128 		{ MT_TX_TIMEOUT_CFG,		0x000a2290 },  in mt76_write_mac_initvals()
129 		{ MT_TX_RETRY_CFG,		0x47f01f0f },  in mt76_write_mac_initvals()
130 		{ MT_EXP_ACK_TIME,		0x002c00dc },  in mt76_write_mac_initvals()
131 		{ MT_TX_PROT_CFG6,		0xe3f42004 },  in mt76_write_mac_initvals()
132 		{ MT_TX_PROT_CFG7,		0xe3f42084 },  in mt76_write_mac_initvals()
133 		{ MT_TX_PROT_CFG8,		0xe3f42104 },  in mt76_write_mac_initvals()
134 		{ MT_PIFS_TX_CFG,		0x00060fff },  in mt76_write_mac_initvals()
135 		{ MT_RX_FILTR_CFG,		0x00015f97 },  in mt76_write_mac_initvals()
136 		{ MT_LEGACY_BASIC_RATE,		0x0000017f },  in mt76_write_mac_initvals()
137 		{ MT_HT_BASIC_RATE,		0x00004003 },  in mt76_write_mac_initvals()
138 		{ MT_PN_PAD_MODE,		0x00000003 },  in mt76_write_mac_initvals()
139 		{ MT_TXOP_HLDR_ET,		0x00000002 },  in mt76_write_mac_initvals()
140 		{ 0xa44,			0x00000000 },  in mt76_write_mac_initvals()
141 		{ MT_HEADER_TRANS_CTRL_REG,	0x00000000 },  in mt76_write_mac_initvals()
142 		{ MT_TSO_CTRL,			0x00000000 },  in mt76_write_mac_initvals()
143 		{ MT_AUX_CLK_CFG,		0x00000000 },  in mt76_write_mac_initvals()
144 		{ MT_DACCLK_EN_DLY_CFG,		0x00000000 },  in mt76_write_mac_initvals()
145 		{ MT_TX_ALC_CFG_4,		0x00000000 },  in mt76_write_mac_initvals()
146 		{ MT_TX_ALC_VGA3,		0x00000000 },  in mt76_write_mac_initvals()
147 		{ MT_TX_PWR_CFG_0,		0x3a3a3a3a },  in mt76_write_mac_initvals()
148 		{ MT_TX_PWR_CFG_1,		0x3a3a3a3a },  in mt76_write_mac_initvals()
149 		{ MT_TX_PWR_CFG_2,		0x3a3a3a3a },  in mt76_write_mac_initvals()
150 		{ MT_TX_PWR_CFG_3,		0x3a3a3a3a },  in mt76_write_mac_initvals()
151 		{ MT_TX_PWR_CFG_4,		0x3a3a3a3a },  in mt76_write_mac_initvals()
152 		{ MT_TX_PWR_CFG_7,		0x3a3a3a3a },  in mt76_write_mac_initvals()
153 		{ MT_TX_PWR_CFG_8,		0x0000003a },  in mt76_write_mac_initvals()
154 		{ MT_TX_PWR_CFG_9,		0x0000003a },  in mt76_write_mac_initvals()
155 		{ MT_EFUSE_CTRL,		0x0000d000 },  in mt76_write_mac_initvals()
156 		{ MT_PAUSE_ENABLE_CONTROL1,	0x0000000a },  in mt76_write_mac_initvals()
157 		{ MT_FCE_WLAN_FLOW_CONTROL1,	0x60401c18 },  in mt76_write_mac_initvals()
158 		{ MT_WPDMA_DELAY_INT_CFG,	0x94ff0000 },  in mt76_write_mac_initvals()
159 		{ MT_TX_SW_CFG3,		0x00000004 },  in mt76_write_mac_initvals()
160 		{ MT_HT_FBK_TO_LEGACY,		0x00001818 },  in mt76_write_mac_initvals()
161 		{ MT_VHT_HT_FBK_CFG1,		0xedcba980 },  in mt76_write_mac_initvals()
162 		{ MT_PROT_AUTO_TX_CFG,		0x00830083 },  in mt76_write_mac_initvals()
163 		{ MT_HT_CTRL_CFG,		0x000001ff },  in mt76_write_mac_initvals()
164 		{ MT_TX_LINK_CFG,		0x00001020 },  in mt76_write_mac_initvals()
175 	mt76_wr_rp(dev, 0, vals, ARRAY_SIZE(vals));  in mt76_write_mac_initvals()
176 	mt76_wr_rp(dev, 0, prot_vals, ARRAY_SIZE(prot_vals));  in mt76_write_mac_initvals()
188 	for (i = 0; i < sband->n_channels; i++) {  in mt76x2_init_txpower()