17 #define N_DIV_RD(src)			((src) & 0x000001ff)
18 #define SC_N_DIV_RD(src)		((src) & 0x0000007f)
19 #define SC_OUTDIV2(src)			(((src) & 0x00000100) >> 8)
22 #define CLKR_RD(src)			(((src) & 0x07000000)>>24)
23 #define CLKOD_RD(src)			(((src) & 0x00300000)>>20)
24 #define REGSPEC_RESET_F1_MASK		0x00010000
25 #define CLKF_RD(src)			(((src) & 0x000001ff))
43 	PLL_TYPE_PCP = 0,
67 	return data & REGSPEC_RESET_F1_MASK ? 0 : 1;  in xgene_clk_pll_is_enabled()
141 	init.num_parents = parent_name ? 1 : 0;  in xgene_register_clk_pll()
176 	reg = of_iomap(np, 0);  in xgene_pllclk_init()
183 			clk_name, of_clk_get_parent_name(np, 0),  in xgene_pllclk_init()
184 			0, reg, 0, pll_type, &clk_lock,  in xgene_pllclk_init()
214  *		0 for (0 + 1) / denom,
217  *		0 for (denom - 0) / denom,
232 #define XGENE_CLK_PMD_SCALE_INVERTED	BIT(0)
240 	unsigned long flags = 0;  in xgene_clk_pmd_recalc_rate()
267 	if (ret == 0)  in xgene_clk_pmd_recalc_rate()
296 	unsigned long flags = 0;  in xgene_clk_pmd_set_rate()
330 	return 0;  in xgene_clk_pmd_set_rate()
357 	init.num_parents = parent_name ? 1 : 0;  in xgene_register_clk_pmd()
384 	u32 flags = 0;  in xgene_pmdclk_init()
392 	rc = of_address_to_resource(np, 0, &res);  in xgene_pmdclk_init()
393 	if (rc != 0) {  in xgene_pmdclk_init()
397 	csr_reg = of_iomap(np, 0);  in xgene_pmdclk_init()
408 				     of_clk_get_parent_name(np, 0), 0,  in xgene_pmdclk_init()
446 	unsigned long flags = 0;  in xgene_clk_enable()
460 		pr_debug("%s clk offset 0x%08X mask 0x%08X value 0x%08X\n",  in xgene_clk_enable()
471 		pr_debug("%s csr offset 0x%08X mask 0x%08X value 0x%08X\n",  in xgene_clk_enable()
480 	return 0;  in xgene_clk_enable()
486 	unsigned long flags = 0;  in xgene_clk_disable()
516 	u32 data = 0;  in xgene_clk_is_enabled()
529 	return data & pclk->param.reg_clk_mask ? 1 : 0;  in xgene_clk_is_enabled()
560 	unsigned long flags = 0;  in xgene_clk_set_rate()
640 	init.flags = 0;  in xgene_register_clk()
642 	init.num_parents = parent_name ? 1 : 0;  in xgene_register_clk()
658 	if (rc != 0) {  in xgene_register_clk()
681 	for (i = 0; i < 2; i++) {  in xgene_devclk_init()
684 		if (rc != 0) {  in xgene_devclk_init()
685 			if (i == 0) {  in xgene_devclk_init()
696 		if (strcmp(res.name, "div-reg") == 0)  in xgene_devclk_init()
698 		else /* if (strcmp(res->name, "csr-reg") == 0) */  in xgene_devclk_init()
702 		parameters.reg_csr_offset = 0;  in xgene_devclk_init()
704 		parameters.reg_csr_mask = 0xF;  in xgene_devclk_init()
707 		parameters.reg_clk_offset = 0x8;  in xgene_devclk_init()
709 		parameters.reg_clk_mask = 0xF;  in xgene_devclk_init()
712 		parameters.reg_divider_offset = 0;  in xgene_devclk_init()
715 		parameters.reg_divider_width = 0;  in xgene_devclk_init()
718 		parameters.reg_divider_shift = 0;  in xgene_devclk_init()
722 		of_clk_get_parent_name(np, 0), &parameters, &clk_lock);  in xgene_devclk_init()
727 	if (rc != 0)  in xgene_devclk_init()