qcacmn: Fix peer id mismatch on Tx completion

Peer id mismatch is observed when prefetch of HW
descriptor exceeds the last valid descriptor.
To fix this issue, add check to limit prefetch to
the las

qcacmn: Fix peer id mismatch on Tx completion

Peer id mismatch is observed when prefetch of HW
descriptor exceeds the last valid descriptor.
To fix this issue, add check to limit prefetch to
the last valid descriptor.

Change-Id: I01582892d55ed1f300d6806e1d8def46f747516b
CRs-Fixed: 3671814

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qcacmn: Add logic to stitch MPDU for LPC

Add logic to stitch MPDU from MSDU and
hold MPDU till PPDU_END tlv to update radiotap
header fields before submitting to stack for
local packet capture mode.

qcacmn: Add logic to stitch MPDU for LPC

Add logic to stitch MPDU from MSDU and
hold MPDU till PPDU_END tlv to update radiotap
header fields before submitting to stack for
local packet capture mode.

CRs-Fixed: 3821723
Change-Id: I7ac8127c1c0abfc747f37139c741dc69fb79a2a4

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qcacmn: Update first_msdu_payload once per status nbuf

first_msdu_payload is updated for every WIFIRX_HEADER_E
TLV received in the status nbuf and this could result
in incorrect offset into the nbuf

qcacmn: Update first_msdu_payload once per status nbuf

first_msdu_payload is updated for every WIFIRX_HEADER_E
TLV received in the status nbuf and this could result
in incorrect offset into the nbuf for the first MSDU
if the PPDU has multiple MPDUs. Also, the size variable
used is 8 bit for the calculation of offset into the nbuf
for the frame which could result in possible overflow.

Fix is to update first_msdu_payload only for the first
WIFIRX_HEADER_E TLV entry for a PPDU and increase the
width of size variable to avoid possible integer overflow.

Change-Id: Ic12cb11328fc1414bd7a68fa941fa0ef764c8b1f
CRs-Fixed: 3788496

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qcacmn: add MU Sniffer compatibility

add missing values for rx_status and rx_user_status
values are for both HE and EHT data as well as usig.

CRs-Fixed: 3734450
Change-Id: I1bfd1a3021e11c4b5f2c07f3

qcacmn: add MU Sniffer compatibility

add missing values for rx_status and rx_user_status
values are for both HE and EHT data as well as usig.

CRs-Fixed: 3734450
Change-Id: I1bfd1a3021e11c4b5f2c07f324273bb778bf5c0f

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qcacmn: Force update HP/TP upon delayed register writes

Currently if HP/TP register updates are delayed due to delayed reg
write work not getting scheduled, although driver has processed
the ring co

qcacmn: Force update HP/TP upon delayed register writes

Currently if HP/TP register updates are delayed due to delayed reg
write work not getting scheduled, although driver has processed
the ring completely, hardware would see HP/TP delta and fires an
interrupt based on interrupt threshold configuration until the
HP/TP updates reach the hardware.

When system is heavily stressed, this delay in HP/TP updates would
result in IRQ storm further stressing the system which is bad.
Force update HP/TP to the hardware under such scenarios to avoid
this problem.

Currently doing this just for CE DST SRNGs, this can be scaled to
other SRNGs on need.

Change-Id: I8a4938dbd4850d7ab6ae5183186237a5e37e1038
CRs-Fixed: 3749078

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qcacmn: Set eht flag when the frame is 11be

In monitor mode, set EHT flag for packets for
11be frames when reading status TLV.

Change-Id: I8792bf7737dcf3efe69125218d5170d69f761142
CRs-Fixed: 3724725

qcacmn: Fix delay req queue not update to date issue

Delay write of SRNG regs may happen on different CPUs.
Sometimes wmb may not sufficient to protect the update
in sequence.

So to fix update issu

qcacmn: Fix delay req queue not update to date issue

Delay write of SRNG regs may happen on different CPUs.
Sometimes wmb may not sufficient to protect the update
in sequence.

So to fix update issue sleep and retry before checking
again for update.

CRs-Fixed: 3717683
Change-Id: I6c7916f91ecefa8175d3e3d9108d018fc8a42cfc

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qcacmn: optimize code for register read/write

Optimize code for checking flag which indicates srngs initialization
during register read/write.

Change-Id: I6e3d2446b1df7214aaa90483046524c7cc01533f
C

qcacmn: optimize code for register read/write

Optimize code for checking flag which indicates srngs initialization
during register read/write.

Change-Id: I6e3d2446b1df7214aaa90483046524c7cc01533f
CRs-Fixed: 3670754

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qcacmn: Add HAL API support to get l3 type from pkt tlvs

Add HAL API support to get l3 type from pkt tlvs for
WCN6450 target.

Change-Id: I50ab1baed5fbf1b81151f13481dfbeca38d9f992
CRs-Fixed: 3659241

qcacmn: Ring IPA TX doorbell with HW HP value

Ring IPA TX doorbell with HW HP value to avoid out-of-sync
scenarios between WLAN and IPA after IPA pipes are disabled
and then re-enabled.

CRs-Fixed:

qcacmn: Ring IPA TX doorbell with HW HP value

Ring IPA TX doorbell with HW HP value to avoid out-of-sync
scenarios between WLAN and IPA after IPA pipes are disabled
and then re-enabled.

CRs-Fixed: 3479426
Change-Id: Ia88c0228759e241722fe31fd1a252e70484684e9

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qcacmn: Add support for disabling MSI for direct link CEs

After direct link WFDS QMI server is down, host driver
unmaps the IPCC MSI address. There is a possibility
where FW can still enqueue entrie

qcacmn: Add support for disabling MSI for direct link CEs

After direct link WFDS QMI server is down, host driver
unmaps the IPCC MSI address. There is a possibility
where FW can still enqueue entries to direct link CE
resulting in a SMMU fault when CE HW raises interrupt
after copy operation.

Fix is to add support for disabling MSI for direct link
CEs and disable MSI prior to MSI address unmap.

CRs-Fixed: 3657150
Change-Id: I38ce3bcc143743884d5c464eae74c390bf32eab6

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qcacmn: fix out of bounds by dereference

change uint32 dereference to uint16 for the last bytes from mac address.

Change-Id: If9d5fb8f302b59fbfd091978f31e64737edc43a3
CRs-Fixed: 3657606

qcacmn: Add hal api to get L3 type from packet tlvs

Add hal api to get L3 type from packet tlvs for
QCA6750 based targets.

Change-Id: I00be71c4366e0ee6f5cbb5d14a55fa0600f3bb7a
CRs-Fixed: 3656683

qcacmn: Mark wow wakeup indication in the packet buffer

Mark the packet buffer to indicate that it was the
packet which woke-up the system from suspend state.

Change-Id: Id4235461f90feef945f518e5ac

qcacmn: Mark wow wakeup indication in the packet buffer

Mark the packet buffer to indicate that it was the
packet which woke-up the system from suspend state.

Change-Id: Id4235461f90feef945f518e5ac01c28f35883285
CRs-Fixed: 3654812

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qcacmn: Introduce monitor 2.0 packet processing flag

QCA_MONITOR_2_0_PKT_SUPPORT is introduced for packet
processing code.

Change-Id: Ib4de57e3e74ca9161d0cb7e3507f9c28d06b8654
CRs-Fixed: 3647037

qcacmn: Avoid memzero operation in monitor interrupt handling

Avoid ppdu info structure memzero operation while handling
monitor interrupts. ppdu info structure can be memzeroed
from workqueue conte

qcacmn: Avoid memzero operation in monitor interrupt handling

Avoid ppdu info structure memzero operation while handling
monitor interrupts. ppdu info structure can be memzeroed
from workqueue context

Change-Id: If2436f7448780926f685ed6a00e14efa68cbfc6d
CRs-Fixed: 3619199

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qcacmn: correct casting and array write index

- correct uint32_t* casting to uint16_t* given that it can overwrite values
after is dereferenced
- correct check for "for loop" max iteration as it cou

qcacmn: correct casting and array write index

- correct uint32_t* casting to uint16_t* given that it can overwrite values
after is dereferenced
- correct check for "for loop" max iteration as it could pass and
overwrite max array size.

Change-Id: Id2b02d1eea8c4ce4d962160bea99358fe3ab5cf7
CRs-Fixed: 3622399

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qcacmn: Add debug to catch non-consecutive duplicate descriptor

Add debug to catch non-consecutive duplicate descriptor in monitor

Change-Id: I253cecf472d5d75154f5791f85761da2f6d9076e
CRs-Fixed: 36

qcacmn: Add debug to catch non-consecutive duplicate descriptor

Add debug to catch non-consecutive duplicate descriptor in monitor

Change-Id: I253cecf472d5d75154f5791f85761da2f6d9076e
CRs-Fixed: 3628868

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qcacmn: Update HAL generic APIs for Rhine architecture

Update HAL generic APIs for Rhine architecture to set the link
desc address and to get the rbm and cookie info from the rx desc.

Change-Id: I0

qcacmn: Update HAL generic APIs for Rhine architecture

Update HAL generic APIs for Rhine architecture to set the link
desc address and to get the rbm and cookie info from the rx desc.

Change-Id: I0e9f0553c19508a8404106ada780b37db2e78857
CRs-Fixed: 3631599

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qcacmn: Fix RXDMA null buffer address access issue

During mon_pdev_init RX monitor status buffers will be attached
to status ring. In case of buffer allocation failure HP will be
pointing to null bu

qcacmn: Fix RXDMA null buffer address access issue

During mon_pdev_init RX monitor status buffers will be attached
to status ring. In case of buffer allocation failure HP will be
pointing to null buffer address entry and during ring process
this index slot will be skipped. This will lead to RXDMA accessing
null buffer address descriptor.

Fix this by adjusting the HP of monitor status ring during RX
buffer allocation failures.

Change-Id: I290a724fefc6f65be058a84c97b9e6d51a08ef39
CRs-Fixed: 3268663

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qcacmn: Update per-MPDU fcs err in radiotap hdr

Update per-MPDU fcs err in radiotap hdr

Change-Id: I3570ec94435746538cccc07ec052e26a19ab6452
CRs-Fixed: 3619376

qcacmn: Add support for RXDMA buf ring for VLAN with IPA

when IPA and WDI3_VLAN is enable we require 4 RXDMA buf ring.
1 RXDMA_BUF SW for HOST
1 RXDMA_BUF SW for IPA
1 RXDMA_BUF SW for IPA_VLAN
1 RX

qcacmn: Add support for RXDMA buf ring for VLAN with IPA

when IPA and WDI3_VLAN is enable we require 4 RXDMA buf ring.
1 RXDMA_BUF SW for HOST
1 RXDMA_BUF SW for IPA
1 RXDMA_BUF SW for IPA_VLAN
1 RXDMA_BUF HW ring

Change-Id: I71b75541c87aaf3a89be023241b6dcd163fc21bb
CRs-Fixed: 3614234

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qcacmn: Add fisa table to ssr dump

Add fisa table to ssr dump

Change-Id: Iebf98bfbcb990d21498e1a1946ebc8a0e0b31410
CRs-Fixed: 3604904

qcacmn: Avoid redundant register read

In hal_write32_mb_confirm_retry(), hal_read32_mb() invoked
after hal_write32_mb_confirm() to confirm whether the write-op
executed successfully, which is not ne

qcacmn: Avoid redundant register read

In hal_write32_mb_confirm_retry(), hal_read32_mb() invoked
after hal_write32_mb_confirm() to confirm whether the write-op
executed successfully, which is not necessary in case it was
already confirmed in hal_write32_mb_confirm().

Avoid such redundant register read, if it is confirmed already.

Change-Id: Ib7c0ec5e9b8e99de8f2548718f12ecddc94c792e
CRs-Fixed: 3617529

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qcacmn: Add Word mask MPDU END TLV for monitor

Receiving MPDU end TLV length as 0
because TLV compaction is enabled and
wmask for mpdu end tlv is set to 0.

Adding word mask for MPDU END TLV.

Chang

qcacmn: Add Word mask MPDU END TLV for monitor

Receiving MPDU end TLV length as 0
because TLV compaction is enabled and
wmask for mpdu end tlv is set to 0.

Adding word mask for MPDU END TLV.

Change-Id: If065cbf19f979734123a433e467a8a9bb8a1013a
CRs-Fixed: 3613053

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