1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _DP_TYPES_H_ 21 #define _DP_TYPES_H_ 22 23 #include <qdf_types.h> 24 #include <qdf_nbuf.h> 25 #include <qdf_lock.h> 26 #include <qdf_atomic.h> 27 #include <qdf_util.h> 28 #include <qdf_list.h> 29 #include <qdf_lro.h> 30 #include <queue.h> 31 #include <htt_common.h> 32 #include <htt.h> 33 #include <htt_stats.h> 34 #include <cdp_txrx_cmn.h> 35 #ifdef DP_MOB_DEFS 36 #include <cds_ieee80211_common.h> 37 #endif 38 #include <wdi_event_api.h> /* WDI subscriber event list */ 39 40 #include "hal_hw_headers.h" 41 #include <hal_tx.h> 42 #include <hal_reo.h> 43 #include "wlan_cfg.h" 44 #include "hal_rx.h" 45 #include <hal_api.h> 46 #include <hal_api_mon.h> 47 #include "hal_rx.h" 48 49 #define dp_init_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_DP_INIT, params) 50 #define dp_init_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_DP_INIT, params) 51 #define dp_init_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_DP_INIT, params) 52 #define dp_init_info(params...) \ 53 __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_DP_INIT, ## params) 54 #define dp_init_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_INIT, params) 55 56 #define dp_vdev_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_DP_VDEV, params) 57 #define dp_vdev_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_DP_VDEV, params) 58 #define dp_vdev_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_DP_VDEV, params) 59 #define dp_vdev_info(params...) \ 60 __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_DP_VDEV, ## params) 61 #define dp_vdev_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_VDEV, params) 62 63 #define MAX_BW 8 64 #define MAX_RETRIES 4 65 #define MAX_RECEPTION_TYPES 4 66 67 #define MINIDUMP_STR_SIZE 25 68 #include <dp_umac_reset.h> 69 70 #define REPT_MU_MIMO 1 71 #define REPT_MU_OFDMA_MIMO 3 72 #define DP_VO_TID 6 73 /** MAX TID MAPS AVAILABLE PER PDEV */ 74 #define DP_MAX_TID_MAPS 16 75 /** pad DSCP_TID_MAP_MAX with 6 to fix oob issue */ 76 #define DSCP_TID_MAP_MAX (64 + 6) 77 #define DP_IP_DSCP_SHIFT 2 78 #define DP_IP_DSCP_MASK 0x3f 79 #define DP_FC0_SUBTYPE_QOS 0x80 80 #define DP_QOS_TID 0x0f 81 #define DP_IPV6_PRIORITY_SHIFT 20 82 #define MAX_MON_LINK_DESC_BANKS 2 83 #define DP_VDEV_ALL CDP_VDEV_ALL 84 85 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 86 #define WLAN_DP_RESET_MON_BUF_RING_FILTER 87 #define MAX_TXDESC_POOLS 6 88 #else 89 #define MAX_TXDESC_POOLS 4 90 #endif 91 92 /* Max no of descriptors to handle special frames like EAPOL */ 93 #define MAX_TX_SPL_DESC 1024 94 95 #define MAX_RXDESC_POOLS 4 96 #define MAX_PPE_TXDESC_POOLS 1 97 98 /* Max no. of VDEV per PSOC */ 99 #ifdef WLAN_PSOC_MAX_VDEVS 100 #define MAX_VDEV_CNT WLAN_PSOC_MAX_VDEVS 101 #else 102 #define MAX_VDEV_CNT 51 103 #endif 104 105 /* Max no. of VDEVs, a PDEV can support */ 106 #ifdef WLAN_PDEV_MAX_VDEVS 107 #define DP_PDEV_MAX_VDEVS WLAN_PDEV_MAX_VDEVS 108 #else 109 #define DP_PDEV_MAX_VDEVS 17 110 #endif 111 112 #define EXCEPTION_DEST_RING_ID 0 113 #define MAX_IDLE_SCATTER_BUFS 16 114 #define DP_MAX_IRQ_PER_CONTEXT 12 115 #define DEFAULT_HW_PEER_ID 0xffff 116 117 #define MAX_AST_AGEOUT_COUNT 128 118 119 #ifdef TX_ADDR_INDEX_SEARCH 120 #define DP_TX_ADDR_SEARCH_ADDR_POLICY HAL_TX_ADDR_INDEX_SEARCH 121 #else 122 #define DP_TX_ADDR_SEARCH_ADDR_POLICY HAL_TX_ADDR_SEARCH_DEFAULT 123 #endif 124 125 #define WBM_INT_ERROR_ALL 0 126 #define WBM_INT_ERROR_REO_NULL_BUFFER 1 127 #define WBM_INT_ERROR_REO_NULL_LINK_DESC 2 128 #define WBM_INT_ERROR_REO_NULL_MSDU_BUFF 3 129 #define WBM_INT_ERROR_REO_BUFF_REAPED 4 130 #define MAX_WBM_INT_ERROR_REASONS 5 131 132 #define MAX_TX_HW_QUEUES MAX_TCL_DATA_RINGS 133 /* Maximum retries for Delba per tid per peer */ 134 #define DP_MAX_DELBA_RETRY 3 135 136 #ifdef AST_OFFLOAD_ENABLE 137 #define AST_OFFLOAD_ENABLE_STATUS 1 138 #else 139 #define AST_OFFLOAD_ENABLE_STATUS 0 140 #endif 141 142 #ifdef FEATURE_MEC_OFFLOAD 143 #define FW_MEC_FW_OFFLOAD_ENABLED 1 144 #else 145 #define FW_MEC_FW_OFFLOAD_ENABLED 0 146 #endif 147 148 #define PCP_TID_MAP_MAX 8 149 #define MAX_MU_USERS 37 150 151 #define REO_CMD_EVENT_HIST_MAX 64 152 153 #define DP_MAX_SRNGS 64 154 155 /* 2G PHYB */ 156 #define PHYB_2G_LMAC_ID 2 157 #define PHYB_2G_TARGET_PDEV_ID 2 158 159 /* Flags for skippig s/w tid classification */ 160 #define DP_TX_HW_DSCP_TID_MAP_VALID 0x1 161 #define DP_TXRX_HLOS_TID_OVERRIDE_ENABLED 0x2 162 #define DP_TX_MESH_ENABLED 0x4 163 #define DP_TX_INVALID_QOS_TAG 0xf 164 165 #ifdef WLAN_FEATURE_RX_PREALLOC_BUFFER_POOL 166 #define DP_RX_REFILL_BUFF_POOL_BURST 64 167 #endif 168 169 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 170 #define DP_RX_FSE_FLOW_MATCH_SFE 0xAAAA 171 #endif 172 173 #ifdef WLAN_VENDOR_SPECIFIC_BAR_UPDATE 174 #define DP_SKIP_BAR_UPDATE_TIMEOUT 5000 175 #endif 176 177 #define DP_TX_MAGIC_PATTERN_INUSE 0xABCD1234 178 #define DP_TX_MAGIC_PATTERN_FREE 0xDEADBEEF 179 180 #define DP_INTR_POLL_TIMER_MS 5 181 182 #ifdef IPA_OFFLOAD 183 #define DP_PEER_REO_STATS_TID_SHIFT 16 184 #define DP_PEER_REO_STATS_TID_MASK 0xFFFF0000 185 #define DP_PEER_REO_STATS_PEER_ID_MASK 0x0000FFFF 186 #define DP_PEER_GET_REO_STATS_TID(comb_peer_id_tid) \ 187 ((comb_peer_id_tid & DP_PEER_REO_STATS_TID_MASK) >> \ 188 DP_PEER_REO_STATS_TID_SHIFT) 189 #define DP_PEER_GET_REO_STATS_PEER_ID(comb_peer_id_tid) \ 190 (comb_peer_id_tid & DP_PEER_REO_STATS_PEER_ID_MASK) 191 #endif 192 193 typedef void dp_ptnr_soc_iter_func(struct dp_soc *ptnr_soc, void *arg, 194 int chip_id); 195 196 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 197 #define DP_MLD_MODE_UNIFIED_NONBOND 0 198 #define DP_MLD_MODE_UNIFIED_BOND 1 199 #define DP_MLD_MODE_HYBRID_NONBOND 2 200 #define DP_MLD_MODE_MAX DP_MLD_MODE_HYBRID_NONBOND 201 202 #define DP_LINK_VDEV_ITER 1 203 #define DP_BRIDGE_VDEV_ITER 2 204 #define DP_ALL_VDEV_ITER 3 205 #define IS_LINK_VDEV_ITER_REQUIRED(type) (type & DP_LINK_VDEV_ITER) 206 #define IS_BRIDGE_VDEV_ITER_REQUIRED(type) (type & DP_BRIDGE_VDEV_ITER) 207 #define DP_VDEV_ITERATE_ALL 1 208 #define DP_VDEV_ITERATE_SKIP_SELF 0 209 #endif 210 211 enum rx_pktlog_mode { 212 DP_RX_PKTLOG_DISABLED = 0, 213 DP_RX_PKTLOG_FULL, 214 DP_RX_PKTLOG_LITE, 215 }; 216 217 /* enum m_copy_mode - Available mcopy mode 218 * 219 */ 220 enum m_copy_mode { 221 M_COPY_DISABLED = 0, 222 M_COPY = 2, 223 M_COPY_EXTENDED = 4, 224 }; 225 226 struct msdu_list { 227 qdf_nbuf_t head; 228 qdf_nbuf_t tail; 229 uint32_t sum_len; 230 }; 231 232 struct dp_soc_cmn; 233 struct dp_pdev; 234 struct dp_vdev; 235 struct dp_tx_desc_s; 236 struct dp_soc; 237 union dp_rx_desc_list_elem_t; 238 struct cdp_peer_rate_stats_ctx; 239 struct cdp_soc_rate_stats_ctx; 240 struct dp_rx_fst; 241 struct dp_mon_filter; 242 struct dp_mon_mpdu; 243 #ifdef BE_PKTLOG_SUPPORT 244 struct dp_mon_filter_be; 245 #endif 246 struct dp_peer; 247 struct dp_txrx_peer; 248 249 /** 250 * enum dp_peer_state - DP peer states 251 * @DP_PEER_STATE_NONE: 252 * @DP_PEER_STATE_INIT: 253 * @DP_PEER_STATE_ACTIVE: 254 * @DP_PEER_STATE_LOGICAL_DELETE: 255 * @DP_PEER_STATE_INACTIVE: 256 * @DP_PEER_STATE_FREED: 257 * @DP_PEER_STATE_INVALID: 258 */ 259 enum dp_peer_state { 260 DP_PEER_STATE_NONE, 261 DP_PEER_STATE_INIT, 262 DP_PEER_STATE_ACTIVE, 263 DP_PEER_STATE_LOGICAL_DELETE, 264 DP_PEER_STATE_INACTIVE, 265 DP_PEER_STATE_FREED, 266 DP_PEER_STATE_INVALID, 267 }; 268 269 /** 270 * enum dp_mod_id - DP module IDs 271 * @DP_MOD_ID_TX_RX: 272 * @DP_MOD_ID_TX_COMP: 273 * @DP_MOD_ID_RX: 274 * @DP_MOD_ID_HTT_COMP: 275 * @DP_MOD_ID_RX_ERR: 276 * @DP_MOD_ID_TX_PPDU_STATS: 277 * @DP_MOD_ID_RX_PPDU_STATS: 278 * @DP_MOD_ID_CDP: 279 * @DP_MOD_ID_GENERIC_STATS: 280 * @DP_MOD_ID_TX_MULTIPASS: 281 * @DP_MOD_ID_TX_CAPTURE: 282 * @DP_MOD_ID_NSS_OFFLOAD: 283 * @DP_MOD_ID_CONFIG: 284 * @DP_MOD_ID_HTT: 285 * @DP_MOD_ID_IPA: 286 * @DP_MOD_ID_AST: 287 * @DP_MOD_ID_MCAST2UCAST: 288 * @DP_MOD_ID_CHILD: 289 * @DP_MOD_ID_MESH: 290 * @DP_MOD_ID_TX_EXCEPTION: 291 * @DP_MOD_ID_TDLS: 292 * @DP_MOD_ID_MISC: 293 * @DP_MOD_ID_MSCS: 294 * @DP_MOD_ID_TX: 295 * @DP_MOD_ID_SAWF: 296 * @DP_MOD_ID_REINJECT: 297 * @DP_MOD_ID_SCS: 298 * @DP_MOD_ID_UMAC_RESET: 299 * @DP_MOD_ID_TX_MCAST: 300 * @DP_MOD_ID_DS: 301 * @DP_MOD_ID_MLO_DEV: 302 * @DP_MOD_ID_MAX: 303 */ 304 enum dp_mod_id { 305 DP_MOD_ID_TX_RX, 306 DP_MOD_ID_TX_COMP, 307 DP_MOD_ID_RX, 308 DP_MOD_ID_HTT_COMP, 309 DP_MOD_ID_RX_ERR, 310 DP_MOD_ID_TX_PPDU_STATS, 311 DP_MOD_ID_RX_PPDU_STATS, 312 DP_MOD_ID_CDP, 313 DP_MOD_ID_GENERIC_STATS, 314 DP_MOD_ID_TX_MULTIPASS, 315 DP_MOD_ID_TX_CAPTURE, 316 DP_MOD_ID_NSS_OFFLOAD, 317 DP_MOD_ID_CONFIG, 318 DP_MOD_ID_HTT, 319 DP_MOD_ID_IPA, 320 DP_MOD_ID_AST, 321 DP_MOD_ID_MCAST2UCAST, 322 DP_MOD_ID_CHILD, 323 DP_MOD_ID_MESH, 324 DP_MOD_ID_TX_EXCEPTION, 325 DP_MOD_ID_TDLS, 326 DP_MOD_ID_MISC, 327 DP_MOD_ID_MSCS, 328 DP_MOD_ID_TX, 329 DP_MOD_ID_SAWF, 330 DP_MOD_ID_REINJECT, 331 DP_MOD_ID_SCS, 332 DP_MOD_ID_UMAC_RESET, 333 DP_MOD_ID_TX_MCAST, 334 DP_MOD_ID_DS, 335 DP_MOD_ID_MLO_DEV, 336 DP_MOD_ID_MAX, 337 }; 338 339 /** 340 * enum dp_peer_type - DP peer type 341 * @DP_PEER_TYPE_LEGACY: 342 * @DP_PEER_TYPE_MLO_LINK: 343 * @DP_PEER_TYPE_MLO: 344 */ 345 enum dp_peer_type { 346 DP_PEER_TYPE_LEGACY, 347 DP_PEER_TYPE_MLO_LINK, 348 DP_PEER_TYPE_MLO, 349 }; 350 351 #define DP_PDEV_ITERATE_VDEV_LIST(_pdev, _vdev) \ 352 TAILQ_FOREACH((_vdev), &(_pdev)->vdev_list, vdev_list_elem) 353 354 #define DP_VDEV_ITERATE_PEER_LIST(_vdev, _peer) \ 355 TAILQ_FOREACH((_peer), &(_vdev)->peer_list, peer_list_elem) 356 357 #define DP_PEER_ITERATE_ASE_LIST(_peer, _ase, _temp_ase) \ 358 TAILQ_FOREACH_SAFE((_ase), &_peer->ast_entry_list, ase_list_elem, (_temp_ase)) 359 360 #define DP_MUTEX_TYPE qdf_spinlock_t 361 362 #define DP_FRAME_IS_MULTICAST(_a) (*(_a) & 0x01) 363 #define DP_FRAME_IS_IPV4_MULTICAST(_a) (*(_a) == 0x01) 364 365 #define DP_FRAME_IS_IPV6_MULTICAST(_a) \ 366 ((_a)[0] == 0x33 && \ 367 (_a)[1] == 0x33) 368 369 #define DP_FRAME_IS_BROADCAST(_a) \ 370 ((_a)[0] == 0xff && \ 371 (_a)[1] == 0xff && \ 372 (_a)[2] == 0xff && \ 373 (_a)[3] == 0xff && \ 374 (_a)[4] == 0xff && \ 375 (_a)[5] == 0xff) 376 #define DP_FRAME_IS_SNAP(_llc) ((_llc)->llc_dsap == 0xaa && \ 377 (_llc)->llc_ssap == 0xaa && \ 378 (_llc)->llc_un.type_snap.control == 0x3) 379 #define DP_FRAME_IS_LLC(typeorlen) ((typeorlen) >= 0x600) 380 #define DP_FRAME_FC0_TYPE_MASK 0x0c 381 #define DP_FRAME_FC0_TYPE_DATA 0x08 382 #define DP_FRAME_IS_DATA(_frame) \ 383 (((_frame)->i_fc[0] & DP_FRAME_FC0_TYPE_MASK) == DP_FRAME_FC0_TYPE_DATA) 384 385 /* 386 * macros to convert hw mac id to sw mac id: 387 * mac ids used by hardware start from a value of 1 while 388 * those in host software start from a value of 0. Use the 389 * macros below to convert between mac ids used by software and 390 * hardware 391 */ 392 #define DP_SW2HW_MACID(id) ((id) + 1) 393 #define DP_HW2SW_MACID(id) ((id) > 0 ? ((id) - 1) : 0) 394 395 /* 396 * Number of Tx Queues 397 * enum and macro to define how many threshold levels is used 398 * for the AC based flow control 399 */ 400 #ifdef QCA_AC_BASED_FLOW_CONTROL 401 enum dp_fl_ctrl_threshold { 402 DP_TH_BE_BK = 0, 403 DP_TH_VI, 404 DP_TH_VO, 405 DP_TH_HI, 406 }; 407 408 #define FL_TH_MAX (4) 409 #define FL_TH_VI_PERCENTAGE (80) 410 #define FL_TH_VO_PERCENTAGE (60) 411 #define FL_TH_HI_PERCENTAGE (40) 412 #endif 413 414 /** 415 * enum dp_intr_mode 416 * @DP_INTR_INTEGRATED: Line interrupts 417 * @DP_INTR_MSI: MSI interrupts 418 * @DP_INTR_POLL: Polling 419 * @DP_INTR_LEGACY_VIRTUAL_IRQ: 420 */ 421 enum dp_intr_mode { 422 DP_INTR_INTEGRATED = 0, 423 DP_INTR_MSI, 424 DP_INTR_POLL, 425 DP_INTR_LEGACY_VIRTUAL_IRQ, 426 }; 427 428 /** 429 * enum dp_tx_frm_type 430 * @dp_tx_frm_std: Regular frame, no added header fragments 431 * @dp_tx_frm_tso: TSO segment, with a modified IP header added 432 * @dp_tx_frm_sg: SG segment 433 * @dp_tx_frm_audio: Audio frames, a custom LLC/SNAP header added 434 * @dp_tx_frm_me: Multicast to Unicast Converted frame 435 * @dp_tx_frm_raw: Raw Frame 436 * @dp_tx_frm_rmnet: 437 */ 438 enum dp_tx_frm_type { 439 dp_tx_frm_std = 0, 440 dp_tx_frm_tso, 441 dp_tx_frm_sg, 442 dp_tx_frm_audio, 443 dp_tx_frm_me, 444 dp_tx_frm_raw, 445 dp_tx_frm_rmnet, 446 }; 447 448 /** 449 * enum dp_ast_type 450 * @dp_ast_type_wds: WDS peer AST type 451 * @dp_ast_type_static: static ast entry type 452 * @dp_ast_type_mec: Multicast echo ast entry type 453 */ 454 enum dp_ast_type { 455 dp_ast_type_wds = 0, 456 dp_ast_type_static, 457 dp_ast_type_mec, 458 }; 459 460 /** 461 * enum dp_nss_cfg 462 * @dp_nss_cfg_default: No radios are offloaded 463 * @dp_nss_cfg_first_radio: First radio offloaded 464 * @dp_nss_cfg_second_radio: Second radio offloaded 465 * @dp_nss_cfg_dbdc: Dual radios offloaded 466 * @dp_nss_cfg_dbtc: Three radios offloaded 467 * @dp_nss_cfg_max: max value 468 */ 469 enum dp_nss_cfg { 470 dp_nss_cfg_default = 0x0, 471 dp_nss_cfg_first_radio = 0x1, 472 dp_nss_cfg_second_radio = 0x2, 473 dp_nss_cfg_dbdc = 0x3, 474 dp_nss_cfg_dbtc = 0x7, 475 dp_nss_cfg_max 476 }; 477 478 #ifdef WLAN_TX_PKT_CAPTURE_ENH 479 #define DP_CPU_RING_MAP_1 1 480 #endif 481 482 /** 483 * enum dp_cpu_ring_map_types - dp tx cpu ring map 484 * @DP_NSS_DEFAULT_MAP: Default mode with no NSS offloaded 485 * @DP_NSS_FIRST_RADIO_OFFLOADED_MAP: Only First Radio is offloaded 486 * @DP_NSS_SECOND_RADIO_OFFLOADED_MAP: Only second radio is offloaded 487 * @DP_NSS_DBDC_OFFLOADED_MAP: Both radios are offloaded 488 * @DP_NSS_DBTC_OFFLOADED_MAP: All three radios are offloaded 489 * @DP_SINGLE_TX_RING_MAP: to avoid out of order all cpu mapped to single ring 490 * @DP_NSS_CPU_RING_MAP_MAX: Max cpu ring map val 491 */ 492 enum dp_cpu_ring_map_types { 493 DP_NSS_DEFAULT_MAP, 494 DP_NSS_FIRST_RADIO_OFFLOADED_MAP, 495 DP_NSS_SECOND_RADIO_OFFLOADED_MAP, 496 DP_NSS_DBDC_OFFLOADED_MAP, 497 DP_NSS_DBTC_OFFLOADED_MAP, 498 #ifdef WLAN_TX_PKT_CAPTURE_ENH 499 DP_SINGLE_TX_RING_MAP, 500 #endif 501 DP_NSS_CPU_RING_MAP_MAX 502 }; 503 504 /** 505 * struct dp_rx_nbuf_frag_info - Hold vaddr and paddr for a buffer 506 * 507 * @paddr: Physical address of buffer allocated. 508 * @virt_addr: union of virtual address representations 509 * @nbuf: Allocated nbuf in case of nbuf approach. 510 * @vaddr: Virtual address of frag allocated in case of frag approach. 511 */ 512 struct dp_rx_nbuf_frag_info { 513 qdf_dma_addr_t paddr; 514 union { 515 qdf_nbuf_t nbuf; 516 qdf_frag_t vaddr; 517 } virt_addr; 518 }; 519 520 /** 521 * enum dp_ctxt_type - context type 522 * @DP_PDEV_TYPE: PDEV context 523 * @DP_RX_RING_HIST_TYPE: Datapath rx ring history 524 * @DP_RX_ERR_RING_HIST_TYPE: Datapath rx error ring history 525 * @DP_RX_REINJECT_RING_HIST_TYPE: Datapath reinject ring history 526 * @DP_TX_TCL_HIST_TYPE: 527 * @DP_TX_COMP_HIST_TYPE: 528 * @DP_FISA_RX_FT_TYPE: 529 * @DP_RX_REFILL_RING_HIST_TYPE: Datapath rx refill ring history 530 * @DP_TX_HW_DESC_HIST_TYPE: Datapath TX HW descriptor history 531 * @DP_MON_SOC_TYPE: Datapath monitor soc context 532 * @DP_MON_PDEV_TYPE: Datapath monitor pdev context 533 * @DP_MON_STATUS_BUF_HIST_TYPE: DP monitor status buffer history 534 * @DP_CFG_EVENT_HIST_TYPE: DP config events history 535 * @DP_MON_TX_DESC_POOL_TYPE: DP TX desc pool buffer 536 * @DP_MON_RX_DESC_POOL_TYPE: DP RX desc pool buffer 537 */ 538 enum dp_ctxt_type { 539 DP_PDEV_TYPE, 540 DP_RX_RING_HIST_TYPE, 541 DP_RX_ERR_RING_HIST_TYPE, 542 DP_RX_REINJECT_RING_HIST_TYPE, 543 DP_TX_TCL_HIST_TYPE, 544 DP_TX_COMP_HIST_TYPE, 545 DP_FISA_RX_FT_TYPE, 546 DP_RX_REFILL_RING_HIST_TYPE, 547 DP_TX_HW_DESC_HIST_TYPE, 548 DP_MON_SOC_TYPE, 549 DP_MON_PDEV_TYPE, 550 DP_MON_STATUS_BUF_HIST_TYPE, 551 DP_CFG_EVENT_HIST_TYPE, 552 DP_MON_TX_DESC_POOL_TYPE, 553 DP_MON_RX_DESC_POOL_TYPE, 554 }; 555 556 /** 557 * struct rx_desc_pool 558 * @pool_size: number of RX descriptor in the pool 559 * @elem_size: Element size 560 * @desc_pages: Multi page descriptors 561 * @array: pointer to array of RX descriptor 562 * @freelist: pointer to free RX descriptor link list 563 * @lock: Protection for the RX descriptor pool 564 * @owner: owner for nbuf 565 * @buf_size: Buffer size 566 * @buf_alignment: Buffer alignment 567 * @rx_mon_dest_frag_enable: Enable frag processing for mon dest buffer 568 * @pf_cache: page frag cache 569 * @desc_type: type of desc this pool serves 570 */ 571 struct rx_desc_pool { 572 uint32_t pool_size; 573 #ifdef RX_DESC_MULTI_PAGE_ALLOC 574 uint16_t elem_size; 575 struct qdf_mem_multi_page_t desc_pages; 576 #else 577 union dp_rx_desc_list_elem_t *array; 578 #endif 579 union dp_rx_desc_list_elem_t *freelist; 580 qdf_spinlock_t lock; 581 uint8_t owner; 582 uint16_t buf_size; 583 uint8_t buf_alignment; 584 bool rx_mon_dest_frag_enable; 585 qdf_frag_cache_t pf_cache; 586 enum qdf_dp_desc_type desc_type; 587 }; 588 589 /** 590 * struct dp_tx_ext_desc_elem_s 591 * @next: next extension descriptor pointer 592 * @vaddr: hlos virtual address pointer 593 * @paddr: physical address pointer for descriptor 594 * @flags: mark features for extension descriptor 595 * @me_buffer: Pointer to ME buffer - store this so that it can be freed on 596 * Tx completion of ME packet 597 * @tso_desc: Pointer to Tso desc 598 * @tso_num_desc: Pointer to tso_num_desc 599 */ 600 struct dp_tx_ext_desc_elem_s { 601 struct dp_tx_ext_desc_elem_s *next; 602 void *vaddr; 603 qdf_dma_addr_t paddr; 604 uint16_t flags; 605 struct dp_tx_me_buf_t *me_buffer; 606 struct qdf_tso_seg_elem_t *tso_desc; 607 struct qdf_tso_num_seg_elem_t *tso_num_desc; 608 }; 609 610 /* 611 * NB: intentionally not using kernel-doc comment because the kernel-doc 612 * script does not handle the qdf_dma_mem_context macro 613 * struct dp_tx_ext_desc_pool_s - Tx Extension Descriptor Pool 614 * @elem_count: Number of descriptors in the pool 615 * @elem_size: Size of each descriptor 616 * @num_free: Number of free descriptors 617 * @desc_pages: multiple page allocation information for actual descriptors 618 * @link_elem_size: size of the link descriptor in cacheable memory used for 619 * chaining the extension descriptors 620 * @desc_link_pages: multiple page allocation information for link descriptors 621 * @freelist: 622 * @lock: 623 * @memctx: 624 */ 625 struct dp_tx_ext_desc_pool_s { 626 uint16_t elem_count; 627 int elem_size; 628 uint16_t num_free; 629 struct qdf_mem_multi_page_t desc_pages; 630 int link_elem_size; 631 struct qdf_mem_multi_page_t desc_link_pages; 632 struct dp_tx_ext_desc_elem_s *freelist; 633 qdf_spinlock_t lock; 634 qdf_dma_mem_context(memctx); 635 }; 636 637 /** 638 * struct dp_tx_desc_s - Tx Descriptor 639 * @next: Next in the chain of descriptors in freelist or in the completion list 640 * @nbuf: Buffer Address 641 * @length: 642 * @magic: 643 * @timestamp_tick: 644 * @flags: Flags to track the state of descriptor and special frame handling 645 * @id: Descriptor ID 646 * @dma_addr: 647 * @vdev_id: vdev_id of vdev over which the packet was transmitted 648 * @tx_status: 649 * @peer_id: 650 * @pdev: Handle to pdev 651 * @tx_encap_type: Transmit encap type (i.e. Raw, Native Wi-Fi, Ethernet). 652 * This is maintained in descriptor to allow more efficient 653 * processing in completion event processing code. 654 * This field is filled in with the htt_pkt_type enum. 655 * @buffer_src: buffer source TQM, REO, FW etc. 656 * @reserved: 657 * @frm_type: Frame Type - ToDo check if this is redundant 658 * @pkt_offset: Offset from which the actual packet data starts 659 * @pool_id: Pool ID - used when releasing the descriptor 660 * @msdu_ext_desc: MSDU extension descriptor 661 * @timestamp: 662 * @driver_egress_ts: driver egress timestamp 663 * @driver_ingress_ts: driver ingress timestamp 664 * @comp: 665 * @tcl_cmd_vaddr: VADDR of the TCL descriptor, valid for soft-umac arch 666 * @tcl_cmd_paddr: PADDR of the TCL descriptor, valid for soft-umac arch 667 */ 668 struct dp_tx_desc_s { 669 struct dp_tx_desc_s *next; 670 qdf_nbuf_t nbuf; 671 uint16_t length; 672 #ifdef DP_TX_TRACKING 673 uint32_t magic; 674 uint64_t timestamp_tick; 675 #endif 676 uint32_t flags; 677 uint32_t id; 678 qdf_dma_addr_t dma_addr; 679 uint8_t vdev_id; 680 uint8_t tx_status; 681 uint16_t peer_id; 682 struct dp_pdev *pdev; 683 uint8_t tx_encap_type:2, 684 buffer_src:3, 685 reserved:3; 686 uint8_t frm_type; 687 uint8_t pkt_offset; 688 uint8_t pool_id; 689 struct dp_tx_ext_desc_elem_s *msdu_ext_desc; 690 qdf_ktime_t timestamp; 691 #ifdef WLAN_FEATURE_TX_LATENCY_STATS 692 qdf_ktime_t driver_egress_ts; 693 qdf_ktime_t driver_ingress_ts; 694 #endif 695 struct hal_tx_desc_comp_s comp; 696 #ifdef WLAN_SOFTUMAC_SUPPORT 697 void *tcl_cmd_vaddr; 698 qdf_dma_addr_t tcl_cmd_paddr; 699 #endif 700 }; 701 702 #ifdef QCA_AC_BASED_FLOW_CONTROL 703 /** 704 * enum flow_pool_status - flow pool status 705 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 706 * and network queues are unpaused 707 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 708 * and network queues are paused 709 * @FLOW_POOL_BE_BK_PAUSED: 710 * @FLOW_POOL_VI_PAUSED: 711 * @FLOW_POOL_VO_PAUSED: 712 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 713 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 714 * @FLOW_POOL_ACTIVE_UNPAUSED_REATTACH: pool is reattached but network 715 * queues are not paused 716 */ 717 enum flow_pool_status { 718 FLOW_POOL_ACTIVE_UNPAUSED = 0, 719 FLOW_POOL_ACTIVE_PAUSED = 1, 720 FLOW_POOL_BE_BK_PAUSED = 2, 721 FLOW_POOL_VI_PAUSED = 3, 722 FLOW_POOL_VO_PAUSED = 4, 723 FLOW_POOL_INVALID = 5, 724 FLOW_POOL_INACTIVE = 6, 725 FLOW_POOL_ACTIVE_UNPAUSED_REATTACH = 7, 726 }; 727 728 #else 729 /** 730 * enum flow_pool_status - flow pool status 731 * @FLOW_POOL_ACTIVE_UNPAUSED : pool is active (can take/put descriptors) 732 * and network queues are unpaused 733 * @FLOW_POOL_ACTIVE_PAUSED: pool is active (can take/put descriptors) 734 * and network queues are paused 735 * @FLOW_POOL_BE_BK_PAUSED: 736 * @FLOW_POOL_VI_PAUSED: 737 * @FLOW_POOL_VO_PAUSED: 738 * @FLOW_POOL_INVALID: pool is invalid (put descriptor) 739 * @FLOW_POOL_INACTIVE: pool is inactive (pool is free) 740 */ 741 enum flow_pool_status { 742 FLOW_POOL_ACTIVE_UNPAUSED = 0, 743 FLOW_POOL_ACTIVE_PAUSED = 1, 744 FLOW_POOL_BE_BK_PAUSED = 2, 745 FLOW_POOL_VI_PAUSED = 3, 746 FLOW_POOL_VO_PAUSED = 4, 747 FLOW_POOL_INVALID = 5, 748 FLOW_POOL_INACTIVE = 6, 749 }; 750 751 #endif 752 753 /** 754 * struct dp_tx_tso_seg_pool_s 755 * @pool_size: total number of pool elements 756 * @num_free: free element count 757 * @freelist: first free element pointer 758 * @desc_pages: multiple page allocation information for actual descriptors 759 * @lock: lock for accessing the pool 760 */ 761 struct dp_tx_tso_seg_pool_s { 762 uint16_t pool_size; 763 uint16_t num_free; 764 struct qdf_tso_seg_elem_t *freelist; 765 struct qdf_mem_multi_page_t desc_pages; 766 qdf_spinlock_t lock; 767 }; 768 769 /** 770 * struct dp_tx_tso_num_seg_pool_s - TSO Num seg pool 771 * @num_seg_pool_size: total number of pool elements 772 * @num_free: free element count 773 * @freelist: first free element pointer 774 * @desc_pages: multiple page allocation information for actual descriptors 775 * @lock: lock for accessing the pool 776 */ 777 778 struct dp_tx_tso_num_seg_pool_s { 779 uint16_t num_seg_pool_size; 780 uint16_t num_free; 781 struct qdf_tso_num_seg_elem_t *freelist; 782 struct qdf_mem_multi_page_t desc_pages; 783 /*tso mutex */ 784 qdf_spinlock_t lock; 785 }; 786 787 /** 788 * struct dp_tx_desc_pool_s - Tx Descriptor pool information 789 * @elem_size: Size of each descriptor in the pool 790 * @num_allocated: Number of used descriptors 791 * @freelist: Chain of free descriptors 792 * @desc_pages: multiple page allocation information for actual descriptors 793 * @pool_size: Total number of descriptors in the pool 794 * @flow_pool_id: 795 * @num_invalid_bin: Deleted pool with pending Tx completions. 796 * @avail_desc: 797 * @status: 798 * @flow_type: 799 * @stop_th: 800 * @start_th: 801 * @max_pause_time: 802 * @latest_pause_time: 803 * @pkt_drop_no_desc: 804 * @flow_pool_lock: 805 * @pool_create_cnt: 806 * @pool_owner_ctx: 807 * @elem_count: 808 * @num_free: Number of free descriptors 809 * @lock: Lock for descriptor allocation/free from/to the pool 810 */ 811 struct dp_tx_desc_pool_s { 812 uint16_t elem_size; 813 uint32_t num_allocated; 814 struct dp_tx_desc_s *freelist; 815 struct qdf_mem_multi_page_t desc_pages; 816 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 817 uint16_t pool_size; 818 uint8_t flow_pool_id; 819 uint8_t num_invalid_bin; 820 uint16_t avail_desc; 821 enum flow_pool_status status; 822 enum htt_flow_type flow_type; 823 #ifdef QCA_AC_BASED_FLOW_CONTROL 824 uint16_t stop_th[FL_TH_MAX]; 825 uint16_t start_th[FL_TH_MAX]; 826 qdf_time_t max_pause_time[FL_TH_MAX]; 827 qdf_time_t latest_pause_time[FL_TH_MAX]; 828 #else 829 uint16_t stop_th; 830 uint16_t start_th; 831 #endif 832 uint16_t pkt_drop_no_desc; 833 qdf_spinlock_t flow_pool_lock; 834 uint8_t pool_create_cnt; 835 void *pool_owner_ctx; 836 #else 837 uint16_t elem_count; 838 uint32_t num_free; 839 qdf_spinlock_t lock; 840 #endif 841 }; 842 843 /** 844 * struct dp_txrx_pool_stats - flow pool related statistics 845 * @pool_map_count: flow pool map received 846 * @pool_unmap_count: flow pool unmap received 847 * @pkt_drop_no_pool: packets dropped due to unavailablity of pool 848 */ 849 struct dp_txrx_pool_stats { 850 uint16_t pool_map_count; 851 uint16_t pool_unmap_count; 852 uint16_t pkt_drop_no_pool; 853 }; 854 855 /** 856 * struct dp_srng - DP srng structure 857 * @hal_srng: hal_srng handle 858 * @base_vaddr_unaligned: un-aligned virtual base address of the srng ring 859 * @base_vaddr_aligned: aligned virtual base address of the srng ring 860 * @base_paddr_unaligned: un-aligned physical base address of the srng ring 861 * @base_paddr_aligned: aligned physical base address of the srng ring 862 * @alloc_size: size of the srng ring 863 * @cached: is the srng ring memory cached or un-cached memory 864 * @irq: irq number of the srng ring 865 * @num_entries: number of entries in the srng ring 866 * @stats: Structure to track the ring utilization stats 867 * @is_mem_prealloc: Is this srng memory pre-allocated 868 * @crit_thresh: Critical threshold for near-full processing of this srng 869 * @safe_thresh: Safe threshold for near-full processing of this srng 870 * @near_full: Flag to indicate srng is near-full 871 */ 872 struct dp_srng { 873 hal_ring_handle_t hal_srng; 874 void *base_vaddr_unaligned; 875 void *base_vaddr_aligned; 876 qdf_dma_addr_t base_paddr_unaligned; 877 qdf_dma_addr_t base_paddr_aligned; 878 uint32_t alloc_size; 879 uint8_t cached; 880 int irq; 881 uint32_t num_entries; 882 struct ring_util_stats stats; 883 #ifdef DP_MEM_PRE_ALLOC 884 uint8_t is_mem_prealloc; 885 #endif 886 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 887 uint16_t crit_thresh; 888 uint16_t safe_thresh; 889 qdf_atomic_t near_full; 890 #endif 891 }; 892 893 struct dp_rx_reorder_array_elem { 894 qdf_nbuf_t head; 895 qdf_nbuf_t tail; 896 }; 897 898 #define DP_RX_BA_INACTIVE 0 899 #define DP_RX_BA_ACTIVE 1 900 #define DP_RX_BA_IN_PROGRESS 2 901 struct dp_reo_cmd_info { 902 uint16_t cmd; 903 enum hal_reo_cmd_type cmd_type; 904 void *data; 905 void (*handler)(struct dp_soc *, void *, union hal_reo_status *); 906 TAILQ_ENTRY(dp_reo_cmd_info) reo_cmd_list_elem; 907 }; 908 909 struct dp_peer_delay_stats { 910 struct cdp_delay_tid_stats delay_tid_stats[CDP_MAX_DATA_TIDS] 911 [CDP_MAX_TXRX_CTX]; 912 }; 913 914 /* Rx TID defrag*/ 915 struct dp_rx_tid_defrag { 916 /* TID */ 917 int tid; 918 919 /* only used for defrag right now */ 920 TAILQ_ENTRY(dp_rx_tid_defrag) defrag_waitlist_elem; 921 922 /* Store dst desc for reinjection */ 923 hal_ring_desc_t dst_ring_desc; 924 struct dp_rx_desc *head_frag_desc; 925 926 /* Sequence and fragments that are being processed currently */ 927 uint32_t curr_seq_num; 928 uint32_t curr_frag_num; 929 930 /* TODO: Check the following while adding defragmentation support */ 931 struct dp_rx_reorder_array_elem *array; 932 /* base - single rx reorder element used for non-aggr cases */ 933 struct dp_rx_reorder_array_elem base; 934 /* rx_tid lock */ 935 qdf_spinlock_t defrag_tid_lock; 936 937 /* head PN number */ 938 uint64_t pn128[2]; 939 940 uint32_t defrag_timeout_ms; 941 942 /* defrag usage only, dp_peer pointer related with this tid */ 943 struct dp_txrx_peer *defrag_peer; 944 }; 945 946 /* Rx TID */ 947 struct dp_rx_tid { 948 /* TID */ 949 int tid; 950 951 /* Num of addba requests */ 952 uint32_t num_of_addba_req; 953 954 /* Num of addba responses */ 955 uint32_t num_of_addba_resp; 956 957 /* Num of delba requests */ 958 uint32_t num_of_delba_req; 959 960 /* Num of addba responses successful */ 961 uint32_t num_addba_rsp_success; 962 963 /* Num of addba responses failed */ 964 uint32_t num_addba_rsp_failed; 965 966 /* pn size */ 967 uint8_t pn_size; 968 /* REO TID queue descriptors */ 969 void *hw_qdesc_vaddr_unaligned; 970 void *hw_qdesc_vaddr_aligned; 971 qdf_dma_addr_t hw_qdesc_paddr_unaligned; 972 qdf_dma_addr_t hw_qdesc_paddr; 973 uint32_t hw_qdesc_alloc_size; 974 975 /* RX ADDBA session state */ 976 int ba_status; 977 978 /* RX BA window size */ 979 uint16_t ba_win_size; 980 981 /* Starting sequence number in Addba request */ 982 uint16_t startseqnum; 983 uint16_t dialogtoken; 984 uint16_t statuscode; 985 /* user defined ADDBA response status code */ 986 uint16_t userstatuscode; 987 988 /* rx_tid lock */ 989 qdf_spinlock_t tid_lock; 990 991 /* Store ppdu_id when 2k exception is received */ 992 uint32_t ppdu_id_2k; 993 994 /* Delba Tx completion status */ 995 uint8_t delba_tx_status; 996 997 /* Delba Tx retry count */ 998 uint8_t delba_tx_retry; 999 1000 /* Delba stats */ 1001 uint32_t delba_tx_success_cnt; 1002 uint32_t delba_tx_fail_cnt; 1003 1004 /* Delba reason code for retries */ 1005 uint8_t delba_rcode; 1006 1007 /* Coex Override preserved windows size 1 based */ 1008 uint16_t rx_ba_win_size_override; 1009 #ifdef IPA_OFFLOAD 1010 /* rx msdu count per tid */ 1011 struct cdp_pkt_info rx_msdu_cnt; 1012 #endif 1013 1014 }; 1015 1016 /** 1017 * struct dp_intr_stats - DP Interrupt Stats for an interrupt context 1018 * @num_tx_ring_masks: interrupts with tx_ring_mask set 1019 * @num_rx_ring_masks: interrupts with rx_ring_mask set 1020 * @num_rx_mon_ring_masks: interrupts with rx_mon_ring_mask set 1021 * @num_rx_err_ring_masks: interrupts with rx_err_ring_mask set 1022 * @num_rx_wbm_rel_ring_masks: interrupts with rx_wbm_rel_ring_mask set 1023 * @num_reo_status_ring_masks: interrupts with reo_status_ring_mask set 1024 * @num_rxdma2host_ring_masks: interrupts with rxdma2host_ring_mask set 1025 * @num_host2rxdma_ring_masks: interrupts with host2rxdma_ring_mask set 1026 * @num_host2rxdma_mon_ring_masks: interrupts with host2rxdma_ring_mask set 1027 * @num_rx_ring_near_full_masks: Near-full interrupts for REO DST ring 1028 * @num_tx_comp_ring_near_full_masks: Near-full interrupts for TX completion 1029 * @num_rx_wbm_rel_ring_near_full_masks: total number of times the wbm rel ring 1030 * near full interrupt was received 1031 * @num_reo_status_ring_near_full_masks: total number of times the reo status 1032 * near full interrupt was received 1033 * @num_near_full_masks: total number of times the near full interrupt 1034 * was received 1035 * @num_masks: total number of times the interrupt was received 1036 * @num_host2txmon_ring__masks: interrupts with host2txmon_ring_mask set 1037 * @num_near_full_masks: total number of times the interrupt was received 1038 * @num_masks: total number of times the near full interrupt was received 1039 * @num_tx_mon_ring_masks: interrupts with num_tx_mon_ring_masks set 1040 * 1041 * Counter for individual masks are incremented only if there are any packets 1042 * on that ring. 1043 */ 1044 struct dp_intr_stats { 1045 uint32_t num_tx_ring_masks[MAX_TCL_DATA_RINGS]; 1046 uint32_t num_rx_ring_masks[MAX_REO_DEST_RINGS]; 1047 uint32_t num_rx_mon_ring_masks; 1048 uint32_t num_rx_err_ring_masks; 1049 uint32_t num_rx_wbm_rel_ring_masks; 1050 uint32_t num_reo_status_ring_masks; 1051 uint32_t num_rxdma2host_ring_masks; 1052 uint32_t num_host2rxdma_ring_masks; 1053 uint32_t num_host2rxdma_mon_ring_masks; 1054 uint32_t num_rx_ring_near_full_masks[MAX_REO_DEST_RINGS]; 1055 uint32_t num_tx_comp_ring_near_full_masks[MAX_TCL_DATA_RINGS]; 1056 uint32_t num_rx_wbm_rel_ring_near_full_masks; 1057 uint32_t num_reo_status_ring_near_full_masks; 1058 uint32_t num_host2txmon_ring__masks; 1059 uint32_t num_near_full_masks; 1060 uint32_t num_masks; 1061 uint32_t num_tx_mon_ring_masks; 1062 }; 1063 1064 #ifdef DP_UMAC_HW_RESET_SUPPORT 1065 /** 1066 * struct dp_intr_bkp - DP per interrupt context ring masks old state 1067 * @tx_ring_mask: WBM Tx completion rings (0-2) associated with this napi ctxt 1068 * @rx_ring_mask: Rx REO rings (0-3) associated with this interrupt context 1069 * @rx_mon_ring_mask: Rx monitor ring mask (0-2) 1070 * @rx_err_ring_mask: REO Exception Ring 1071 * @rx_wbm_rel_ring_mask: WBM2SW Rx Release Ring 1072 * @reo_status_ring_mask: REO command response ring 1073 * @rxdma2host_ring_mask: RXDMA to host destination ring 1074 * @host2rxdma_ring_mask: Host to RXDMA buffer ring 1075 * @host2rxdma_mon_ring_mask: Host to RXDMA monitor buffer ring 1076 * @host2txmon_ring_mask: Tx monitor buffer ring 1077 * @tx_mon_ring_mask: Tx monitor ring mask (0-2) 1078 * 1079 */ 1080 struct dp_intr_bkp { 1081 uint8_t tx_ring_mask; 1082 uint8_t rx_ring_mask; 1083 uint8_t rx_mon_ring_mask; 1084 uint8_t rx_err_ring_mask; 1085 uint8_t rx_wbm_rel_ring_mask; 1086 uint8_t reo_status_ring_mask; 1087 uint8_t rxdma2host_ring_mask; 1088 uint8_t host2rxdma_ring_mask; 1089 uint8_t host2rxdma_mon_ring_mask; 1090 uint8_t host2txmon_ring_mask; 1091 uint8_t tx_mon_ring_mask; 1092 }; 1093 #endif 1094 1095 /* per interrupt context */ 1096 struct dp_intr { 1097 uint8_t tx_ring_mask; /* WBM Tx completion rings (0-2) 1098 associated with this napi context */ 1099 uint8_t rx_ring_mask; /* Rx REO rings (0-3) associated 1100 with this interrupt context */ 1101 uint8_t rx_mon_ring_mask; /* Rx monitor ring mask (0-2) */ 1102 uint8_t rx_err_ring_mask; /* REO Exception Ring */ 1103 uint8_t rx_wbm_rel_ring_mask; /* WBM2SW Rx Release Ring */ 1104 uint8_t reo_status_ring_mask; /* REO command response ring */ 1105 uint8_t rxdma2host_ring_mask; /* RXDMA to host destination ring */ 1106 uint8_t host2rxdma_ring_mask; /* Host to RXDMA buffer ring */ 1107 /* Host to RXDMA monitor buffer ring */ 1108 uint8_t host2rxdma_mon_ring_mask; 1109 /* RX REO rings near full interrupt mask */ 1110 uint8_t rx_near_full_grp_1_mask; 1111 /* RX REO rings near full interrupt mask */ 1112 uint8_t rx_near_full_grp_2_mask; 1113 /* WBM TX completion rings near full interrupt mask */ 1114 uint8_t tx_ring_near_full_mask; 1115 uint8_t host2txmon_ring_mask; /* Tx monitor buffer ring */ 1116 uint8_t tx_mon_ring_mask; /* Tx monitor ring mask (0-2) */ 1117 struct dp_soc *soc; /* Reference to SoC structure , 1118 to get DMA ring handles */ 1119 qdf_lro_ctx_t lro_ctx; 1120 uint8_t dp_intr_id; 1121 1122 /* Interrupt Stats for individual masks */ 1123 struct dp_intr_stats intr_stats; 1124 uint8_t umac_reset_intr_mask; /* UMAC reset interrupt mask */ 1125 }; 1126 1127 #define REO_DESC_FREELIST_SIZE 64 1128 #define REO_DESC_FREE_DEFER_MS 1000 1129 struct reo_desc_list_node { 1130 qdf_list_node_t node; 1131 unsigned long free_ts; 1132 struct dp_rx_tid rx_tid; 1133 bool resend_update_reo_cmd; 1134 uint32_t pending_ext_desc_size; 1135 #ifdef REO_QDESC_HISTORY 1136 uint8_t peer_mac[QDF_MAC_ADDR_SIZE]; 1137 #endif 1138 }; 1139 1140 #ifdef WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY 1141 #define REO_DESC_DEFERRED_FREELIST_SIZE 256 1142 #define REO_DESC_DEFERRED_FREE_MS 30000 1143 1144 struct reo_desc_deferred_freelist_node { 1145 qdf_list_node_t node; 1146 unsigned long free_ts; 1147 void *hw_qdesc_vaddr_unaligned; 1148 qdf_dma_addr_t hw_qdesc_paddr; 1149 uint32_t hw_qdesc_alloc_size; 1150 #ifdef REO_QDESC_HISTORY 1151 uint8_t peer_mac[QDF_MAC_ADDR_SIZE]; 1152 #endif /* REO_QDESC_HISTORY */ 1153 }; 1154 #endif /* WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY */ 1155 1156 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 1157 /** 1158 * struct reo_cmd_event_record: Elements to record for each reo command 1159 * @cmd_type: reo command type 1160 * @cmd_return_status: reo command post status 1161 * @timestamp: record timestamp for the reo command 1162 */ 1163 struct reo_cmd_event_record { 1164 enum hal_reo_cmd_type cmd_type; 1165 uint8_t cmd_return_status; 1166 uint64_t timestamp; 1167 }; 1168 1169 /** 1170 * struct reo_cmd_event_history: Account for reo cmd events 1171 * @index: record number 1172 * @cmd_record: list of records 1173 */ 1174 struct reo_cmd_event_history { 1175 qdf_atomic_t index; 1176 struct reo_cmd_event_record cmd_record[REO_CMD_EVENT_HIST_MAX]; 1177 }; 1178 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 1179 1180 /* SoC level data path statistics */ 1181 struct dp_soc_stats { 1182 struct { 1183 uint32_t added; 1184 uint32_t deleted; 1185 uint32_t aged_out; 1186 uint32_t map_err; 1187 uint32_t ast_mismatch; 1188 } ast; 1189 1190 struct { 1191 uint32_t added; 1192 uint32_t deleted; 1193 } mec; 1194 1195 /* SOC level TX stats */ 1196 struct { 1197 /* Total packets transmitted */ 1198 struct cdp_pkt_info egress[MAX_TCL_DATA_RINGS]; 1199 /* Enqueues per tcl ring */ 1200 uint32_t tcl_enq[MAX_TCL_DATA_RINGS]; 1201 /* packets dropped on tx because of no peer */ 1202 struct cdp_pkt_info tx_invalid_peer; 1203 /* descriptors in each tcl ring */ 1204 uint32_t tcl_ring_full[MAX_TCL_DATA_RINGS]; 1205 /* Descriptors in use at soc */ 1206 uint32_t desc_in_use; 1207 /* tqm_release_reason == FW removed */ 1208 uint32_t dropped_fw_removed; 1209 /* tx completion release_src != TQM or FW */ 1210 uint32_t invalid_release_source; 1211 /* TX descriptor from completion ring Desc is not valid */ 1212 uint32_t invalid_tx_comp_desc; 1213 /* tx completion wbm_internal_error */ 1214 uint32_t wbm_internal_error[MAX_WBM_INT_ERROR_REASONS]; 1215 /* tx completion non_wbm_internal_error */ 1216 uint32_t non_wbm_internal_err; 1217 /* TX Comp loop packet limit hit */ 1218 uint32_t tx_comp_loop_pkt_limit_hit; 1219 /* Head pointer Out of sync at the end of dp_tx_comp_handler */ 1220 uint32_t hp_oos2; 1221 /* tx desc freed as part of vdev detach */ 1222 uint32_t tx_comp_exception; 1223 /* TQM drops after/during peer delete */ 1224 uint64_t tqm_drop_no_peer; 1225 /* Number of tx completions reaped per WBM2SW release ring */ 1226 uint32_t tx_comp[MAX_TCL_DATA_RINGS]; 1227 /* Number of tx completions force freed */ 1228 uint32_t tx_comp_force_freed; 1229 /* Tx completion ring near full */ 1230 uint32_t near_full; 1231 /* Tx drops with buffer src as HAL_TX_COMP_RELEASE_SOURCE_FW */ 1232 uint32_t fw2wbm_tx_drop; 1233 } tx; 1234 1235 /* SOC level RX stats */ 1236 struct { 1237 /* Total rx packets count */ 1238 struct cdp_pkt_info ingress; 1239 /* Rx errors */ 1240 /* Total Packets in Rx Error ring */ 1241 uint32_t err_ring_pkts; 1242 /* No of Fragments */ 1243 uint32_t rx_frags; 1244 /* No of incomplete fragments in waitlist */ 1245 uint32_t rx_frag_wait; 1246 /* Fragments dropped due to errors */ 1247 uint32_t rx_frag_err; 1248 /* Fragments received OOR causing sequence num mismatch */ 1249 uint32_t rx_frag_oor; 1250 /* Fragments dropped due to len errors in skb */ 1251 uint32_t rx_frag_err_len_error; 1252 /* Fragments dropped due to no peer found */ 1253 uint32_t rx_frag_err_no_peer; 1254 /* No of reinjected packets */ 1255 uint32_t reo_reinject; 1256 /* Reap loop packet limit hit */ 1257 uint32_t reap_loop_pkt_limit_hit; 1258 /* Head pointer Out of sync at the end of dp_rx_process */ 1259 uint32_t hp_oos2; 1260 /* Rx ring near full */ 1261 uint32_t near_full; 1262 /* Break ring reaping as not all scattered msdu received */ 1263 uint32_t msdu_scatter_wait_break; 1264 /* Number of bar frames received */ 1265 uint32_t bar_frame; 1266 /* Number of frames routed from rxdma */ 1267 uint32_t rxdma2rel_route_drop; 1268 /* Number of frames routed from reo*/ 1269 uint32_t reo2rel_route_drop; 1270 uint64_t fast_recycled; 1271 /* Number of hw stats requested */ 1272 uint32_t rx_hw_stats_requested; 1273 /* Number of hw stats request timeout */ 1274 uint32_t rx_hw_stats_timeout; 1275 1276 struct { 1277 /* Invalid RBM error count */ 1278 uint32_t invalid_rbm; 1279 /* Invalid VDEV Error count */ 1280 uint32_t invalid_vdev; 1281 /* Invalid PDEV error count */ 1282 uint32_t invalid_pdev; 1283 1284 /* Packets delivered to stack that no related peer */ 1285 uint32_t pkt_delivered_no_peer; 1286 /* Defrag peer uninit error count */ 1287 uint32_t defrag_peer_uninit; 1288 /* Invalid sa_idx or da_idx*/ 1289 uint32_t invalid_sa_da_idx; 1290 /* MSDU DONE failures */ 1291 uint32_t msdu_done_fail; 1292 /* Invalid PEER Error count */ 1293 struct cdp_pkt_info rx_invalid_peer; 1294 /* Invalid PEER ID count */ 1295 struct cdp_pkt_info rx_invalid_peer_id; 1296 /* Invalid packet length */ 1297 struct cdp_pkt_info rx_invalid_pkt_len; 1298 /* HAL ring access Fail error count */ 1299 uint32_t hal_ring_access_fail; 1300 /* HAL ring access full Fail error count */ 1301 uint32_t hal_ring_access_full_fail; 1302 /* RX DMA error count */ 1303 uint32_t rxdma_error[HAL_RXDMA_ERR_MAX]; 1304 /* RX REO DEST Desc Invalid Magic count */ 1305 uint32_t rx_desc_invalid_magic; 1306 /* REO Error count */ 1307 uint32_t reo_error[HAL_REO_ERR_MAX]; 1308 /* HAL REO ERR Count */ 1309 uint32_t hal_reo_error[MAX_REO_DEST_RINGS]; 1310 /* HAL REO DEST Duplicate count */ 1311 uint32_t hal_reo_dest_dup; 1312 /* HAL WBM RELEASE Duplicate count */ 1313 uint32_t hal_wbm_rel_dup; 1314 /* HAL RXDMA error Duplicate count */ 1315 uint32_t hal_rxdma_err_dup; 1316 /* ipa smmu map duplicate count */ 1317 uint32_t ipa_smmu_map_dup; 1318 /* ipa smmu unmap duplicate count */ 1319 uint32_t ipa_smmu_unmap_dup; 1320 /* ipa smmu unmap while ipa pipes is disabled */ 1321 uint32_t ipa_unmap_no_pipe; 1322 /* REO cmd send fail/requeue count */ 1323 uint32_t reo_cmd_send_fail; 1324 /* REO cmd send drain count */ 1325 uint32_t reo_cmd_send_drain; 1326 /* RX msdu drop count due to scatter */ 1327 uint32_t scatter_msdu; 1328 /* RX msdu drop count due to invalid cookie */ 1329 uint32_t invalid_cookie; 1330 /* Count of stale cookie read in RX path */ 1331 uint32_t stale_cookie; 1332 /* Delba sent count due to RX 2k jump */ 1333 uint32_t rx_2k_jump_delba_sent; 1334 /* RX 2k jump msdu indicated to stack count */ 1335 uint32_t rx_2k_jump_to_stack; 1336 /* RX 2k jump msdu dropped count */ 1337 uint32_t rx_2k_jump_drop; 1338 /* REO ERR msdu buffer received */ 1339 uint32_t reo_err_msdu_buf_rcved; 1340 /* REO ERR msdu buffer with invalid coookie received */ 1341 uint32_t reo_err_msdu_buf_invalid_cookie; 1342 /* REO OOR msdu drop count */ 1343 uint32_t reo_err_oor_drop; 1344 /* REO OOR msdu indicated to stack count */ 1345 uint32_t reo_err_oor_to_stack; 1346 /* REO OOR scattered msdu count */ 1347 uint32_t reo_err_oor_sg_count; 1348 /* RX msdu rejected count on delivery to vdev stack_fn*/ 1349 uint32_t rejected; 1350 /* Incorrect msdu count in MPDU desc info */ 1351 uint32_t msdu_count_mismatch; 1352 /* RX raw frame dropped count */ 1353 uint32_t raw_frm_drop; 1354 /* Stale link desc cookie count*/ 1355 uint32_t invalid_link_cookie; 1356 /* Nbuf sanity failure */ 1357 uint32_t nbuf_sanity_fail; 1358 /* Duplicate link desc refilled */ 1359 uint32_t dup_refill_link_desc; 1360 /* Incorrect msdu continuation bit in MSDU desc */ 1361 uint32_t msdu_continuation_err; 1362 /* count of start sequence (ssn) updates */ 1363 uint32_t ssn_update_count; 1364 /* count of bar handling fail */ 1365 uint32_t bar_handle_fail_count; 1366 /* EAPOL drop count in intrabss scenario */ 1367 uint32_t intrabss_eapol_drop; 1368 /* PN check failed for 2K-jump or OOR error */ 1369 uint32_t pn_in_dest_check_fail; 1370 /* MSDU len err count */ 1371 uint32_t msdu_len_err; 1372 /* Rx flush count */ 1373 uint32_t rx_flush_count; 1374 /* Rx invalid tid count */ 1375 uint32_t rx_invalid_tid_err; 1376 /* Invalid address1 in defrag path*/ 1377 uint32_t defrag_ad1_invalid; 1378 /* decrypt error drop */ 1379 uint32_t decrypt_err_drop; 1380 #ifdef GLOBAL_ASSERT_AVOIDANCE 1381 /* rx_desc NULL war count*/ 1382 uint32_t rx_desc_null; 1383 /* wbm err invalid release buffer type */ 1384 uint32_t wbm_err_buf_rel_type; 1385 /* Reo entry rx desc null */ 1386 uint32_t reo_err_rx_desc_null; 1387 /* Invalid chip id received in intrabss path */ 1388 uint64_t intra_bss_bad_chipid; 1389 #endif 1390 } err; 1391 1392 /* packet count per core - per ring */ 1393 uint64_t ring_packets[NR_CPUS][MAX_REO_DEST_RINGS]; 1394 } rx; 1395 1396 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 1397 struct reo_cmd_event_history cmd_event_history; 1398 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 1399 }; 1400 1401 union dp_align_mac_addr { 1402 uint8_t raw[QDF_MAC_ADDR_SIZE]; 1403 struct { 1404 uint16_t bytes_ab; 1405 uint16_t bytes_cd; 1406 uint16_t bytes_ef; 1407 } align2; 1408 struct { 1409 uint32_t bytes_abcd; 1410 uint16_t bytes_ef; 1411 } align4; 1412 struct __attribute__((__packed__)) { 1413 uint16_t bytes_ab; 1414 uint32_t bytes_cdef; 1415 } align4_2; 1416 }; 1417 1418 /** 1419 * struct dp_ast_free_cb_params - HMWDS free callback cookie 1420 * @mac_addr: ast mac address 1421 * @peer_mac_addr: mac address of peer 1422 * @type: ast entry type 1423 * @vdev_id: vdev_id 1424 * @flags: ast flags 1425 */ 1426 struct dp_ast_free_cb_params { 1427 union dp_align_mac_addr mac_addr; 1428 union dp_align_mac_addr peer_mac_addr; 1429 enum cdp_txrx_ast_entry_type type; 1430 uint8_t vdev_id; 1431 uint32_t flags; 1432 }; 1433 1434 /** 1435 * struct dp_ast_entry - AST entry 1436 * 1437 * @ast_idx: Hardware AST Index 1438 * @peer_id: Next Hop peer_id (for non-WDS nodes, this will be point to 1439 * associated peer with this MAC address) 1440 * @mac_addr: MAC Address for this AST entry 1441 * @next_hop: Set to 1 if this is for a WDS node 1442 * @is_active: flag to indicate active data traffic on this node 1443 * (used for aging out/expiry) 1444 * @ase_list_elem: node in peer AST list 1445 * @is_bss: flag to indicate if entry corresponds to bss peer 1446 * @is_mapped: flag to indicate that we have mapped the AST entry 1447 * in ast_table 1448 * @pdev_id: pdev ID 1449 * @vdev_id: vdev ID 1450 * @ast_hash_value: hast value in HW 1451 * @ref_cnt: reference count 1452 * @type: flag to indicate type of the entry(static/WDS/MEC) 1453 * @delete_in_progress: Flag to indicate that delete commands send to FW 1454 * and host is waiting for response from FW 1455 * @callback: ast free/unmap callback 1456 * @cookie: argument to callback 1457 * @hash_list_elem: node in soc AST hash list (mac address used as hash) 1458 */ 1459 struct dp_ast_entry { 1460 uint16_t ast_idx; 1461 uint16_t peer_id; 1462 union dp_align_mac_addr mac_addr; 1463 bool next_hop; 1464 bool is_active; 1465 bool is_mapped; 1466 uint8_t pdev_id; 1467 uint8_t vdev_id; 1468 uint16_t ast_hash_value; 1469 qdf_atomic_t ref_cnt; 1470 enum cdp_txrx_ast_entry_type type; 1471 bool delete_in_progress; 1472 txrx_ast_free_cb callback; 1473 void *cookie; 1474 TAILQ_ENTRY(dp_ast_entry) ase_list_elem; 1475 TAILQ_ENTRY(dp_ast_entry) hash_list_elem; 1476 }; 1477 1478 /** 1479 * struct dp_mec_entry - MEC entry 1480 * 1481 * @mac_addr: MAC Address for this MEC entry 1482 * @is_active: flag to indicate active data traffic on this node 1483 * (used for aging out/expiry) 1484 * @pdev_id: pdev ID 1485 * @vdev_id: vdev ID 1486 * @hash_list_elem: node in soc MEC hash list (mac address used as hash) 1487 */ 1488 struct dp_mec_entry { 1489 union dp_align_mac_addr mac_addr; 1490 bool is_active; 1491 uint8_t pdev_id; 1492 uint8_t vdev_id; 1493 1494 TAILQ_ENTRY(dp_mec_entry) hash_list_elem; 1495 }; 1496 1497 /* SOC level htt stats */ 1498 struct htt_t2h_stats { 1499 /* lock to protect htt_stats_msg update */ 1500 qdf_spinlock_t lock; 1501 1502 /* work queue to process htt stats */ 1503 qdf_work_t work; 1504 1505 /* T2H Ext stats message queue */ 1506 qdf_nbuf_queue_t msg; 1507 1508 /* number of completed stats in htt_stats_msg */ 1509 uint32_t num_stats; 1510 }; 1511 1512 struct link_desc_bank { 1513 void *base_vaddr_unaligned; 1514 void *base_vaddr; 1515 qdf_dma_addr_t base_paddr_unaligned; 1516 qdf_dma_addr_t base_paddr; 1517 uint32_t size; 1518 }; 1519 1520 struct rx_buff_pool { 1521 qdf_nbuf_queue_head_t emerg_nbuf_q; 1522 uint32_t nbuf_fail_cnt; 1523 bool is_initialized; 1524 }; 1525 1526 struct rx_refill_buff_pool { 1527 bool is_initialized; 1528 uint16_t head; 1529 uint16_t tail; 1530 struct dp_pdev *dp_pdev; 1531 uint16_t max_bufq_len; 1532 qdf_nbuf_t buf_elem[2048]; 1533 }; 1534 1535 #ifdef DP_TX_HW_DESC_HISTORY 1536 #define DP_TX_HW_DESC_HIST_MAX 6144 1537 #define DP_TX_HW_DESC_HIST_PER_SLOT_MAX 2048 1538 #define DP_TX_HW_DESC_HIST_MAX_SLOTS 3 1539 #define DP_TX_HW_DESC_HIST_SLOT_SHIFT 11 1540 1541 struct dp_tx_hw_desc_evt { 1542 uint8_t tcl_desc[HAL_TX_DESC_LEN_BYTES]; 1543 uint8_t tcl_ring_id; 1544 uint64_t posted; 1545 uint32_t hp; 1546 uint32_t tp; 1547 }; 1548 1549 /* struct dp_tx_hw_desc_history - TX HW desc hisotry 1550 * @index: Index where the last entry is written 1551 * @entry: history entries 1552 */ 1553 struct dp_tx_hw_desc_history { 1554 qdf_atomic_t index; 1555 uint16_t num_entries_per_slot; 1556 uint16_t allocated; 1557 struct dp_tx_hw_desc_evt *entry[DP_TX_HW_DESC_HIST_MAX_SLOTS]; 1558 }; 1559 #endif 1560 1561 /** 1562 * enum dp_mon_status_process_event - Events for monitor status buffer record 1563 * @DP_MON_STATUS_BUF_REAP: Monitor status buffer is reaped from ring 1564 * @DP_MON_STATUS_BUF_ENQUEUE: Status buffer is enqueued to local queue 1565 * @DP_MON_STATUS_BUF_DEQUEUE: Status buffer is dequeued from local queue 1566 */ 1567 enum dp_mon_status_process_event { 1568 DP_MON_STATUS_BUF_REAP, 1569 DP_MON_STATUS_BUF_ENQUEUE, 1570 DP_MON_STATUS_BUF_DEQUEUE, 1571 }; 1572 1573 #ifdef WLAN_FEATURE_DP_MON_STATUS_RING_HISTORY 1574 #define DP_MON_STATUS_HIST_MAX 2048 1575 1576 /** 1577 * struct dp_mon_stat_info_record - monitor stat ring buffer info 1578 * @hbi: HW ring buffer info 1579 * @timestamp: timestamp when this entry was recorded 1580 * @event: event 1581 * @rx_desc: RX descriptor corresponding to the received buffer 1582 * @nbuf: buffer attached to rx_desc, if event is REAP, else the buffer 1583 * which was enqueued or dequeued. 1584 * @rx_desc_nbuf_data: nbuf data pointer. 1585 */ 1586 struct dp_mon_stat_info_record { 1587 struct hal_buf_info hbi; 1588 uint64_t timestamp; 1589 enum dp_mon_status_process_event event; 1590 void *rx_desc; 1591 qdf_nbuf_t nbuf; 1592 uint8_t *rx_desc_nbuf_data; 1593 }; 1594 1595 /* struct dp_rx_history - rx ring hisotry 1596 * @index: Index where the last entry is written 1597 * @entry: history entries 1598 */ 1599 struct dp_mon_status_ring_history { 1600 qdf_atomic_t index; 1601 struct dp_mon_stat_info_record entry[DP_MON_STATUS_HIST_MAX]; 1602 }; 1603 #endif 1604 1605 #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY 1606 /* 1607 * The logic for get current index of these history is dependent on this 1608 * value being power of 2. 1609 */ 1610 #define DP_RX_HIST_MAX 2048 1611 #define DP_RX_ERR_HIST_MAX 2048 1612 #define DP_RX_REINJECT_HIST_MAX 1024 1613 #define DP_RX_REFILL_HIST_MAX 2048 1614 1615 QDF_COMPILE_TIME_ASSERT(rx_history_size, 1616 (DP_RX_HIST_MAX & 1617 (DP_RX_HIST_MAX - 1)) == 0); 1618 QDF_COMPILE_TIME_ASSERT(rx_err_history_size, 1619 (DP_RX_ERR_HIST_MAX & 1620 (DP_RX_ERR_HIST_MAX - 1)) == 0); 1621 QDF_COMPILE_TIME_ASSERT(rx_reinject_history_size, 1622 (DP_RX_REINJECT_HIST_MAX & 1623 (DP_RX_REINJECT_HIST_MAX - 1)) == 0); 1624 QDF_COMPILE_TIME_ASSERT(rx_refill_history_size, 1625 (DP_RX_REFILL_HIST_MAX & 1626 (DP_RX_REFILL_HIST_MAX - 1)) == 0); 1627 1628 1629 /** 1630 * struct dp_buf_info_record - ring buffer info 1631 * @hbi: HW ring buffer info 1632 * @timestamp: timestamp when this entry was recorded 1633 */ 1634 struct dp_buf_info_record { 1635 struct hal_buf_info hbi; 1636 uint64_t timestamp; 1637 }; 1638 1639 /** 1640 * struct dp_refill_info_record - ring refill buffer info 1641 * @hp: HP value after refill 1642 * @tp: cached tail value during refill 1643 * @num_req: number of buffers requested to refill 1644 * @num_refill: number of buffers refilled to ring 1645 * @timestamp: timestamp when this entry was recorded 1646 */ 1647 struct dp_refill_info_record { 1648 uint32_t hp; 1649 uint32_t tp; 1650 uint32_t num_req; 1651 uint32_t num_refill; 1652 uint64_t timestamp; 1653 }; 1654 1655 /** 1656 * struct dp_rx_history - rx ring hisotry 1657 * @index: Index where the last entry is written 1658 * @entry: history entries 1659 */ 1660 struct dp_rx_history { 1661 qdf_atomic_t index; 1662 struct dp_buf_info_record entry[DP_RX_HIST_MAX]; 1663 }; 1664 1665 /** 1666 * struct dp_rx_err_history - rx err ring hisotry 1667 * @index: Index where the last entry is written 1668 * @entry: history entries 1669 */ 1670 struct dp_rx_err_history { 1671 qdf_atomic_t index; 1672 struct dp_buf_info_record entry[DP_RX_ERR_HIST_MAX]; 1673 }; 1674 1675 /** 1676 * struct dp_rx_reinject_history - rx reinject ring hisotry 1677 * @index: Index where the last entry is written 1678 * @entry: history entries 1679 */ 1680 struct dp_rx_reinject_history { 1681 qdf_atomic_t index; 1682 struct dp_buf_info_record entry[DP_RX_REINJECT_HIST_MAX]; 1683 }; 1684 1685 /** 1686 * struct dp_rx_refill_history - rx buf refill hisotry 1687 * @index: Index where the last entry is written 1688 * @entry: history entries 1689 */ 1690 struct dp_rx_refill_history { 1691 qdf_atomic_t index; 1692 struct dp_refill_info_record entry[DP_RX_REFILL_HIST_MAX]; 1693 }; 1694 1695 #endif 1696 1697 /** 1698 * enum dp_cfg_event_type - Datapath config events type 1699 * @DP_CFG_EVENT_VDEV_ATTACH: vdev attach 1700 * @DP_CFG_EVENT_VDEV_DETACH: vdev detach 1701 * @DP_CFG_EVENT_VDEV_UNREF_DEL: vdev memory free after last ref is released 1702 * @DP_CFG_EVENT_PEER_CREATE: peer create 1703 * @DP_CFG_EVENT_PEER_DELETE: peer delete 1704 * @DP_CFG_EVENT_PEER_UNREF_DEL: peer memory free after last ref is released 1705 * @DP_CFG_EVENT_PEER_SETUP: peer setup 1706 * @DP_CFG_EVENT_MLO_ADD_LINK: add link peer to mld peer 1707 * @DP_CFG_EVENT_MLO_DEL_LINK: delete link peer from mld peer 1708 * @DP_CFG_EVENT_MLO_SETUP: MLO peer setup 1709 * @DP_CFG_EVENT_MLO_SETUP_VDEV_UPDATE: MLD peer vdev update 1710 * @DP_CFG_EVENT_PEER_MAP: peer map 1711 * @DP_CFG_EVENT_PEER_UNMAP: peer unmap 1712 * @DP_CFG_EVENT_MLO_PEER_MAP: MLD peer map 1713 * @DP_CFG_EVENT_MLO_PEER_UNMAP: MLD peer unmap 1714 */ 1715 enum dp_cfg_event_type { 1716 DP_CFG_EVENT_VDEV_ATTACH, 1717 DP_CFG_EVENT_VDEV_DETACH, 1718 DP_CFG_EVENT_VDEV_UNREF_DEL, 1719 DP_CFG_EVENT_PEER_CREATE, 1720 DP_CFG_EVENT_PEER_DELETE, 1721 DP_CFG_EVENT_PEER_UNREF_DEL, 1722 DP_CFG_EVENT_PEER_SETUP, 1723 DP_CFG_EVENT_MLO_ADD_LINK, 1724 DP_CFG_EVENT_MLO_DEL_LINK, 1725 DP_CFG_EVENT_MLO_SETUP, 1726 DP_CFG_EVENT_MLO_SETUP_VDEV_UPDATE, 1727 DP_CFG_EVENT_PEER_MAP, 1728 DP_CFG_EVENT_PEER_UNMAP, 1729 DP_CFG_EVENT_MLO_PEER_MAP, 1730 DP_CFG_EVENT_MLO_PEER_UNMAP, 1731 }; 1732 1733 #ifdef WLAN_FEATURE_DP_CFG_EVENT_HISTORY 1734 /* Size must be in 2 power, for bitwise index rotation */ 1735 #define DP_CFG_EVT_HISTORY_SIZE 0x800 1736 #define DP_CFG_EVT_HIST_PER_SLOT_MAX 256 1737 #define DP_CFG_EVT_HIST_MAX_SLOTS 8 1738 #define DP_CFG_EVT_HIST_SLOT_SHIFT 8 1739 1740 /** 1741 * struct dp_vdev_attach_detach_desc - vdev ops descriptor 1742 * @vdev: DP vdev handle 1743 * @mac_addr: vdev mac address 1744 * @vdev_id: vdev id 1745 * @ref_count: vdev ref count 1746 */ 1747 struct dp_vdev_attach_detach_desc { 1748 struct dp_vdev *vdev; 1749 union dp_align_mac_addr mac_addr; 1750 uint8_t vdev_id; 1751 int32_t ref_count; 1752 }; 1753 1754 /** 1755 * struct dp_peer_cmn_ops_desc - peer events descriptor 1756 * @vdev_id: vdev_id of the vdev on which peer exists 1757 * @is_reuse: indicates if its a peer reuse case, during peer create 1758 * @peer: DP peer handle 1759 * @vdev: DP vdev handle on which peer exists 1760 * @mac_addr: peer mac address 1761 * @vdev_mac_addr: vdev mac address 1762 * @vdev_ref_count: vdev ref count 1763 * @peer_ref_count: peer ref count 1764 */ 1765 struct dp_peer_cmn_ops_desc { 1766 uint8_t vdev_id : 5, 1767 is_reuse : 1; 1768 struct dp_peer *peer; 1769 struct dp_vdev *vdev; 1770 union dp_align_mac_addr mac_addr; 1771 union dp_align_mac_addr vdev_mac_addr; 1772 int32_t vdev_ref_count; 1773 int32_t peer_ref_count; 1774 }; 1775 1776 /** 1777 * struct dp_mlo_add_del_link_desc - MLO add/del link event descriptor 1778 * @idx: index at which link peer got added in MLD peer's list 1779 * @num_links: num links added in the MLD peer's list 1780 * @action_result: add/del was success or not 1781 * @reserved: reserved bit 1782 * @link_peer: link peer handle 1783 * @mld_peer: MLD peer handle 1784 * @link_mac_addr: link peer mac address 1785 * @mld_mac_addr: MLD peer mac address 1786 */ 1787 struct dp_mlo_add_del_link_desc { 1788 uint8_t idx : 3, 1789 num_links : 3, 1790 action_result : 1, 1791 reserved : 1; 1792 struct dp_peer *link_peer; 1793 struct dp_peer *mld_peer; 1794 union dp_align_mac_addr link_mac_addr; 1795 union dp_align_mac_addr mld_mac_addr; 1796 }; 1797 1798 /** 1799 * struct dp_mlo_setup_vdev_update_desc - MLD peer vdev update event desc 1800 * @mld_peer: MLD peer handle 1801 * @prev_vdev: previous vdev handle 1802 * @new_vdev: new vdev handle 1803 */ 1804 struct dp_mlo_setup_vdev_update_desc { 1805 struct dp_peer *mld_peer; 1806 struct dp_vdev *prev_vdev; 1807 struct dp_vdev *new_vdev; 1808 }; 1809 1810 /** 1811 * struct dp_rx_peer_map_unmap_desc - peer map/unmap event descriptor 1812 * @peer_id: peer id 1813 * @ml_peer_id: ML peer id, if its an MLD peer 1814 * @hw_peer_id: hw peer id 1815 * @vdev_id: vdev id of the peer 1816 * @is_ml_peer: is this MLD peer 1817 * @mac_addr: mac address of the peer 1818 * @peer: peer handle 1819 */ 1820 struct dp_rx_peer_map_unmap_desc { 1821 uint16_t peer_id; 1822 uint16_t ml_peer_id; 1823 uint16_t hw_peer_id; 1824 uint8_t vdev_id; 1825 uint8_t is_ml_peer; 1826 union dp_align_mac_addr mac_addr; 1827 struct dp_peer *peer; 1828 }; 1829 1830 /** 1831 * struct dp_peer_setup_desc - peer setup event descriptor 1832 * @peer: DP peer handle 1833 * @vdev: vdev handle on which peer exists 1834 * @vdev_ref_count: vdev ref count 1835 * @mac_addr: peer mac address 1836 * @mld_mac_addr: MLD mac address 1837 * @is_first_link: is the current link the first link created 1838 * @is_primary_link: is the current link primary link 1839 * @vdev_id: vdev id of the vdev on which the current link peer exists 1840 * @reserved: reserved bit 1841 */ 1842 struct dp_peer_setup_desc { 1843 struct dp_peer *peer; 1844 struct dp_vdev *vdev; 1845 int32_t vdev_ref_count; 1846 union dp_align_mac_addr mac_addr; 1847 union dp_align_mac_addr mld_mac_addr; 1848 uint8_t is_first_link : 1, 1849 is_primary_link : 1, 1850 vdev_id : 5, 1851 reserved : 1; 1852 }; 1853 1854 /** 1855 * union dp_cfg_event_desc - DP config event descriptor 1856 * @vdev_evt: vdev events desc 1857 * @peer_cmn_evt: common peer events desc 1858 * @peer_setup_evt: peer setup event desc 1859 * @mlo_link_delink_evt: MLO link/delink event desc 1860 * @mlo_setup_vdev_update: MLD peer vdev update event desc 1861 * @peer_map_unmap_evt: peer map/unmap event desc 1862 */ 1863 union dp_cfg_event_desc { 1864 struct dp_vdev_attach_detach_desc vdev_evt; 1865 struct dp_peer_cmn_ops_desc peer_cmn_evt; 1866 struct dp_peer_setup_desc peer_setup_evt; 1867 struct dp_mlo_add_del_link_desc mlo_link_delink_evt; 1868 struct dp_mlo_setup_vdev_update_desc mlo_setup_vdev_update; 1869 struct dp_rx_peer_map_unmap_desc peer_map_unmap_evt; 1870 }; 1871 1872 /** 1873 * struct dp_cfg_event - DP config event descriptor 1874 * @timestamp: timestamp at which event was recorded 1875 * @type: event type 1876 * @event_desc: event descriptor 1877 */ 1878 struct dp_cfg_event { 1879 uint64_t timestamp; 1880 enum dp_cfg_event_type type; 1881 union dp_cfg_event_desc event_desc; 1882 }; 1883 1884 /** 1885 * struct dp_cfg_event_history - DP config event history 1886 * @index: current index 1887 * @num_entries_per_slot: number of entries per slot 1888 * @allocated: Is the history allocated or not 1889 * @entry: event history descriptors 1890 */ 1891 struct dp_cfg_event_history { 1892 qdf_atomic_t index; 1893 uint16_t num_entries_per_slot; 1894 uint16_t allocated; 1895 struct dp_cfg_event *entry[DP_CFG_EVT_HIST_MAX_SLOTS]; 1896 }; 1897 #endif 1898 1899 enum dp_tx_event_type { 1900 DP_TX_DESC_INVAL_EVT = 0, 1901 DP_TX_DESC_MAP, 1902 DP_TX_DESC_COOKIE, 1903 DP_TX_DESC_FLUSH, 1904 DP_TX_DESC_UNMAP, 1905 DP_TX_COMP_UNMAP, 1906 DP_TX_COMP_UNMAP_ERR, 1907 DP_TX_COMP_MSDU_EXT, 1908 }; 1909 1910 #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY 1911 /* Size must be in 2 power, for bitwise index rotation */ 1912 #define DP_TX_TCL_HISTORY_SIZE 0x4000 1913 #define DP_TX_TCL_HIST_PER_SLOT_MAX 2048 1914 #define DP_TX_TCL_HIST_MAX_SLOTS 8 1915 #define DP_TX_TCL_HIST_SLOT_SHIFT 11 1916 1917 /* Size must be in 2 power, for bitwise index rotation */ 1918 #define DP_TX_COMP_HISTORY_SIZE 0x4000 1919 #define DP_TX_COMP_HIST_PER_SLOT_MAX 2048 1920 #define DP_TX_COMP_HIST_MAX_SLOTS 8 1921 #define DP_TX_COMP_HIST_SLOT_SHIFT 11 1922 1923 struct dp_tx_desc_event { 1924 qdf_nbuf_t skb; 1925 dma_addr_t paddr; 1926 uint32_t sw_cookie; 1927 enum dp_tx_event_type type; 1928 uint64_t ts; 1929 }; 1930 1931 struct dp_tx_tcl_history { 1932 qdf_atomic_t index; 1933 uint16_t num_entries_per_slot; 1934 uint16_t allocated; 1935 struct dp_tx_desc_event *entry[DP_TX_TCL_HIST_MAX_SLOTS]; 1936 }; 1937 1938 struct dp_tx_comp_history { 1939 qdf_atomic_t index; 1940 uint16_t num_entries_per_slot; 1941 uint16_t allocated; 1942 struct dp_tx_desc_event *entry[DP_TX_COMP_HIST_MAX_SLOTS]; 1943 }; 1944 #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */ 1945 1946 /* structure to record recent operation related variable */ 1947 struct dp_last_op_info { 1948 /* last link desc buf info through WBM release ring */ 1949 struct hal_buf_info wbm_rel_link_desc; 1950 /* last link desc buf info through REO reinject ring */ 1951 struct hal_buf_info reo_reinject_link_desc; 1952 }; 1953 1954 #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR 1955 1956 /** 1957 * struct dp_swlm_tcl_data - params for tcl register write coalescing 1958 * decision making 1959 * @nbuf: TX packet 1960 * @tid: tid for transmitting the current packet 1961 * @num_ll_connections: Number of low latency connections on this vdev 1962 * @ring_id: TCL ring id 1963 * @pkt_len: Packet length 1964 * 1965 * This structure contains the information required by the software 1966 * latency manager to decide on whether to coalesce the current TCL 1967 * register write or not. 1968 */ 1969 struct dp_swlm_tcl_data { 1970 qdf_nbuf_t nbuf; 1971 uint8_t tid; 1972 uint8_t num_ll_connections; 1973 uint8_t ring_id; 1974 uint32_t pkt_len; 1975 }; 1976 1977 /** 1978 * union swlm_data - SWLM query data 1979 * @tcl_data: data for TCL query in SWLM 1980 */ 1981 union swlm_data { 1982 struct dp_swlm_tcl_data *tcl_data; 1983 }; 1984 1985 /** 1986 * struct dp_swlm_ops - SWLM ops 1987 * @tcl_wr_coalesce_check: handler to check if the current TCL register 1988 * write can be coalesced or not 1989 */ 1990 struct dp_swlm_ops { 1991 int (*tcl_wr_coalesce_check)(struct dp_soc *soc, 1992 struct dp_swlm_tcl_data *tcl_data); 1993 }; 1994 1995 /** 1996 * struct dp_swlm_stats - Stats for Software Latency manager. 1997 * @tcl: TCL stats 1998 * @tcl.timer_flush_success: Num TCL HP writes success from timer context 1999 * @tcl.timer_flush_fail: Num TCL HP writes failure from timer context 2000 * @tcl.tid_fail: Num TCL register write coalescing skips, since the pkt 2001 * was being transmitted on a TID above coalescing threshold 2002 * @tcl.sp_frames: Num TCL register write coalescing skips, since the pkt 2003 * being transmitted was a special frame 2004 * @tcl.ll_connection: Num TCL register write coalescing skips, since the 2005 * vdev has low latency connections 2006 * @tcl.bytes_thresh_reached: Num TCL HP writes flush after the coalescing 2007 * bytes threshold was reached 2008 * @tcl.time_thresh_reached: Num TCL HP writes flush after the coalescing 2009 * session time expired 2010 * @tcl.tput_criteria_fail: Num TCL HP writes coalescing fails, since the 2011 * throughput did not meet session threshold 2012 * @tcl.coalesce_success: Num of TCL HP writes coalesced successfully. 2013 * @tcl.coalesce_fail: Num of TCL HP writes coalesces failed 2014 */ 2015 struct dp_swlm_stats { 2016 struct { 2017 uint32_t timer_flush_success; 2018 uint32_t timer_flush_fail; 2019 uint32_t tid_fail; 2020 uint32_t sp_frames; 2021 uint32_t ll_connection; 2022 uint32_t bytes_thresh_reached; 2023 uint32_t time_thresh_reached; 2024 uint32_t tput_criteria_fail; 2025 uint32_t coalesce_success; 2026 uint32_t coalesce_fail; 2027 } tcl[MAX_TCL_DATA_RINGS]; 2028 }; 2029 2030 /** 2031 * struct dp_swlm_tcl_params: Parameters based on TCL for different modules 2032 * in the Software latency manager. 2033 * @soc: DP soc reference 2034 * @ring_id: TCL ring id 2035 * @flush_timer: Timer for flushing the coalesced TCL HP writes 2036 * @sampling_session_tx_bytes: Num bytes transmitted in the sampling time 2037 * @bytes_flush_thresh: Bytes threshold to flush the TCL HP register write 2038 * @coalesce_end_time: End timestamp for current coalescing session 2039 * @bytes_coalesced: Num bytes coalesced in the current session 2040 * @prev_tx_packets: Previous TX packets accounted 2041 * @prev_tx_bytes: Previous TX bytes accounted 2042 * @prev_rx_bytes: Previous RX bytes accounted 2043 * @expire_time: expiry time for sample 2044 * @tput_pass_cnt: threshold throughput pass counter 2045 */ 2046 struct dp_swlm_tcl_params { 2047 struct dp_soc *soc; 2048 uint32_t ring_id; 2049 qdf_timer_t flush_timer; 2050 uint32_t sampling_session_tx_bytes; 2051 uint32_t bytes_flush_thresh; 2052 uint64_t coalesce_end_time; 2053 uint32_t bytes_coalesced; 2054 uint32_t prev_tx_packets; 2055 uint32_t prev_tx_bytes; 2056 uint32_t prev_rx_bytes; 2057 uint64_t expire_time; 2058 uint32_t tput_pass_cnt; 2059 }; 2060 2061 /** 2062 * struct dp_swlm_params: Parameters for different modules in the 2063 * Software latency manager. 2064 * @rx_traffic_thresh: Threshold for RX traffic, to begin TCL register 2065 * write coalescing 2066 * @tx_traffic_thresh: Threshold for TX traffic, to begin TCL register 2067 * write coalescing 2068 * @sampling_time: Sampling time to test the throughput threshold 2069 * @time_flush_thresh: Time threshold to flush the TCL HP register write 2070 * @tx_thresh_multiplier: Multiplier to deduce the bytes threshold after 2071 * which the TCL HP register is written, thereby 2072 * ending the coalescing. 2073 * @tx_pkt_thresh: Threshold for TX packet count, to begin TCL register 2074 * write coalescing 2075 * @tcl: TCL ring specific params 2076 */ 2077 2078 struct dp_swlm_params { 2079 uint32_t rx_traffic_thresh; 2080 uint32_t tx_traffic_thresh; 2081 uint32_t sampling_time; 2082 uint32_t time_flush_thresh; 2083 uint32_t tx_thresh_multiplier; 2084 uint32_t tx_pkt_thresh; 2085 struct dp_swlm_tcl_params tcl[MAX_TCL_DATA_RINGS]; 2086 }; 2087 2088 /** 2089 * struct dp_swlm - Software latency manager context 2090 * @ops: SWLM ops pointers 2091 * @is_enabled: SWLM enabled/disabled 2092 * @is_init: SWLM module initialized 2093 * @stats: SWLM stats 2094 * @params: SWLM SRNG params 2095 * @tcl_flush_timer: flush timer for TCL register writes 2096 */ 2097 struct dp_swlm { 2098 struct dp_swlm_ops *ops; 2099 uint8_t is_enabled:1, 2100 is_init:1; 2101 struct dp_swlm_stats stats; 2102 struct dp_swlm_params params; 2103 }; 2104 #endif 2105 2106 #ifdef IPA_OFFLOAD 2107 /* IPA uC datapath offload Wlan Tx resources */ 2108 struct ipa_dp_tx_rsc { 2109 /* Resource info to be passed to IPA */ 2110 qdf_dma_addr_t ipa_tcl_ring_base_paddr; 2111 void *ipa_tcl_ring_base_vaddr; 2112 uint32_t ipa_tcl_ring_size; 2113 qdf_dma_addr_t ipa_tcl_hp_paddr; 2114 uint32_t alloc_tx_buf_cnt; 2115 2116 qdf_dma_addr_t ipa_wbm_ring_base_paddr; 2117 void *ipa_wbm_ring_base_vaddr; 2118 uint32_t ipa_wbm_ring_size; 2119 qdf_dma_addr_t ipa_wbm_tp_paddr; 2120 /* WBM2SW HP shadow paddr */ 2121 qdf_dma_addr_t ipa_wbm_hp_shadow_paddr; 2122 2123 /* TX buffers populated into the WBM ring */ 2124 void **tx_buf_pool_vaddr_unaligned; 2125 qdf_dma_addr_t *tx_buf_pool_paddr_unaligned; 2126 }; 2127 2128 /* IPA uC datapath offload Wlan Rx resources */ 2129 struct ipa_dp_rx_rsc { 2130 /* Resource info to be passed to IPA */ 2131 qdf_dma_addr_t ipa_reo_ring_base_paddr; 2132 void *ipa_reo_ring_base_vaddr; 2133 uint32_t ipa_reo_ring_size; 2134 qdf_dma_addr_t ipa_reo_tp_paddr; 2135 2136 /* Resource info to be passed to firmware and IPA */ 2137 qdf_dma_addr_t ipa_rx_refill_buf_ring_base_paddr; 2138 void *ipa_rx_refill_buf_ring_base_vaddr; 2139 uint32_t ipa_rx_refill_buf_ring_size; 2140 qdf_dma_addr_t ipa_rx_refill_buf_hp_paddr; 2141 }; 2142 #endif 2143 2144 struct dp_tx_msdu_info_s; 2145 /** 2146 * enum dp_context_type- DP Context Type 2147 * @DP_CONTEXT_TYPE_SOC: Context type DP SOC 2148 * @DP_CONTEXT_TYPE_PDEV: Context type DP PDEV 2149 * @DP_CONTEXT_TYPE_VDEV: Context type DP VDEV 2150 * @DP_CONTEXT_TYPE_PEER: Context type DP PEER 2151 * @DP_CONTEXT_TYPE_MON_SOC: Context type DP MON SOC 2152 * @DP_CONTEXT_TYPE_MON_PDEV: Context type DP MON PDEV 2153 * 2154 * Helper enums to be used to retrieve the size of the corresponding 2155 * data structure by passing the type. 2156 */ 2157 enum dp_context_type { 2158 DP_CONTEXT_TYPE_SOC, 2159 DP_CONTEXT_TYPE_PDEV, 2160 DP_CONTEXT_TYPE_VDEV, 2161 DP_CONTEXT_TYPE_PEER, 2162 DP_CONTEXT_TYPE_MON_SOC, 2163 DP_CONTEXT_TYPE_MON_PDEV 2164 }; 2165 2166 /** 2167 * struct dp_arch_ops - DP target specific arch ops 2168 * @txrx_soc_attach: 2169 * @txrx_soc_detach: 2170 * @txrx_soc_init: 2171 * @txrx_soc_deinit: 2172 * @txrx_soc_srng_alloc: 2173 * @txrx_soc_srng_init: 2174 * @txrx_soc_srng_deinit: 2175 * @txrx_soc_srng_free: 2176 * @txrx_pdev_attach: 2177 * @txrx_pdev_detach: 2178 * @txrx_vdev_attach: 2179 * @txrx_vdev_detach: 2180 * @txrx_peer_map_attach: 2181 * @txrx_peer_map_detach: 2182 * @dp_rxdma_ring_sel_cfg: 2183 * @soc_cfg_attach: 2184 * @txrx_peer_setup: 2185 * @peer_get_reo_hash: 2186 * @reo_remap_config: 2187 * @tx_hw_enqueue: enqueue TX data to HW 2188 * @tx_comp_get_params_from_hal_desc: get software tx descriptor and release 2189 * source from HAL desc for wbm release ring 2190 * @dp_tx_mlo_mcast_send: Tx send handler for MLO multicast enhance 2191 * @dp_tx_process_htt_completion: 2192 * @dp_rx_process: 2193 * @dp_tx_send_fast: 2194 * @dp_tx_desc_pool_init: 2195 * @dp_tx_desc_pool_deinit: 2196 * @dp_rx_desc_pool_init: 2197 * @dp_rx_desc_pool_deinit: 2198 * @dp_wbm_get_rx_desc_from_hal_desc: 2199 * @dp_rx_intrabss_mcast_handler: 2200 * @dp_rx_word_mask_subscribe: 2201 * @dp_rx_desc_cookie_2_va: 2202 * @dp_service_near_full_srngs: Handler for servicing the near full IRQ 2203 * @tx_implicit_rbm_set: 2204 * @dp_rx_peer_metadata_peer_id_get: 2205 * @dp_rx_chain_msdus: 2206 * @txrx_set_vdev_param: target specific ops while setting vdev params 2207 * @txrx_get_vdev_mcast_param: target specific ops for getting vdev 2208 * params related to multicast 2209 * @txrx_get_context_size: 2210 * @txrx_get_mon_context_size: 2211 * @dp_srng_test_and_update_nf_params: Check if the srng is in near full state 2212 * and set the near-full params. 2213 * @dp_tx_mcast_handler: 2214 * @dp_rx_mcast_handler: 2215 * @dp_tx_is_mcast_primary: 2216 * @dp_soc_get_by_idle_bm_id: 2217 * @mlo_peer_find_hash_detach: 2218 * @mlo_peer_find_hash_attach: 2219 * @mlo_peer_find_hash_add: 2220 * @mlo_peer_find_hash_remove: 2221 * @mlo_peer_find_hash_find: 2222 * @mlo_get_chip_id: get the MLO chip id 2223 * @mlo_link_peer_find_hash_find_by_chip_id: return the link peer on the chip 2224 * @get_hw_link_id: 2225 * @dp_rx_peer_set_link_id: set link id in nbuf cb 2226 * @get_reo_qdesc_addr: 2227 * @get_rx_hash_key: 2228 * @dp_set_rx_fst: 2229 * @dp_get_rx_fst: 2230 * @dp_rx_fst_deref: 2231 * @dp_rx_fst_ref: 2232 * @txrx_print_peer_stats: 2233 * @dp_peer_rx_reorder_queue_setup: Dp peer reorder queue setup 2234 * @dp_bank_reconfig: 2235 * @dp_get_soc_by_chip_id: Get soc by chip id 2236 * @dp_soc_get_num_soc: 2237 * @dp_reconfig_tx_vdev_mcast_ctrl: 2238 * @dp_cc_reg_cfg_init: 2239 * @dp_tx_compute_hw_delay: 2240 * @print_mlo_ast_stats: 2241 * @dp_partner_chips_map: 2242 * @dp_partner_chips_unmap: 2243 * @ipa_get_bank_id: Get TCL bank id used by IPA 2244 * @ipa_get_wdi_ver: Get WDI version 2245 * @dp_txrx_ppeds_rings_status: 2246 * @dp_tx_ppeds_inuse_desc: 2247 * @dp_ppeds_clear_stats: Clear ppeds related stats 2248 * @dp_tx_ppeds_cfg_astidx_cache_mapping: 2249 * @dp_txrx_ppeds_rings_stats: Printing the util stats of ring 2250 * @dp_txrx_ppeds_clear_rings_stats: Clearing the ring util stats 2251 * @txrx_soc_ppeds_start: 2252 * @txrx_soc_ppeds_stop: 2253 * @dp_register_ppeds_interrupts: 2254 * @dp_free_ppeds_interrupts: 2255 * @dp_rx_wbm_err_reap_desc: Reap WBM Error Ring Descriptor 2256 * @dp_rx_null_q_desc_handle: Handle Null Queue Exception Error 2257 * @dp_tx_desc_pool_alloc: Allocate arch specific TX descriptor pool 2258 * @dp_tx_desc_pool_free: Free arch specific TX descriptor pool 2259 * @txrx_srng_init: Init txrx srng 2260 * @dp_get_vdev_stats_for_unmap_peer: Get vdev stats pointer for unmap peer 2261 * @dp_get_interface_stats: Get interface stats 2262 * @ppeds_handle_attached: 2263 * @txrx_soc_ppeds_interrupt_stop: 2264 * @txrx_soc_ppeds_interrupt_start: 2265 * @txrx_soc_ppeds_service_status_update: 2266 * @txrx_soc_ppeds_enabled_check: 2267 * @txrx_soc_ppeds_txdesc_pool_reset: 2268 * @dp_update_ring_hptp: Update rings hptp during suspend/resume 2269 * @dp_get_fst_cmem_base: Get CMEM base address for FISA 2270 * @dp_flush_tx_ring: Flush TCL ring HP 2271 * @dp_mlo_print_ptnr_info: print partner vdev info 2272 * @dp_soc_interrupt_attach: DP interrupt attach 2273 * @dp_soc_attach_poll: DP poll attach 2274 * @dp_soc_interrupt_detach: DP interrupt detach 2275 * @dp_service_srngs: Service DP interrupts 2276 */ 2277 struct dp_arch_ops { 2278 /* INIT/DEINIT Arch Ops */ 2279 QDF_STATUS (*txrx_soc_attach)(struct dp_soc *soc, 2280 struct cdp_soc_attach_params *params); 2281 QDF_STATUS (*txrx_soc_detach)(struct dp_soc *soc); 2282 void* (*txrx_soc_init)(struct dp_soc *soc, HTC_HANDLE htc_handle, 2283 struct hif_opaque_softc *hif_handle); 2284 QDF_STATUS (*txrx_soc_deinit)(struct dp_soc *soc); 2285 QDF_STATUS (*txrx_soc_srng_alloc)(struct dp_soc *soc); 2286 QDF_STATUS (*txrx_soc_srng_init)(struct dp_soc *soc); 2287 void (*txrx_soc_srng_deinit)(struct dp_soc *soc); 2288 void (*txrx_soc_srng_free)(struct dp_soc *soc); 2289 QDF_STATUS (*txrx_pdev_attach)(struct dp_pdev *pdev, 2290 struct cdp_pdev_attach_params *params); 2291 QDF_STATUS (*txrx_pdev_detach)(struct dp_pdev *pdev); 2292 QDF_STATUS (*txrx_vdev_attach)(struct dp_soc *soc, 2293 struct dp_vdev *vdev); 2294 QDF_STATUS (*txrx_vdev_detach)(struct dp_soc *soc, 2295 struct dp_vdev *vdev); 2296 QDF_STATUS (*txrx_peer_map_attach)(struct dp_soc *soc); 2297 void (*txrx_peer_map_detach)(struct dp_soc *soc); 2298 QDF_STATUS (*dp_rxdma_ring_sel_cfg)(struct dp_soc *soc); 2299 void (*soc_cfg_attach)(struct dp_soc *soc); 2300 QDF_STATUS (*txrx_peer_setup)(struct cdp_soc_t *soc_hdl, 2301 uint8_t vdev_id, uint8_t *peer_mac, 2302 struct cdp_peer_setup_info *setup_info); 2303 void (*peer_get_reo_hash)(struct dp_vdev *vdev, 2304 struct cdp_peer_setup_info *setup_info, 2305 enum cdp_host_reo_dest_ring *reo_dest, 2306 bool *hash_based, 2307 uint8_t *lmac_peer_id_msb); 2308 bool (*reo_remap_config)(struct dp_soc *soc, uint32_t *remap0, 2309 uint32_t *remap1, uint32_t *remap2); 2310 2311 /* TX RX Arch Ops */ 2312 QDF_STATUS (*tx_hw_enqueue)(struct dp_soc *soc, struct dp_vdev *vdev, 2313 struct dp_tx_desc_s *tx_desc, 2314 uint16_t fw_metadata, 2315 struct cdp_tx_exception_metadata *metadata, 2316 struct dp_tx_msdu_info_s *msdu_info); 2317 2318 void (*tx_comp_get_params_from_hal_desc)(struct dp_soc *soc, 2319 void *tx_comp_hal_desc, 2320 struct dp_tx_desc_s **desc); 2321 2322 qdf_nbuf_t (*dp_tx_mlo_mcast_send)(struct dp_soc *soc, 2323 struct dp_vdev *vdev, 2324 qdf_nbuf_t nbuf, 2325 struct cdp_tx_exception_metadata 2326 *tx_exc_metadata); 2327 2328 void (*dp_tx_process_htt_completion)(struct dp_soc *soc, 2329 struct dp_tx_desc_s *tx_desc, 2330 uint8_t *status, 2331 uint8_t ring_id); 2332 2333 uint32_t (*dp_rx_process)(struct dp_intr *int_ctx, 2334 hal_ring_handle_t hal_ring_hdl, 2335 uint8_t reo_ring_num, uint32_t quota); 2336 2337 qdf_nbuf_t (*dp_tx_send_fast)(struct cdp_soc_t *soc_hdl, 2338 uint8_t vdev_id, 2339 qdf_nbuf_t nbuf); 2340 2341 QDF_STATUS (*dp_tx_desc_pool_init)(struct dp_soc *soc, 2342 uint32_t num_elem, 2343 uint8_t pool_id, 2344 bool spcl_tx_desc); 2345 void (*dp_tx_desc_pool_deinit)( 2346 struct dp_soc *soc, 2347 struct dp_tx_desc_pool_s *tx_desc_pool, 2348 uint8_t pool_id, 2349 bool spcl_tx_desc); 2350 2351 QDF_STATUS (*dp_rx_desc_pool_init)(struct dp_soc *soc, 2352 struct rx_desc_pool *rx_desc_pool, 2353 uint32_t pool_id); 2354 void (*dp_rx_desc_pool_deinit)(struct dp_soc *soc, 2355 struct rx_desc_pool *rx_desc_pool, 2356 uint32_t pool_id); 2357 2358 QDF_STATUS (*dp_wbm_get_rx_desc_from_hal_desc)( 2359 struct dp_soc *soc, 2360 void *ring_desc, 2361 struct dp_rx_desc **r_rx_desc); 2362 2363 bool 2364 (*dp_rx_intrabss_mcast_handler)(struct dp_soc *soc, 2365 struct dp_txrx_peer *ta_txrx_peer, 2366 qdf_nbuf_t nbuf_copy, 2367 struct cdp_tid_rx_stats *tid_stats, 2368 uint8_t link_id); 2369 2370 void (*dp_rx_word_mask_subscribe)( 2371 struct dp_soc *soc, 2372 uint32_t *msg_word, 2373 void *rx_filter); 2374 2375 struct dp_rx_desc *(*dp_rx_desc_cookie_2_va)(struct dp_soc *soc, 2376 uint32_t cookie); 2377 uint32_t (*dp_service_near_full_srngs)(struct dp_soc *soc, 2378 struct dp_intr *int_ctx, 2379 uint32_t dp_budget); 2380 void (*tx_implicit_rbm_set)(struct dp_soc *soc, uint8_t tx_ring_id, 2381 uint8_t bm_id); 2382 uint16_t (*dp_rx_peer_metadata_peer_id_get)(struct dp_soc *soc, 2383 uint32_t peer_metadata); 2384 bool (*dp_rx_chain_msdus)(struct dp_soc *soc, qdf_nbuf_t nbuf, 2385 uint8_t *rx_tlv_hdr, uint8_t mac_id); 2386 /* Control Arch Ops */ 2387 QDF_STATUS (*txrx_set_vdev_param)(struct dp_soc *soc, 2388 struct dp_vdev *vdev, 2389 enum cdp_vdev_param_type param, 2390 cdp_config_param_type val); 2391 2392 QDF_STATUS (*txrx_get_vdev_mcast_param)(struct dp_soc *soc, 2393 struct dp_vdev *vdev, 2394 cdp_config_param_type *val); 2395 2396 /* Misc Arch Ops */ 2397 qdf_size_t (*txrx_get_context_size)(enum dp_context_type); 2398 #ifdef WIFI_MONITOR_SUPPORT 2399 qdf_size_t (*txrx_get_mon_context_size)(enum dp_context_type); 2400 #endif 2401 int (*dp_srng_test_and_update_nf_params)(struct dp_soc *soc, 2402 struct dp_srng *dp_srng, 2403 int *max_reap_limit); 2404 2405 /* MLO ops */ 2406 #ifdef WLAN_FEATURE_11BE_MLO 2407 #ifdef WLAN_MCAST_MLO 2408 void (*dp_tx_mcast_handler)(struct dp_soc *soc, struct dp_vdev *vdev, 2409 qdf_nbuf_t nbuf); 2410 bool (*dp_rx_mcast_handler)(struct dp_soc *soc, struct dp_vdev *vdev, 2411 struct dp_txrx_peer *peer, qdf_nbuf_t nbuf, 2412 uint8_t link_id); 2413 bool (*dp_tx_is_mcast_primary)(struct dp_soc *soc, 2414 struct dp_vdev *vdev); 2415 #endif 2416 struct dp_soc * (*dp_soc_get_by_idle_bm_id)(struct dp_soc *soc, 2417 uint8_t bm_id); 2418 2419 void (*mlo_peer_find_hash_detach)(struct dp_soc *soc); 2420 QDF_STATUS (*mlo_peer_find_hash_attach)(struct dp_soc *soc); 2421 void (*mlo_peer_find_hash_add)(struct dp_soc *soc, 2422 struct dp_peer *peer); 2423 void (*mlo_peer_find_hash_remove)(struct dp_soc *soc, 2424 struct dp_peer *peer); 2425 2426 struct dp_peer *(*mlo_peer_find_hash_find)(struct dp_soc *soc, 2427 uint8_t *peer_mac_addr, 2428 int mac_addr_is_aligned, 2429 enum dp_mod_id mod_id, 2430 uint8_t vdev_id); 2431 #ifdef WLAN_MLO_MULTI_CHIP 2432 uint8_t (*mlo_get_chip_id)(struct dp_soc *soc); 2433 struct dp_peer *(*mlo_link_peer_find_hash_find_by_chip_id) 2434 (struct dp_soc *soc, 2435 uint8_t *peer_mac_addr, 2436 int mac_addr_is_aligned, 2437 uint8_t vdev_id, 2438 uint8_t chip_id, 2439 enum dp_mod_id mod_id); 2440 #endif 2441 #endif 2442 uint8_t (*get_hw_link_id)(struct dp_pdev *pdev); 2443 void (*dp_rx_peer_set_link_id)(qdf_nbuf_t nbuf, uint32_t peer_mdata); 2444 uint64_t (*get_reo_qdesc_addr)(hal_soc_handle_t hal_soc_hdl, 2445 uint8_t *dst_ring_desc, 2446 uint8_t *buf, 2447 struct dp_txrx_peer *peer, 2448 unsigned int tid); 2449 void (*get_rx_hash_key)(struct dp_soc *soc, 2450 struct cdp_lro_hash_config *lro_hash); 2451 void (*dp_set_rx_fst)(struct dp_rx_fst *fst); 2452 struct dp_rx_fst *(*dp_get_rx_fst)(void); 2453 uint32_t (*dp_rx_fst_deref)(void); 2454 void (*dp_rx_fst_ref)(void); 2455 void (*txrx_print_peer_stats)(struct cdp_peer_stats *peer_stats, 2456 enum peer_stats_type stats_type); 2457 QDF_STATUS (*dp_peer_rx_reorder_queue_setup)(struct dp_soc *soc, 2458 struct dp_peer *peer, 2459 int tid, 2460 uint32_t ba_window_size); 2461 void (*dp_bank_reconfig)(struct dp_soc *soc, struct dp_vdev *vdev); 2462 2463 struct dp_soc * (*dp_get_soc_by_chip_id)(struct dp_soc *soc, 2464 uint8_t chip_id); 2465 2466 uint8_t (*dp_soc_get_num_soc)(struct dp_soc *soc); 2467 void (*dp_reconfig_tx_vdev_mcast_ctrl)(struct dp_soc *soc, 2468 struct dp_vdev *vdev); 2469 2470 void (*dp_cc_reg_cfg_init)(struct dp_soc *soc, bool is_4k_align); 2471 2472 QDF_STATUS 2473 (*dp_tx_compute_hw_delay)(struct dp_soc *soc, 2474 struct dp_vdev *vdev, 2475 struct hal_tx_completion_status *ts, 2476 uint32_t *delay_us); 2477 void (*print_mlo_ast_stats)(struct dp_soc *soc); 2478 void (*dp_partner_chips_map)(struct dp_soc *soc, 2479 struct dp_peer *peer, 2480 uint16_t peer_id); 2481 void (*dp_partner_chips_unmap)(struct dp_soc *soc, 2482 uint16_t peer_id); 2483 2484 #ifdef IPA_OFFLOAD 2485 int8_t (*ipa_get_bank_id)(struct dp_soc *soc); 2486 void (*ipa_get_wdi_ver)(uint8_t *wdi_ver); 2487 #endif 2488 #ifdef WLAN_SUPPORT_PPEDS 2489 void (*dp_txrx_ppeds_rings_status)(struct dp_soc *soc); 2490 void (*dp_tx_ppeds_inuse_desc)(struct dp_soc *soc); 2491 void (*dp_ppeds_clear_stats)(struct dp_soc *soc); 2492 void (*dp_tx_ppeds_cfg_astidx_cache_mapping)(struct dp_soc *soc, 2493 struct dp_vdev *vdev, 2494 bool peer_map); 2495 void (*dp_txrx_ppeds_rings_stats)(struct dp_soc *soc); 2496 void (*dp_txrx_ppeds_clear_rings_stats)(struct dp_soc *soc); 2497 #endif 2498 bool (*ppeds_handle_attached)(struct dp_soc *soc); 2499 QDF_STATUS (*txrx_soc_ppeds_start)(struct dp_soc *soc); 2500 void (*txrx_soc_ppeds_stop)(struct dp_soc *soc); 2501 int (*dp_register_ppeds_interrupts)(struct dp_soc *soc, 2502 struct dp_srng *srng, int vector, 2503 int ring_type, int ring_num); 2504 void (*dp_free_ppeds_interrupts)(struct dp_soc *soc, 2505 struct dp_srng *srng, int ring_type, 2506 int ring_num); 2507 qdf_nbuf_t (*dp_rx_wbm_err_reap_desc)(struct dp_intr *int_ctx, 2508 struct dp_soc *soc, 2509 hal_ring_handle_t hal_ring_hdl, 2510 uint32_t quota, 2511 uint32_t *rx_bufs_used); 2512 QDF_STATUS (*dp_rx_null_q_desc_handle)(struct dp_soc *soc, 2513 qdf_nbuf_t nbuf, 2514 uint8_t *rx_tlv_hdr, 2515 uint8_t pool_id, 2516 struct dp_txrx_peer *txrx_peer, 2517 bool is_reo_exception, 2518 uint8_t link_id); 2519 2520 QDF_STATUS (*dp_tx_desc_pool_alloc)(struct dp_soc *soc, 2521 uint32_t num_elem, 2522 uint8_t pool_id); 2523 void (*dp_tx_desc_pool_free)(struct dp_soc *soc, uint8_t pool_id); 2524 2525 QDF_STATUS (*txrx_srng_init)(struct dp_soc *soc, struct dp_srng *srng, 2526 int ring_type, int ring_num, int mac_id); 2527 2528 void (*dp_get_vdev_stats_for_unmap_peer)( 2529 struct dp_vdev *vdev, 2530 struct dp_peer *peer, 2531 struct cdp_vdev_stats **vdev_stats); 2532 QDF_STATUS (*dp_get_interface_stats)(struct cdp_soc_t *soc_hdl, 2533 uint8_t vdev_id, 2534 void *buf, 2535 bool is_aggregate); 2536 #ifdef WLAN_SUPPORT_PPEDS 2537 void (*txrx_soc_ppeds_interrupt_stop)(struct dp_soc *soc); 2538 void (*txrx_soc_ppeds_interrupt_start)(struct dp_soc *soc); 2539 void (*txrx_soc_ppeds_service_status_update)(struct dp_soc *soc, 2540 bool enable); 2541 bool (*txrx_soc_ppeds_enabled_check)(struct dp_soc *soc); 2542 void (*txrx_soc_ppeds_txdesc_pool_reset)(struct dp_soc *soc, 2543 qdf_nbuf_t *nbuf_list); 2544 #endif 2545 void (*dp_update_ring_hptp)(struct dp_soc *soc, bool force_flush_tx); 2546 uint64_t (*dp_get_fst_cmem_base)(struct dp_soc *soc, uint64_t size); 2547 int (*dp_flush_tx_ring)(struct dp_pdev *pdev, int ring_id); 2548 void (*dp_mlo_print_ptnr_info)(struct dp_vdev *vdev); 2549 QDF_STATUS (*dp_soc_interrupt_attach)(struct cdp_soc_t *txrx_soc); 2550 QDF_STATUS (*dp_soc_attach_poll)(struct cdp_soc_t *txrx_soc); 2551 void (*dp_soc_interrupt_detach)(struct cdp_soc_t *txrx_soc); 2552 uint32_t (*dp_service_srngs)(void *dp_ctx, uint32_t dp_budget, int cpu); 2553 }; 2554 2555 /** 2556 * struct dp_soc_features: Data structure holding the SOC level feature flags. 2557 * @pn_in_reo_dest: PN provided by hardware in the REO destination ring. 2558 * @dmac_cmn_src_rxbuf_ring_enabled: Flag to indicate DMAC mode common Rx 2559 * buffer source rings 2560 * @rssi_dbm_conv_support: Rssi dbm conversion support param. 2561 * @umac_hw_reset_support: UMAC HW reset support 2562 * @wds_ext_ast_override_enable: 2563 */ 2564 struct dp_soc_features { 2565 uint8_t pn_in_reo_dest:1, 2566 dmac_cmn_src_rxbuf_ring_enabled:1; 2567 bool rssi_dbm_conv_support; 2568 bool umac_hw_reset_support; 2569 bool wds_ext_ast_override_enable; 2570 }; 2571 2572 enum sysfs_printing_mode { 2573 PRINTING_MODE_DISABLED = 0, 2574 PRINTING_MODE_ENABLED 2575 }; 2576 2577 /** 2578 * typedef notify_pre_reset_fw_callback() - pre-reset callback 2579 * @soc: DP SoC 2580 */ 2581 typedef void (*notify_pre_reset_fw_callback)(struct dp_soc *soc); 2582 2583 #ifdef WLAN_SYSFS_DP_STATS 2584 /** 2585 * struct sysfs_stats_config: Data structure holding stats sysfs config. 2586 * @rw_stats_lock: Lock to read and write to stat_type and pdev_id. 2587 * @sysfs_read_lock: Lock held while another stat req is being executed. 2588 * @sysfs_write_user_buffer: Lock to change buff len, max buf len 2589 * and *buf. 2590 * @sysfs_txrx_fw_request_done: Event to wait for firmware response. 2591 * @stat_type_requested: stat type requested. 2592 * @mac_id: mac id for which stat type are requested. 2593 * @printing_mode: Should a print go through. 2594 * @process_id: Process allowed to write to buffer. 2595 * @curr_buffer_length: Curr length of buffer written 2596 * @max_buffer_length: Max buffer length. 2597 * @buf: Sysfs buffer. 2598 */ 2599 struct sysfs_stats_config { 2600 /* lock held to read stats */ 2601 qdf_spinlock_t rw_stats_lock; 2602 qdf_mutex_t sysfs_read_lock; 2603 qdf_spinlock_t sysfs_write_user_buffer; 2604 qdf_event_t sysfs_txrx_fw_request_done; 2605 uint32_t stat_type_requested; 2606 uint32_t mac_id; 2607 enum sysfs_printing_mode printing_mode; 2608 int process_id; 2609 uint16_t curr_buffer_length; 2610 uint16_t max_buffer_length; 2611 char *buf; 2612 }; 2613 #endif 2614 2615 struct test_mem_free { 2616 unsigned long ts_qdesc_mem_hdl; 2617 qdf_dma_addr_t hw_qdesc_paddr; 2618 void *hw_qdesc_vaddr_align; 2619 void *hw_qdesc_vaddr_unalign; 2620 uint32_t peer_id; 2621 uint32_t tid; 2622 uint8_t chip_id; 2623 unsigned long ts_hw_flush_back; 2624 }; 2625 2626 struct test_qaddr_del { 2627 unsigned long ts_qaddr_del; 2628 uint32_t peer_id; 2629 uint32_t paddr; 2630 uint32_t tid; 2631 uint8_t chip_id; 2632 }; 2633 2634 /* SOC level structure for data path */ 2635 struct dp_soc { 2636 /** 2637 * re-use memory section starts 2638 */ 2639 2640 /* Common base structure - Should be the first member */ 2641 struct cdp_soc_t cdp_soc; 2642 2643 /* SoC Obj */ 2644 struct cdp_ctrl_objmgr_psoc *ctrl_psoc; 2645 2646 /* OS device abstraction */ 2647 qdf_device_t osdev; 2648 2649 /*cce disable*/ 2650 bool cce_disable; 2651 2652 /* WLAN config context */ 2653 struct wlan_cfg_dp_soc_ctxt *wlan_cfg_ctx; 2654 2655 /* HTT handle for host-fw interaction */ 2656 struct htt_soc *htt_handle; 2657 2658 /* Commint init done */ 2659 qdf_atomic_t cmn_init_done; 2660 2661 /* Opaque hif handle */ 2662 struct hif_opaque_softc *hif_handle; 2663 2664 /* PDEVs on this SOC */ 2665 struct dp_pdev *pdev_list[MAX_PDEV_CNT]; 2666 2667 /* Ring used to replenish rx buffers (maybe to the firmware of MAC) */ 2668 struct dp_srng rx_refill_buf_ring[MAX_PDEV_CNT]; 2669 2670 struct dp_srng rxdma_mon_desc_ring[MAX_NUM_LMAC_HW]; 2671 2672 /* RXDMA error destination ring */ 2673 struct dp_srng rxdma_err_dst_ring[MAX_NUM_LMAC_HW]; 2674 2675 /* RXDMA monitor buffer replenish ring */ 2676 struct dp_srng rxdma_mon_buf_ring[MAX_NUM_LMAC_HW]; 2677 2678 /* RXDMA monitor destination ring */ 2679 struct dp_srng rxdma_mon_dst_ring[MAX_NUM_LMAC_HW]; 2680 2681 /* RXDMA monitor status ring. TBD: Check format of this ring */ 2682 struct dp_srng rxdma_mon_status_ring[MAX_NUM_LMAC_HW]; 2683 2684 /* Ring to handover links to hw in monitor mode for SOFTUMAC arch */ 2685 struct dp_srng sw2rxdma_link_ring[MAX_NUM_LMAC_HW]; 2686 2687 /* Number of PDEVs */ 2688 uint8_t pdev_count; 2689 2690 /*ast override support in HW*/ 2691 bool ast_override_support; 2692 2693 /*number of hw dscp tid map*/ 2694 uint8_t num_hw_dscp_tid_map; 2695 2696 /* HAL SOC handle */ 2697 hal_soc_handle_t hal_soc; 2698 2699 /* rx monitor pkt tlv size */ 2700 uint16_t rx_mon_pkt_tlv_size; 2701 /* rx pkt tlv size */ 2702 uint16_t rx_pkt_tlv_size; 2703 /* rx pkt tlv size in current operation mode */ 2704 uint16_t curr_rx_pkt_tlv_size; 2705 2706 struct dp_arch_ops arch_ops; 2707 2708 /* Device ID coming from Bus sub-system */ 2709 uint32_t device_id; 2710 2711 /* Link descriptor pages */ 2712 struct qdf_mem_multi_page_t link_desc_pages; 2713 2714 /* total link descriptors for regular RX and TX */ 2715 uint32_t total_link_descs; 2716 2717 /* Link descriptor Idle list for HW internal use (SRNG mode) */ 2718 struct dp_srng wbm_idle_link_ring; 2719 2720 /* Link descriptor Idle list for HW internal use (scatter buffer mode) 2721 */ 2722 qdf_dma_addr_t wbm_idle_scatter_buf_base_paddr[MAX_IDLE_SCATTER_BUFS]; 2723 void *wbm_idle_scatter_buf_base_vaddr[MAX_IDLE_SCATTER_BUFS]; 2724 uint32_t num_scatter_bufs; 2725 2726 /* Tx SW descriptor pool */ 2727 struct dp_tx_desc_pool_s tx_desc[MAX_TXDESC_POOLS]; 2728 2729 /* Tx MSDU Extension descriptor pool */ 2730 struct dp_tx_ext_desc_pool_s tx_ext_desc[MAX_TXDESC_POOLS]; 2731 2732 /* Tx TSO descriptor pool */ 2733 struct dp_tx_tso_seg_pool_s tx_tso_desc[MAX_TXDESC_POOLS]; 2734 2735 /* Tx TSO Num of segments pool */ 2736 struct dp_tx_tso_num_seg_pool_s tx_tso_num_seg[MAX_TXDESC_POOLS]; 2737 2738 /* REO destination rings */ 2739 struct dp_srng reo_dest_ring[MAX_REO_DEST_RINGS]; 2740 2741 /* REO exception ring - See if should combine this with reo_dest_ring */ 2742 struct dp_srng reo_exception_ring; 2743 2744 /* REO reinjection ring */ 2745 struct dp_srng reo_reinject_ring; 2746 2747 /* REO command ring */ 2748 struct dp_srng reo_cmd_ring; 2749 2750 /* REO command status ring */ 2751 struct dp_srng reo_status_ring; 2752 2753 /* WBM Rx release ring */ 2754 struct dp_srng rx_rel_ring; 2755 2756 /* TCL data ring */ 2757 struct dp_srng tcl_data_ring[MAX_TCL_DATA_RINGS]; 2758 2759 /* Number of Tx comp rings */ 2760 uint8_t num_tx_comp_rings; 2761 2762 /* Number of TCL data rings */ 2763 uint8_t num_tcl_data_rings; 2764 2765 /* TCL CMD_CREDIT ring */ 2766 bool init_tcl_cmd_cred_ring; 2767 2768 /* It is used as credit based ring on QCN9000 else command ring */ 2769 struct dp_srng tcl_cmd_credit_ring; 2770 2771 /* TCL command status ring */ 2772 struct dp_srng tcl_status_ring; 2773 2774 /* WBM Tx completion rings */ 2775 struct dp_srng tx_comp_ring[MAX_TCL_DATA_RINGS]; 2776 2777 /* Common WBM link descriptor release ring (SW to WBM) */ 2778 struct dp_srng wbm_desc_rel_ring; 2779 2780 /* DP Interrupts */ 2781 struct dp_intr intr_ctx[WLAN_CFG_INT_NUM_CONTEXTS]; 2782 2783 /* Monitor mode mac id to dp_intr_id map */ 2784 int mon_intr_id_lmac_map[MAX_NUM_LMAC_HW]; 2785 /* Rx SW descriptor pool for RXDMA monitor buffer */ 2786 struct rx_desc_pool rx_desc_mon[MAX_RXDESC_POOLS]; 2787 2788 /* Rx SW descriptor pool for RXDMA status buffer */ 2789 struct rx_desc_pool rx_desc_status[MAX_RXDESC_POOLS]; 2790 2791 /* Rx SW descriptor pool for RXDMA buffer */ 2792 struct rx_desc_pool rx_desc_buf[MAX_RXDESC_POOLS]; 2793 2794 /* Number of REO destination rings */ 2795 uint8_t num_reo_dest_rings; 2796 2797 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 2798 /* lock to control access to soc TX descriptors */ 2799 qdf_spinlock_t flow_pool_array_lock; 2800 2801 /* pause callback to pause TX queues as per flow control */ 2802 tx_pause_callback pause_cb; 2803 2804 /* flow pool related statistics */ 2805 struct dp_txrx_pool_stats pool_stats; 2806 #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */ 2807 2808 notify_pre_reset_fw_callback notify_fw_callback; 2809 2810 unsigned long service_rings_running; 2811 2812 uint32_t wbm_idle_scatter_buf_size; 2813 2814 /* VDEVs on this SOC */ 2815 struct dp_vdev *vdev_id_map[MAX_VDEV_CNT]; 2816 2817 uint8_t hw_txrx_stats_en:1; 2818 2819 /* Tx H/W queues lock */ 2820 qdf_spinlock_t tx_queue_lock[MAX_TX_HW_QUEUES]; 2821 2822 /* Tx ring map for interrupt processing */ 2823 uint8_t tx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 2824 2825 /* Rx ring map for interrupt processing */ 2826 uint8_t rx_ring_map[WLAN_CFG_INT_NUM_CONTEXTS]; 2827 2828 /* peer ID to peer object map (array of pointers to peer objects) */ 2829 struct dp_peer **peer_id_to_obj_map; 2830 2831 struct { 2832 unsigned mask; 2833 unsigned idx_bits; 2834 TAILQ_HEAD(, dp_peer) * bins; 2835 } peer_hash; 2836 2837 /* rx defrag state – TBD: do we need this per radio? */ 2838 struct { 2839 struct { 2840 TAILQ_HEAD(, dp_rx_tid_defrag) waitlist; 2841 uint32_t timeout_ms; 2842 uint32_t next_flush_ms; 2843 qdf_spinlock_t defrag_lock; 2844 } defrag; 2845 struct { 2846 int defrag_timeout_check; 2847 int dup_check; 2848 } flags; 2849 TAILQ_HEAD(, dp_reo_cmd_info) reo_cmd_list; 2850 qdf_spinlock_t reo_cmd_lock; 2851 } rx; 2852 2853 /* optional rx processing function */ 2854 void (*rx_opt_proc)( 2855 struct dp_vdev *vdev, 2856 struct dp_peer *peer, 2857 unsigned tid, 2858 qdf_nbuf_t msdu_list); 2859 2860 /* pool addr for mcast enhance buff */ 2861 struct { 2862 int size; 2863 uint32_t paddr; 2864 uint32_t *vaddr; 2865 struct dp_tx_me_buf_t *freelist; 2866 int buf_in_use; 2867 qdf_dma_mem_context(memctx); 2868 } me_buf; 2869 2870 /* Protect peer hash table */ 2871 DP_MUTEX_TYPE peer_hash_lock; 2872 /* Protect peer_id_to_objmap */ 2873 DP_MUTEX_TYPE peer_map_lock; 2874 2875 /* maximum number of suppoerted peers */ 2876 uint32_t max_peers; 2877 /* maximum value for peer_id */ 2878 uint32_t max_peer_id; 2879 2880 #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH 2881 uint32_t peer_id_shift; 2882 uint32_t peer_id_mask; 2883 #endif 2884 2885 /* rx peer metadata field shift and mask configuration */ 2886 uint8_t htt_peer_id_s; 2887 uint32_t htt_peer_id_m; 2888 uint8_t htt_vdev_id_s; 2889 uint32_t htt_vdev_id_m; 2890 uint8_t htt_mld_peer_valid_s; 2891 uint32_t htt_mld_peer_valid_m; 2892 /* rx peer metadata version */ 2893 uint8_t rx_peer_metadata_ver; 2894 2895 /* SoC level data path statistics */ 2896 struct dp_soc_stats stats; 2897 #ifdef WLAN_SYSFS_DP_STATS 2898 /* sysfs config for DP stats */ 2899 struct sysfs_stats_config *sysfs_config; 2900 #endif 2901 /* timestamp to keep track of msdu buffers received on reo err ring */ 2902 uint64_t rx_route_err_start_pkt_ts; 2903 2904 /* Num RX Route err in a given window to keep track of rate of errors */ 2905 uint32_t rx_route_err_in_window; 2906 2907 /* Enable processing of Tx completion status words */ 2908 bool process_tx_status; 2909 bool process_rx_status; 2910 struct dp_ast_entry **ast_table; 2911 struct { 2912 unsigned mask; 2913 unsigned idx_bits; 2914 TAILQ_HEAD(, dp_ast_entry) * bins; 2915 } ast_hash; 2916 2917 #ifdef DP_TX_HW_DESC_HISTORY 2918 struct dp_tx_hw_desc_history tx_hw_desc_history; 2919 #endif 2920 2921 #ifdef WLAN_FEATURE_DP_RX_RING_HISTORY 2922 struct dp_rx_history *rx_ring_history[MAX_REO_DEST_RINGS]; 2923 struct dp_rx_refill_history *rx_refill_ring_history[MAX_PDEV_CNT]; 2924 struct dp_rx_err_history *rx_err_ring_history; 2925 struct dp_rx_reinject_history *rx_reinject_ring_history; 2926 #endif 2927 2928 #ifdef WLAN_FEATURE_DP_MON_STATUS_RING_HISTORY 2929 struct dp_mon_status_ring_history *mon_status_ring_history; 2930 #endif 2931 2932 #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY 2933 struct dp_tx_tcl_history tx_tcl_history; 2934 struct dp_tx_comp_history tx_comp_history; 2935 #endif 2936 2937 #ifdef WLAN_FEATURE_DP_CFG_EVENT_HISTORY 2938 struct dp_cfg_event_history cfg_event_history; 2939 #endif 2940 2941 qdf_spinlock_t ast_lock; 2942 /*Timer for AST entry ageout maintenance */ 2943 qdf_timer_t ast_aging_timer; 2944 2945 /*Timer counter for WDS AST entry ageout*/ 2946 uint8_t wds_ast_aging_timer_cnt; 2947 bool pending_ageout; 2948 bool ast_offload_support; 2949 bool host_ast_db_enable; 2950 uint32_t max_ast_ageout_count; 2951 uint8_t eapol_over_control_port; 2952 2953 uint8_t sta_mode_search_policy; 2954 qdf_timer_t lmac_reap_timer; 2955 uint8_t lmac_timer_init; 2956 qdf_timer_t int_timer; 2957 uint8_t intr_mode; 2958 uint8_t lmac_polled_mode; 2959 2960 qdf_list_t reo_desc_freelist; 2961 qdf_spinlock_t reo_desc_freelist_lock; 2962 2963 /* htt stats */ 2964 struct htt_t2h_stats htt_stats; 2965 2966 void *external_txrx_handle; /* External data path handle */ 2967 qdf_atomic_t ipa_map_allowed; 2968 #ifdef IPA_OFFLOAD 2969 struct ipa_dp_tx_rsc ipa_uc_tx_rsc; 2970 #ifdef IPA_WDI3_TX_TWO_PIPES 2971 /* Resources for the alternative IPA TX pipe */ 2972 struct ipa_dp_tx_rsc ipa_uc_tx_rsc_alt; 2973 #endif 2974 2975 struct ipa_dp_rx_rsc ipa_uc_rx_rsc; 2976 #ifdef IPA_WDI3_VLAN_SUPPORT 2977 struct ipa_dp_rx_rsc ipa_uc_rx_rsc_alt; 2978 #endif 2979 qdf_atomic_t ipa_pipes_enabled; 2980 bool ipa_first_tx_db_access; 2981 qdf_spinlock_t ipa_rx_buf_map_lock; 2982 bool ipa_rx_buf_map_lock_initialized; 2983 uint8_t ipa_reo_ctx_lock_required[MAX_REO_DEST_RINGS]; 2984 #endif 2985 2986 #ifdef WLAN_FEATURE_STATS_EXT 2987 struct { 2988 uint32_t rx_mpdu_received; 2989 uint32_t rx_mpdu_missed; 2990 } ext_stats; 2991 qdf_event_t rx_hw_stats_event; 2992 qdf_spinlock_t rx_hw_stats_lock; 2993 bool is_last_stats_ctx_init; 2994 struct dp_req_rx_hw_stats_t *rx_hw_stats; 2995 #endif /* WLAN_FEATURE_STATS_EXT */ 2996 2997 /* Indicates HTT map/unmap versions*/ 2998 uint8_t peer_map_unmap_versions; 2999 /* Per peer per Tid ba window size support */ 3000 uint8_t per_tid_basize_max_tid; 3001 /* Soc level flag to enable da_war */ 3002 uint8_t da_war_enabled; 3003 /* number of active ast entries */ 3004 uint32_t num_ast_entries; 3005 /* peer extended rate statistics context at soc level*/ 3006 struct cdp_soc_rate_stats_ctx *rate_stats_ctx; 3007 /* peer extended rate statistics control flag */ 3008 bool peerstats_enabled; 3009 3010 /* 8021p PCP-TID map values */ 3011 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 3012 /* TID map priority value */ 3013 uint8_t tidmap_prty; 3014 /* Pointer to global per ring type specific configuration table */ 3015 struct wlan_srng_cfg *wlan_srng_cfg; 3016 /* Num Tx outstanding on device */ 3017 qdf_atomic_t num_tx_outstanding; 3018 /* Num Tx exception on device */ 3019 qdf_atomic_t num_tx_exception; 3020 /* Num Tx allowed */ 3021 uint32_t num_tx_allowed; 3022 /* Num Regular Tx allowed */ 3023 uint32_t num_reg_tx_allowed; 3024 /* Num Tx allowed for special frames*/ 3025 uint32_t num_tx_spl_allowed; 3026 /* Preferred HW mode */ 3027 uint8_t preferred_hw_mode; 3028 3029 /** 3030 * Flag to indicate whether WAR to address single cache entry 3031 * invalidation bug is enabled or not 3032 */ 3033 bool is_rx_fse_full_cache_invalidate_war_enabled; 3034 #if defined(WLAN_SUPPORT_RX_FLOW_TAG) 3035 /** 3036 * Pointer to DP RX Flow FST at SOC level if 3037 * is_rx_flow_search_table_per_pdev is false 3038 * TBD: rx_fst[num_macs] if we decide to have per mac FST 3039 */ 3040 struct dp_rx_fst *rx_fst; 3041 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 3042 /* SG supported for msdu continued packets from wbm release ring */ 3043 bool wbm_release_desc_rx_sg_support; 3044 bool peer_map_attach_success; 3045 /* Flag to disable mac1 ring interrupts */ 3046 bool disable_mac1_intr; 3047 /* Flag to disable mac2 ring interrupts */ 3048 bool disable_mac2_intr; 3049 3050 struct { 3051 /* 1st msdu in sg for msdu continued packets in wbm rel ring */ 3052 bool wbm_is_first_msdu_in_sg; 3053 /* Wbm sg list head */ 3054 qdf_nbuf_t wbm_sg_nbuf_head; 3055 /* Wbm sg list tail */ 3056 qdf_nbuf_t wbm_sg_nbuf_tail; 3057 uint32_t wbm_sg_desc_msdu_len; 3058 } wbm_sg_param; 3059 /* Number of msdu exception descriptors */ 3060 uint32_t num_msdu_exception_desc; 3061 3062 /* RX buffer params */ 3063 struct rx_buff_pool rx_buff_pool[MAX_PDEV_CNT]; 3064 struct rx_refill_buff_pool rx_refill_buff_pool; 3065 /* Save recent operation related variable */ 3066 struct dp_last_op_info last_op_info; 3067 TAILQ_HEAD(, dp_peer) inactive_peer_list; 3068 qdf_spinlock_t inactive_peer_list_lock; 3069 TAILQ_HEAD(, dp_vdev) inactive_vdev_list; 3070 qdf_spinlock_t inactive_vdev_list_lock; 3071 /* lock to protect vdev_id_map table*/ 3072 qdf_spinlock_t vdev_map_lock; 3073 3074 /* Flow Search Table is in CMEM */ 3075 bool fst_in_cmem; 3076 3077 #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR 3078 struct dp_swlm swlm; 3079 #endif 3080 3081 #ifdef FEATURE_RUNTIME_PM 3082 /* DP Rx timestamp */ 3083 qdf_time_t rx_last_busy; 3084 /* Dp runtime refcount */ 3085 qdf_atomic_t dp_runtime_refcount; 3086 /* Dp tx pending count in RTPM */ 3087 qdf_atomic_t tx_pending_rtpm; 3088 #endif 3089 /* Invalid buffer that allocated for RX buffer */ 3090 qdf_nbuf_queue_t invalid_buf_queue; 3091 3092 #ifdef FEATURE_MEC 3093 /** @mec_lock: spinlock for MEC table */ 3094 qdf_spinlock_t mec_lock; 3095 /** @mec_cnt: number of active mec entries */ 3096 qdf_atomic_t mec_cnt; 3097 struct { 3098 /** @mask: mask bits */ 3099 uint32_t mask; 3100 /** @idx_bits: index to shift bits */ 3101 uint32_t idx_bits; 3102 /** @bins: MEC table */ 3103 TAILQ_HEAD(, dp_mec_entry) * bins; 3104 } mec_hash; 3105 #endif 3106 3107 #ifdef WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY 3108 qdf_list_t reo_desc_deferred_freelist; 3109 qdf_spinlock_t reo_desc_deferred_freelist_lock; 3110 bool reo_desc_deferred_freelist_init; 3111 #endif 3112 /* BM id for first WBM2SW ring */ 3113 uint32_t wbm_sw0_bm_id; 3114 3115 /* Store arch_id from device_id */ 3116 uint16_t arch_id; 3117 3118 /* link desc ID start per device type */ 3119 uint32_t link_desc_id_start; 3120 3121 /* CMEM buffer target reserved for host usage */ 3122 uint64_t cmem_base; 3123 /* CMEM size in bytes */ 3124 uint64_t cmem_total_size; 3125 /* CMEM free size in bytes */ 3126 uint64_t cmem_avail_size; 3127 3128 /* SOC level feature flags */ 3129 struct dp_soc_features features; 3130 3131 #ifdef WIFI_MONITOR_SUPPORT 3132 struct dp_mon_soc *monitor_soc; 3133 #endif 3134 uint8_t rxdma2sw_rings_not_supported:1, 3135 wbm_sg_last_msdu_war:1, 3136 mec_fw_offload:1, 3137 multi_peer_grp_cmd_supported:1, 3138 umac_reset_supported:1; 3139 3140 /* Number of Rx refill rings */ 3141 uint8_t num_rx_refill_buf_rings; 3142 #ifdef FEATURE_RUNTIME_PM 3143 /* flag to indicate vote for runtime_pm for high tput castt*/ 3144 qdf_atomic_t rtpm_high_tput_flag; 3145 #endif 3146 /* Buffer manager ID for idle link descs */ 3147 uint8_t idle_link_bm_id; 3148 qdf_atomic_t ref_count; 3149 3150 unsigned long vdev_stats_id_map; 3151 bool txmon_hw_support; 3152 3153 #ifdef DP_UMAC_HW_RESET_SUPPORT 3154 struct dp_soc_umac_reset_ctx umac_reset_ctx; 3155 #endif 3156 /* PPDU to link_id mapping parameters */ 3157 uint8_t link_id_offset; 3158 uint8_t link_id_bits; 3159 #ifdef FEATURE_RX_LINKSPEED_ROAM_TRIGGER 3160 /* A flag using to decide the switch of rx link speed */ 3161 bool high_throughput; 3162 #endif 3163 bool is_tx_pause; 3164 3165 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 3166 /* number of IPv4 flows inserted */ 3167 qdf_atomic_t ipv4_fse_cnt; 3168 /* number of IPv6 flows inserted */ 3169 qdf_atomic_t ipv6_fse_cnt; 3170 #endif 3171 /* Reo queue ref table items */ 3172 struct reo_queue_ref_table reo_qref; 3173 #ifdef DP_TX_PACKET_INSPECT_FOR_ILP 3174 /* Flag to show if TX ILP is enabled */ 3175 bool tx_ilp_enable; 3176 #endif 3177 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 3178 uint8_t mld_mode_ap; 3179 #endif 3180 struct test_qaddr_del *list_shared_qaddr_del; 3181 struct test_qaddr_del *reo_write_list; 3182 struct test_mem_free *list_qdesc_addr_free; 3183 struct test_mem_free *list_qdesc_addr_alloc; 3184 uint64_t free_addr_list_idx; 3185 uint64_t alloc_addr_list_idx; 3186 uint64_t shared_qaddr_del_idx; 3187 uint64_t write_paddr_list_idx; 3188 3189 #ifdef WLAN_FEATURE_TX_LATENCY_STATS 3190 /* callback function for tx latency stats */ 3191 cdp_tx_latency_cb tx_latency_cb; 3192 #endif 3193 }; 3194 3195 #ifdef IPA_OFFLOAD 3196 /** 3197 * struct dp_ipa_resources - Resources needed for IPA 3198 * @tx_ring: 3199 * @tx_num_alloc_buffer: 3200 * @tx_comp_ring: 3201 * @rx_rdy_ring: 3202 * @rx_refill_ring: 3203 * @tx_comp_doorbell_paddr: IPA UC doorbell registers paddr 3204 * @tx_comp_doorbell_vaddr: 3205 * @rx_ready_doorbell_paddr: 3206 * @is_db_ddr_mapped: 3207 * @tx_alt_ring: 3208 * @tx_alt_ring_num_alloc_buffer: 3209 * @tx_alt_comp_ring: 3210 * @tx_alt_comp_doorbell_paddr: IPA UC doorbell registers paddr 3211 * @tx_alt_comp_doorbell_vaddr: 3212 * @rx_alt_rdy_ring: 3213 * @rx_alt_refill_ring: 3214 * @rx_alt_ready_doorbell_paddr: 3215 */ 3216 struct dp_ipa_resources { 3217 qdf_shared_mem_t tx_ring; 3218 uint32_t tx_num_alloc_buffer; 3219 3220 qdf_shared_mem_t tx_comp_ring; 3221 qdf_shared_mem_t rx_rdy_ring; 3222 qdf_shared_mem_t rx_refill_ring; 3223 3224 /* IPA UC doorbell registers paddr */ 3225 qdf_dma_addr_t tx_comp_doorbell_paddr; 3226 uint32_t *tx_comp_doorbell_vaddr; 3227 qdf_dma_addr_t rx_ready_doorbell_paddr; 3228 3229 bool is_db_ddr_mapped; 3230 3231 #ifdef IPA_WDI3_TX_TWO_PIPES 3232 qdf_shared_mem_t tx_alt_ring; 3233 uint32_t tx_alt_ring_num_alloc_buffer; 3234 qdf_shared_mem_t tx_alt_comp_ring; 3235 3236 /* IPA UC doorbell registers paddr */ 3237 qdf_dma_addr_t tx_alt_comp_doorbell_paddr; 3238 uint32_t *tx_alt_comp_doorbell_vaddr; 3239 #endif 3240 #ifdef IPA_WDI3_VLAN_SUPPORT 3241 qdf_shared_mem_t rx_alt_rdy_ring; 3242 qdf_shared_mem_t rx_alt_refill_ring; 3243 qdf_dma_addr_t rx_alt_ready_doorbell_paddr; 3244 #endif 3245 }; 3246 #endif 3247 3248 #define MAX_RX_MAC_RINGS 2 3249 /* Same as NAC_MAX_CLENT */ 3250 #define DP_NAC_MAX_CLIENT 24 3251 3252 /* 3253 * 24 bits cookie size 3254 * 10 bits page id 0 ~ 1023 for MCL 3255 * 3 bits page id 0 ~ 7 for WIN 3256 * WBM Idle List Desc size = 128, 3257 * Num descs per page = 4096/128 = 32 for MCL 3258 * Num descs per page = 2MB/128 = 16384 for WIN 3259 */ 3260 /* 3261 * Macros to setup link descriptor cookies - for link descriptors, we just 3262 * need first 3 bits to store bank/page ID for WIN. The 3263 * remaining bytes will be used to set a unique ID, which will 3264 * be useful in debugging 3265 */ 3266 #ifdef MAX_ALLOC_PAGE_SIZE 3267 #if PAGE_SIZE == 4096 3268 #define LINK_DESC_PAGE_ID_MASK 0x007FE0 3269 #define LINK_DESC_ID_SHIFT 5 3270 #define LINK_DESC_ID_START_21_BITS_COOKIE 0x8000 3271 #elif PAGE_SIZE == 65536 3272 #define LINK_DESC_PAGE_ID_MASK 0x007E00 3273 #define LINK_DESC_ID_SHIFT 9 3274 #define LINK_DESC_ID_START_21_BITS_COOKIE 0x800 3275 #else 3276 #error "Unsupported kernel PAGE_SIZE" 3277 #endif 3278 #define LINK_DESC_COOKIE(_desc_id, _page_id, _desc_id_start) \ 3279 ((((_page_id) + (_desc_id_start)) << LINK_DESC_ID_SHIFT) | (_desc_id)) 3280 #define LINK_DESC_COOKIE_PAGE_ID(_cookie) \ 3281 (((_cookie) & LINK_DESC_PAGE_ID_MASK) >> LINK_DESC_ID_SHIFT) 3282 #else 3283 #define LINK_DESC_PAGE_ID_MASK 0x7 3284 #define LINK_DESC_ID_SHIFT 3 3285 #define LINK_DESC_COOKIE(_desc_id, _page_id, _desc_id_start) \ 3286 ((((_desc_id) + (_desc_id_start)) << LINK_DESC_ID_SHIFT) | (_page_id)) 3287 #define LINK_DESC_COOKIE_PAGE_ID(_cookie) \ 3288 ((_cookie) & LINK_DESC_PAGE_ID_MASK) 3289 #define LINK_DESC_ID_START_21_BITS_COOKIE 0x8000 3290 #endif 3291 #define LINK_DESC_ID_START_20_BITS_COOKIE 0x4000 3292 3293 /* same as ieee80211_nac_param */ 3294 enum dp_nac_param_cmd { 3295 /* IEEE80211_NAC_PARAM_ADD */ 3296 DP_NAC_PARAM_ADD = 1, 3297 /* IEEE80211_NAC_PARAM_DEL */ 3298 DP_NAC_PARAM_DEL, 3299 /* IEEE80211_NAC_PARAM_LIST */ 3300 DP_NAC_PARAM_LIST, 3301 }; 3302 3303 /** 3304 * struct dp_neighbour_peer - neighbour peer list type for smart mesh 3305 * @neighbour_peers_macaddr: neighbour peer's mac address 3306 * @vdev: associated vdev 3307 * @ast_entry: ast_entry for neighbour peer 3308 * @rssi: rssi value 3309 * @neighbour_peer_list_elem: neighbour peer list TAILQ element 3310 */ 3311 struct dp_neighbour_peer { 3312 union dp_align_mac_addr neighbour_peers_macaddr; 3313 struct dp_vdev *vdev; 3314 struct dp_ast_entry *ast_entry; 3315 uint8_t rssi; 3316 TAILQ_ENTRY(dp_neighbour_peer) neighbour_peer_list_elem; 3317 }; 3318 3319 #ifdef WLAN_TX_PKT_CAPTURE_ENH 3320 #define WLAN_TX_PKT_CAPTURE_ENH 1 3321 #define DP_TX_PPDU_PROC_THRESHOLD 8 3322 #define DP_TX_PPDU_PROC_TIMEOUT 10 3323 #endif 3324 3325 /** 3326 * struct ppdu_info - PPDU Status info descriptor 3327 * @ppdu_id: Unique ppduid assigned by firmware for every tx packet 3328 * @sched_cmdid: schedule command id, which will be same in a burst 3329 * @max_ppdu_id: wrap around for ppdu id 3330 * @tsf_l32: 3331 * @tlv_bitmap: 3332 * @last_tlv_cnt: Keep track for missing ppdu tlvs 3333 * @last_user: last ppdu processed for user 3334 * @is_ampdu: set if Ampdu aggregate 3335 * @nbuf: ppdu descriptor payload 3336 * @ppdu_desc: ppdu descriptor 3337 * @ulist: Union of lists 3338 * @ppdu_info_dlist_elem: linked list of ppdu tlvs 3339 * @ppdu_info_slist_elem: Singly linked list (queue) of ppdu tlvs 3340 * @ppdu_info_list_elem: linked list of ppdu tlvs 3341 * @ppdu_info_queue_elem: Singly linked list (queue) of ppdu tlvs 3342 * @compltn_common_tlv: Successful tlv counter from COMPLTN COMMON tlv 3343 * @ack_ba_tlv: Successful tlv counter from ACK BA tlv 3344 * @done: 3345 */ 3346 struct ppdu_info { 3347 uint32_t ppdu_id; 3348 uint32_t sched_cmdid; 3349 uint32_t max_ppdu_id; 3350 uint32_t tsf_l32; 3351 uint16_t tlv_bitmap; 3352 uint16_t last_tlv_cnt; 3353 uint16_t last_user:8, 3354 is_ampdu:1; 3355 qdf_nbuf_t nbuf; 3356 struct cdp_tx_completion_ppdu *ppdu_desc; 3357 #ifdef WLAN_TX_PKT_CAPTURE_ENH 3358 union { 3359 TAILQ_ENTRY(ppdu_info) ppdu_info_dlist_elem; 3360 STAILQ_ENTRY(ppdu_info) ppdu_info_slist_elem; 3361 } ulist; 3362 #define ppdu_info_list_elem ulist.ppdu_info_dlist_elem 3363 #define ppdu_info_queue_elem ulist.ppdu_info_slist_elem 3364 #else 3365 TAILQ_ENTRY(ppdu_info) ppdu_info_list_elem; 3366 #endif 3367 uint8_t compltn_common_tlv; 3368 uint8_t ack_ba_tlv; 3369 bool done; 3370 }; 3371 3372 /** 3373 * struct msdu_completion_info - wbm msdu completion info 3374 * @ppdu_id: Unique ppduid assigned by firmware for every tx packet 3375 * @peer_id: peer_id 3376 * @tid: tid which used during transmit 3377 * @first_msdu: first msdu indication 3378 * @last_msdu: last msdu indication 3379 * @msdu_part_of_amsdu: msdu part of amsdu 3380 * @transmit_cnt: retried count 3381 * @status: transmit status 3382 * @tsf: timestamp which it transmitted 3383 */ 3384 struct msdu_completion_info { 3385 uint32_t ppdu_id; 3386 uint16_t peer_id; 3387 uint8_t tid; 3388 uint8_t first_msdu:1, 3389 last_msdu:1, 3390 msdu_part_of_amsdu:1; 3391 uint8_t transmit_cnt; 3392 uint8_t status; 3393 uint32_t tsf; 3394 }; 3395 3396 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 3397 struct rx_protocol_tag_map { 3398 /* This is the user configured tag for the said protocol type */ 3399 uint16_t tag; 3400 }; 3401 3402 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 3403 /** 3404 * struct rx_protocol_tag_stats - protocol statistics 3405 * @tag_ctr: number of rx msdus matching this tag 3406 */ 3407 struct rx_protocol_tag_stats { 3408 uint32_t tag_ctr; 3409 }; 3410 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 3411 3412 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 3413 3414 #ifdef WLAN_RX_PKT_CAPTURE_ENH 3415 /* Template data to be set for Enhanced RX Monitor packets */ 3416 #define RX_MON_CAP_ENH_TRAILER 0xdeadc0dedeadda7a 3417 3418 /** 3419 * struct dp_rx_mon_enh_trailer_data - Data structure to set a known pattern 3420 * at end of each MSDU in monitor-lite mode 3421 * @reserved1: reserved for future use 3422 * @reserved2: reserved for future use 3423 * @flow_tag: flow tag value read from skb->cb 3424 * @protocol_tag: protocol tag value read from skb->cb 3425 */ 3426 struct dp_rx_mon_enh_trailer_data { 3427 uint16_t reserved1; 3428 uint16_t reserved2; 3429 uint16_t flow_tag; 3430 uint16_t protocol_tag; 3431 }; 3432 #endif /* WLAN_RX_PKT_CAPTURE_ENH */ 3433 3434 #ifdef HTT_STATS_DEBUGFS_SUPPORT 3435 /* Number of debugfs entries created for HTT stats */ 3436 #define PDEV_HTT_STATS_DBGFS_SIZE HTT_DBG_NUM_EXT_STATS 3437 3438 /** 3439 * struct pdev_htt_stats_dbgfs_priv - Structure to maintain debugfs information 3440 * of HTT stats 3441 * @pdev: dp pdev of debugfs entry 3442 * @stats_id: stats id of debugfs entry 3443 */ 3444 struct pdev_htt_stats_dbgfs_priv { 3445 struct dp_pdev *pdev; 3446 uint16_t stats_id; 3447 }; 3448 3449 /** 3450 * struct pdev_htt_stats_dbgfs_cfg - PDEV level data structure for debugfs 3451 * support for HTT stats 3452 * @debugfs_entry: qdf_debugfs directory entry 3453 * @m: qdf debugfs file handler 3454 * @pdev_htt_stats_dbgfs_ops: File operations of entry created 3455 * @priv: HTT stats debugfs private object 3456 * @htt_stats_dbgfs_event: HTT stats event for debugfs support 3457 * @lock: HTT stats debugfs lock 3458 * @htt_stats_dbgfs_msg_process: Function callback to print HTT stats 3459 */ 3460 struct pdev_htt_stats_dbgfs_cfg { 3461 qdf_dentry_t debugfs_entry[PDEV_HTT_STATS_DBGFS_SIZE]; 3462 qdf_debugfs_file_t m; 3463 struct qdf_debugfs_fops 3464 pdev_htt_stats_dbgfs_ops[PDEV_HTT_STATS_DBGFS_SIZE - 1]; 3465 struct pdev_htt_stats_dbgfs_priv priv[PDEV_HTT_STATS_DBGFS_SIZE - 1]; 3466 qdf_event_t htt_stats_dbgfs_event; 3467 qdf_mutex_t lock; 3468 void (*htt_stats_dbgfs_msg_process)(void *data, A_INT32 len); 3469 }; 3470 #endif /* HTT_STATS_DEBUGFS_SUPPORT */ 3471 3472 struct dp_srng_ring_state { 3473 enum hal_ring_type ring_type; 3474 uint32_t sw_head; 3475 uint32_t sw_tail; 3476 uint32_t hw_head; 3477 uint32_t hw_tail; 3478 3479 }; 3480 3481 struct dp_soc_srngs_state { 3482 uint32_t seq_num; 3483 uint32_t max_ring_id; 3484 struct dp_srng_ring_state ring_state[DP_MAX_SRNGS]; 3485 TAILQ_ENTRY(dp_soc_srngs_state) list_elem; 3486 }; 3487 3488 #ifdef WLAN_FEATURE_11BE_MLO 3489 /* struct dp_mlo_sync_timestamp - PDEV level data structure for storing 3490 * MLO timestamp received via HTT msg. 3491 * msg_type: This would be set to HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND 3492 * pdev_id: pdev_id 3493 * chip_id: chip_id 3494 * mac_clk_freq: mac clock frequency of the mac HW block in MHz 3495 * sync_tstmp_lo_us: lower 32 bits of the WLAN global time stamp (in us) at 3496 * which last sync interrupt was received 3497 * sync_tstmp_hi_us: upper 32 bits of the WLAN global time stamp (in us) at 3498 * which last sync interrupt was received 3499 * mlo_offset_lo_us: lower 32 bits of the MLO time stamp offset in us 3500 * mlo_offset_hi_us: upper 32 bits of the MLO time stamp offset in us 3501 * mlo_offset_clks: MLO time stamp offset in clock ticks for sub us 3502 * mlo_comp_us: MLO time stamp compensation applied in us 3503 * mlo_comp_clks: MLO time stamp compensation applied in clock ticks 3504 * for sub us resolution 3505 * mlo_comp_timer: period of MLO compensation timer at which compensation 3506 * is applied, in us 3507 */ 3508 struct dp_mlo_sync_timestamp { 3509 uint32_t msg_type:8, 3510 pdev_id:2, 3511 chip_id:2, 3512 rsvd1:4, 3513 mac_clk_freq:16; 3514 uint32_t sync_tstmp_lo_us; 3515 uint32_t sync_tstmp_hi_us; 3516 uint32_t mlo_offset_lo_us; 3517 uint32_t mlo_offset_hi_us; 3518 uint32_t mlo_offset_clks; 3519 uint32_t mlo_comp_us:16, 3520 mlo_comp_clks:10, 3521 rsvd2:6; 3522 uint32_t mlo_comp_timer:22, 3523 rsvd3:10; 3524 }; 3525 #endif 3526 3527 /* PDEV level structure for data path */ 3528 struct dp_pdev { 3529 /** 3530 * Re-use Memory Section Starts 3531 */ 3532 3533 /* PDEV Id */ 3534 uint8_t pdev_id; 3535 3536 /* LMAC Id */ 3537 uint8_t lmac_id; 3538 3539 /* Target pdev Id */ 3540 uint8_t target_pdev_id; 3541 3542 bool pdev_deinit; 3543 3544 /* TXRX SOC handle */ 3545 struct dp_soc *soc; 3546 3547 /* pdev status down or up required to handle dynamic hw 3548 * mode switch between DBS and DBS_SBS. 3549 * 1 = down 3550 * 0 = up 3551 */ 3552 bool is_pdev_down; 3553 3554 /* Enhanced Stats is enabled */ 3555 uint8_t enhanced_stats_en:1, 3556 link_peer_stats:1; 3557 3558 /* Flag to indicate fast path Tx flags */ 3559 uint32_t tx_fast_flag; 3560 3561 /* Flag to indicate fast RX */ 3562 bool rx_fast_flag; 3563 3564 /* Second ring used to replenish rx buffers */ 3565 struct dp_srng rx_refill_buf_ring2; 3566 #ifdef IPA_WDI3_VLAN_SUPPORT 3567 /* Third ring used to replenish rx buffers */ 3568 struct dp_srng rx_refill_buf_ring3; 3569 #endif 3570 3571 #ifdef FEATURE_DIRECT_LINK 3572 /* Fourth ring used to replenish rx buffers */ 3573 struct dp_srng rx_refill_buf_ring4; 3574 #endif 3575 3576 /* Empty ring used by firmware to post rx buffers to the MAC */ 3577 struct dp_srng rx_mac_buf_ring[MAX_RX_MAC_RINGS]; 3578 3579 int ch_band_lmac_id_mapping[REG_BAND_UNKNOWN]; 3580 3581 /* wlan_cfg pdev ctxt*/ 3582 struct wlan_cfg_dp_pdev_ctxt *wlan_cfg_ctx; 3583 3584 /** 3585 * TODO: See if we need a ring map here for LMAC rings. 3586 * 1. Monitor rings are currently planning to be processed on receiving 3587 * PPDU end interrupts and hence won't need ring based interrupts. 3588 * 2. Rx buffer rings will be replenished during REO destination 3589 * processing and doesn't require regular interrupt handling - we will 3590 * only handle low water mark interrupts which is not expected 3591 * frequently 3592 */ 3593 3594 /* VDEV list */ 3595 TAILQ_HEAD(, dp_vdev) vdev_list; 3596 3597 /* vdev list lock */ 3598 qdf_spinlock_t vdev_list_lock; 3599 3600 /* Number of vdevs this device have */ 3601 uint16_t vdev_count; 3602 3603 /* PDEV transmit lock */ 3604 qdf_spinlock_t tx_lock; 3605 3606 /*tx_mutex for me*/ 3607 DP_MUTEX_TYPE tx_mutex; 3608 3609 /* msdu chain head & tail */ 3610 qdf_nbuf_t invalid_peer_head_msdu; 3611 qdf_nbuf_t invalid_peer_tail_msdu; 3612 3613 /* Band steering */ 3614 /* TBD */ 3615 3616 /* PDEV level data path statistics */ 3617 struct cdp_pdev_stats stats; 3618 3619 /* Global RX decap mode for the device */ 3620 enum htt_pkt_type rx_decap_mode; 3621 3622 qdf_atomic_t num_tx_outstanding; 3623 int32_t tx_descs_max; 3624 3625 qdf_atomic_t num_tx_exception; 3626 3627 /* MCL specific local peer handle */ 3628 struct { 3629 uint8_t pool[OL_TXRX_NUM_LOCAL_PEER_IDS + 1]; 3630 uint8_t freelist; 3631 qdf_spinlock_t lock; 3632 struct dp_peer *map[OL_TXRX_NUM_LOCAL_PEER_IDS]; 3633 } local_peer_ids; 3634 3635 /* dscp_tid_map_*/ 3636 uint8_t dscp_tid_map[DP_MAX_TID_MAPS][DSCP_TID_MAP_MAX]; 3637 3638 /* operating channel */ 3639 struct { 3640 uint8_t num; 3641 uint8_t band; 3642 uint16_t freq; 3643 } operating_channel; 3644 3645 /* pool addr for mcast enhance buff */ 3646 struct { 3647 int size; 3648 uint32_t paddr; 3649 char *vaddr; 3650 struct dp_tx_me_buf_t *freelist; 3651 int buf_in_use; 3652 qdf_dma_mem_context(memctx); 3653 } me_buf; 3654 3655 bool hmmc_tid_override_en; 3656 uint8_t hmmc_tid; 3657 3658 /* Number of VAPs with mcast enhancement enabled */ 3659 qdf_atomic_t mc_num_vap_attached; 3660 3661 qdf_atomic_t stats_cmd_complete; 3662 3663 #ifdef IPA_OFFLOAD 3664 ipa_uc_op_cb_type ipa_uc_op_cb; 3665 void *usr_ctxt; 3666 struct dp_ipa_resources ipa_resource; 3667 #endif 3668 3669 /* TBD */ 3670 3671 /* map this pdev to a particular Reo Destination ring */ 3672 enum cdp_host_reo_dest_ring reo_dest; 3673 3674 /* WDI event handlers */ 3675 struct wdi_event_subscribe_t **wdi_event_list; 3676 3677 bool cfr_rcc_mode; 3678 3679 /* enable time latency check for tx completion */ 3680 bool latency_capture_enable; 3681 3682 /* enable calculation of delay stats*/ 3683 bool delay_stats_flag; 3684 /* vow stats */ 3685 bool vow_stats; 3686 void *dp_txrx_handle; /* Advanced data path handle */ 3687 uint32_t ppdu_id; 3688 bool first_nbuf; 3689 /* Current noise-floor reading for the pdev channel */ 3690 int16_t chan_noise_floor; 3691 3692 /* 3693 * For multiradio device, this flag indicates if 3694 * this radio is primary or secondary. 3695 * 3696 * For HK 1.0, this is used for WAR for the AST issue. 3697 * HK 1.x mandates creation of only 1 AST entry with same MAC address 3698 * across 2 radios. is_primary indicates the radio on which DP should 3699 * install HW AST entry if there is a request to add 2 AST entries 3700 * with same MAC address across 2 radios 3701 */ 3702 uint8_t is_primary; 3703 struct cdp_tx_sojourn_stats sojourn_stats; 3704 qdf_nbuf_t sojourn_buf; 3705 3706 union dp_rx_desc_list_elem_t *free_list_head; 3707 union dp_rx_desc_list_elem_t *free_list_tail; 3708 /* Cached peer_id from htt_peer_details_tlv */ 3709 uint16_t fw_stats_peer_id; 3710 3711 /* qdf_event for fw_peer_stats */ 3712 qdf_event_t fw_peer_stats_event; 3713 3714 /* qdf_event for fw_stats */ 3715 qdf_event_t fw_stats_event; 3716 3717 /* qdf_event for fw__obss_stats */ 3718 qdf_event_t fw_obss_stats_event; 3719 3720 /* To check if request is already sent for obss stats */ 3721 bool pending_fw_obss_stats_response; 3722 3723 /* User configured max number of tx buffers */ 3724 uint32_t num_tx_allowed; 3725 3726 /* 3727 * User configured max num of tx buffers excluding the 3728 * number of buffers reserved for handling special frames 3729 */ 3730 uint32_t num_reg_tx_allowed; 3731 3732 /* User configured max number of tx buffers for the special frames*/ 3733 uint32_t num_tx_spl_allowed; 3734 3735 /* unique cookie required for peer session */ 3736 uint32_t next_peer_cookie; 3737 3738 /* 3739 * Run time enabled when the first protocol tag is added, 3740 * run time disabled when the last protocol tag is deleted 3741 */ 3742 bool is_rx_protocol_tagging_enabled; 3743 3744 #ifdef WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG 3745 /* 3746 * The protocol type is used as array index to save 3747 * user provided tag info 3748 */ 3749 struct rx_protocol_tag_map rx_proto_tag_map[RX_PROTOCOL_TAG_MAX]; 3750 3751 #ifdef WLAN_SUPPORT_RX_TAG_STATISTICS 3752 /* 3753 * Track msdus received from each reo ring separately to avoid 3754 * simultaneous writes from different core 3755 */ 3756 struct rx_protocol_tag_stats 3757 reo_proto_tag_stats[MAX_REO_DEST_RINGS][RX_PROTOCOL_TAG_MAX]; 3758 /* Track msdus received from exception ring separately */ 3759 struct rx_protocol_tag_stats 3760 rx_err_proto_tag_stats[RX_PROTOCOL_TAG_MAX]; 3761 struct rx_protocol_tag_stats 3762 mon_proto_tag_stats[RX_PROTOCOL_TAG_MAX]; 3763 #endif /* WLAN_SUPPORT_RX_TAG_STATISTICS */ 3764 #endif /* WLAN_SUPPORT_RX_PROTOCOL_TYPE_TAG */ 3765 3766 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 3767 /** 3768 * Pointer to DP Flow FST at SOC level if 3769 * is_rx_flow_search_table_per_pdev is true 3770 */ 3771 struct dp_rx_fst *rx_fst; 3772 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 3773 3774 #ifdef FEATURE_TSO_STATS 3775 /* TSO Id to index into TSO packet information */ 3776 qdf_atomic_t tso_idx; 3777 #endif /* FEATURE_TSO_STATS */ 3778 3779 #ifdef WLAN_SUPPORT_DATA_STALL 3780 data_stall_detect_cb data_stall_detect_callback; 3781 #endif /* WLAN_SUPPORT_DATA_STALL */ 3782 3783 /* flag to indicate whether LRO hash command has been sent to FW */ 3784 uint8_t is_lro_hash_configured; 3785 3786 #ifdef HTT_STATS_DEBUGFS_SUPPORT 3787 /* HTT stats debugfs params */ 3788 struct pdev_htt_stats_dbgfs_cfg *dbgfs_cfg; 3789 #endif 3790 struct { 3791 qdf_work_t work; 3792 qdf_workqueue_t *work_queue; 3793 uint32_t seq_num; 3794 uint8_t queue_depth; 3795 qdf_spinlock_t list_lock; 3796 3797 TAILQ_HEAD(, dp_soc_srngs_state) list; 3798 } bkp_stats; 3799 #ifdef WIFI_MONITOR_SUPPORT 3800 struct dp_mon_pdev *monitor_pdev; 3801 #endif 3802 #ifdef WLAN_FEATURE_11BE_MLO 3803 struct dp_mlo_sync_timestamp timestamp; 3804 #endif 3805 /* Is isolation mode enabled */ 3806 bool isolation; 3807 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 3808 uint8_t is_first_wakeup_packet; 3809 #endif 3810 #ifdef CONNECTIVITY_PKTLOG 3811 /* packetdump callback functions */ 3812 ol_txrx_pktdump_cb dp_tx_packetdump_cb; 3813 ol_txrx_pktdump_cb dp_rx_packetdump_cb; 3814 #endif 3815 3816 /* Firmware Stats for TLV received from Firmware */ 3817 uint64_t fw_stats_tlv_bitmap_rcvd; 3818 3819 /* For Checking Pending Firmware Response */ 3820 bool pending_fw_stats_response; 3821 }; 3822 3823 struct dp_peer; 3824 3825 #ifdef DP_RX_UDP_OVER_PEER_ROAM 3826 #define WLAN_ROAM_PEER_AUTH_STATUS_NONE 0x0 3827 /* 3828 * This macro is equivalent to macro ROAM_AUTH_STATUS_AUTHENTICATED used 3829 * in connection mgr 3830 */ 3831 #define WLAN_ROAM_PEER_AUTH_STATUS_AUTHENTICATED 0x2 3832 #endif 3833 3834 #ifdef WLAN_FEATURE_TX_LATENCY_STATS 3835 /** 3836 * struct dp_tx_latency_config - configuration for per-link transmit latency 3837 * statistics 3838 * @enabled: the feature is enabled or not 3839 * @report: async report is enabled or not 3840 * @granularity: granularity(in microseconds) of the distribution for the types 3841 */ 3842 struct dp_tx_latency_config { 3843 qdf_atomic_t enabled; 3844 qdf_atomic_t report; 3845 qdf_atomic_t granularity[CDP_TX_LATENCY_TYPE_MAX]; 3846 }; 3847 3848 /** 3849 * struct dp_tx_latency_stats - transmit latency distribution for a type 3850 * @latency_accum: accumulated latencies 3851 * @msdus_accum: accumulated number of msdus 3852 * @distribution: distribution of latencies 3853 */ 3854 struct dp_tx_latency_stats { 3855 qdf_atomic_t latency_accum; 3856 qdf_atomic_t msdus_accum; 3857 qdf_atomic_t distribution[CDP_TX_LATENCY_DISTR_LV_MAX]; 3858 }; 3859 3860 /** 3861 * struct dp_tx_latency - transmit latency statistics for remote link peer 3862 * @cur_idx: current row index of the 2D stats array 3863 * @stats: two-dimensional array, to store the transmit latency statistics. 3864 * one row is used to store the stats of the current cycle, it's indicated 3865 * by cur_idx, the other is for the last cycle. 3866 */ 3867 struct dp_tx_latency { 3868 uint8_t cur_idx; 3869 struct dp_tx_latency_stats stats[2][CDP_TX_LATENCY_TYPE_MAX]; 3870 }; 3871 #endif 3872 3873 /* VDEV structure for data path state */ 3874 struct dp_vdev { 3875 /* OS device abstraction */ 3876 qdf_device_t osdev; 3877 3878 /* physical device that is the parent of this virtual device */ 3879 struct dp_pdev *pdev; 3880 3881 /* VDEV operating mode */ 3882 enum wlan_op_mode opmode; 3883 3884 /* VDEV subtype */ 3885 enum wlan_op_subtype subtype; 3886 3887 /* Tx encapsulation type for this VAP */ 3888 enum htt_cmn_pkt_type tx_encap_type; 3889 3890 /* Rx Decapsulation type for this VAP */ 3891 enum htt_cmn_pkt_type rx_decap_type; 3892 3893 /* WDS enabled */ 3894 bool wds_enabled; 3895 3896 /* MEC enabled */ 3897 bool mec_enabled; 3898 3899 #ifdef QCA_SUPPORT_WDS_EXTENDED 3900 bool wds_ext_enabled; 3901 bool drop_tx_mcast; 3902 #endif /* QCA_SUPPORT_WDS_EXTENDED */ 3903 bool drop_3addr_mcast; 3904 #ifdef WLAN_VENDOR_SPECIFIC_BAR_UPDATE 3905 bool skip_bar_update; 3906 unsigned long skip_bar_update_last_ts; 3907 #endif 3908 /* WDS Aging timer period */ 3909 uint32_t wds_aging_timer_val; 3910 3911 /* NAWDS enabled */ 3912 bool nawds_enabled; 3913 3914 /* Multicast enhancement enabled */ 3915 uint8_t mcast_enhancement_en; 3916 3917 /* IGMP multicast enhancement enabled */ 3918 uint8_t igmp_mcast_enhanc_en; 3919 3920 /* vdev_id - ID used to specify a particular vdev to the target */ 3921 uint8_t vdev_id; 3922 3923 /* Default HTT meta data for this VDEV */ 3924 /* TBD: check alignment constraints */ 3925 uint16_t htt_tcl_metadata; 3926 3927 /* vdev lmac_id */ 3928 uint8_t lmac_id; 3929 3930 /* vdev bank_id */ 3931 uint8_t bank_id; 3932 3933 /* Mesh mode vdev */ 3934 uint32_t mesh_vdev; 3935 3936 /* Mesh mode rx filter setting */ 3937 uint32_t mesh_rx_filter; 3938 3939 /* DSCP-TID mapping table ID */ 3940 uint8_t dscp_tid_map_id; 3941 3942 /* Address search type to be set in TX descriptor */ 3943 uint8_t search_type; 3944 3945 /* 3946 * Flag to indicate if s/w tid classification should be 3947 * skipped 3948 */ 3949 uint8_t skip_sw_tid_classification; 3950 3951 /* Flag to enable peer authorization */ 3952 uint8_t peer_authorize; 3953 3954 /* AST hash value for BSS peer in HW valid for STA VAP*/ 3955 uint16_t bss_ast_hash; 3956 3957 /* AST hash index for BSS peer in HW valid for STA VAP*/ 3958 uint16_t bss_ast_idx; 3959 3960 bool multipass_en; 3961 3962 /* Address search flags to be configured in HAL descriptor */ 3963 uint8_t hal_desc_addr_search_flags; 3964 3965 /* Handle to the OS shim SW's virtual device */ 3966 ol_osif_vdev_handle osif_vdev; 3967 3968 /* MAC address */ 3969 union dp_align_mac_addr mac_addr; 3970 3971 #ifdef WLAN_FEATURE_11BE_MLO 3972 /* MLO MAC address corresponding to vdev */ 3973 union dp_align_mac_addr mld_mac_addr; 3974 #if defined(WLAN_MLO_MULTI_CHIP) && defined(WLAN_MCAST_MLO) 3975 uint8_t mlo_vdev:1, 3976 is_bridge_vdev:1, 3977 reserved_1:6; 3978 #endif 3979 #endif 3980 3981 /* node in the pdev's list of vdevs */ 3982 TAILQ_ENTRY(dp_vdev) vdev_list_elem; 3983 3984 /* dp_peer list */ 3985 TAILQ_HEAD(, dp_peer) peer_list; 3986 /* to protect peer_list */ 3987 DP_MUTEX_TYPE peer_list_lock; 3988 3989 /* RX call back function to flush GRO packets*/ 3990 ol_txrx_rx_gro_flush_ind_fp osif_gro_flush; 3991 /* default RX call back function called by dp */ 3992 ol_txrx_rx_fp osif_rx; 3993 #ifdef QCA_SUPPORT_EAPOL_OVER_CONTROL_PORT 3994 /* callback to receive eapol frames */ 3995 ol_txrx_rx_fp osif_rx_eapol; 3996 #endif 3997 /* callback to deliver rx frames to the OS */ 3998 ol_txrx_rx_fp osif_rx_stack; 3999 /* Callback to handle rx fisa frames */ 4000 ol_txrx_fisa_rx_fp osif_fisa_rx; 4001 ol_txrx_fisa_flush_fp osif_fisa_flush; 4002 4003 /* call back function to flush out queued rx packets*/ 4004 ol_txrx_rx_flush_fp osif_rx_flush; 4005 ol_txrx_rsim_rx_decap_fp osif_rsim_rx_decap; 4006 ol_txrx_get_key_fp osif_get_key; 4007 ol_txrx_tx_free_ext_fp osif_tx_free_ext; 4008 4009 #ifdef notyet 4010 /* callback to check if the msdu is an WAI (WAPI) frame */ 4011 ol_rx_check_wai_fp osif_check_wai; 4012 #endif 4013 4014 /* proxy arp function */ 4015 ol_txrx_proxy_arp_fp osif_proxy_arp; 4016 4017 ol_txrx_mcast_me_fp me_convert; 4018 4019 /* completion function used by this vdev*/ 4020 ol_txrx_completion_fp tx_comp; 4021 4022 ol_txrx_get_tsf_time get_tsf_time; 4023 4024 /* callback to classify critical packets */ 4025 ol_txrx_classify_critical_pkt_fp tx_classify_critical_pkt_cb; 4026 4027 /* deferred vdev deletion state */ 4028 struct { 4029 /* VDEV delete pending */ 4030 int pending; 4031 /* 4032 * callback and a context argument to provide a 4033 * notification for when the vdev is deleted. 4034 */ 4035 ol_txrx_vdev_delete_cb callback; 4036 void *context; 4037 } delete; 4038 4039 /* tx data delivery notification callback function */ 4040 struct { 4041 ol_txrx_data_tx_cb func; 4042 void *ctxt; 4043 } tx_non_std_data_callback; 4044 4045 4046 /* safe mode control to bypass the encrypt and decipher process*/ 4047 uint32_t safemode; 4048 4049 /* rx filter related */ 4050 uint32_t drop_unenc; 4051 #ifdef notyet 4052 privacy_exemption privacy_filters[MAX_PRIVACY_FILTERS]; 4053 uint32_t filters_num; 4054 #endif 4055 /* TDLS Link status */ 4056 bool tdls_link_connected; 4057 bool is_tdls_frame; 4058 4059 /* per vdev rx nbuf queue */ 4060 qdf_nbuf_queue_t rxq; 4061 4062 uint8_t tx_ring_id; 4063 struct dp_tx_desc_pool_s *tx_desc; 4064 struct dp_tx_ext_desc_pool_s *tx_ext_desc; 4065 4066 /* Capture timestamp of previous tx packet enqueued */ 4067 uint64_t prev_tx_enq_tstamp; 4068 4069 /* Capture timestamp of previous rx packet delivered */ 4070 uint64_t prev_rx_deliver_tstamp; 4071 4072 /* VDEV Stats */ 4073 struct cdp_vdev_stats stats; 4074 4075 /* Is this a proxySTA VAP */ 4076 uint8_t proxysta_vdev : 1, /* Is this a proxySTA VAP */ 4077 wrap_vdev : 1, /* Is this a QWRAP AP VAP */ 4078 isolation_vdev : 1, /* Is this a QWRAP AP VAP */ 4079 reserved : 5; /* Reserved */ 4080 4081 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 4082 struct dp_tx_desc_pool_s *pool; 4083 #endif 4084 /* AP BRIDGE enabled */ 4085 bool ap_bridge_enabled; 4086 4087 enum cdp_sec_type sec_type; 4088 4089 /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */ 4090 bool raw_mode_war; 4091 4092 4093 /* 8021p PCP-TID mapping table ID */ 4094 uint8_t tidmap_tbl_id; 4095 4096 /* 8021p PCP-TID map values */ 4097 uint8_t pcp_tid_map[PCP_TID_MAP_MAX]; 4098 4099 /* TIDmap priority */ 4100 uint8_t tidmap_prty; 4101 4102 #ifdef QCA_MULTIPASS_SUPPORT 4103 uint16_t *iv_vlan_map; 4104 4105 /* dp_peer special list */ 4106 TAILQ_HEAD(, dp_txrx_peer) mpass_peer_list; 4107 DP_MUTEX_TYPE mpass_peer_mutex; 4108 #endif 4109 /* Extended data path handle */ 4110 struct cdp_ext_vdev *vdev_dp_ext_handle; 4111 #ifdef VDEV_PEER_PROTOCOL_COUNT 4112 /* 4113 * Rx-Ingress and Tx-Egress are in the lower level DP layer 4114 * Rx-Egress and Tx-ingress are handled in osif layer for DP 4115 * So 4116 * Rx-Egress and Tx-ingress mask definitions are in OSIF layer 4117 * Rx-Ingress and Tx-Egress definitions are here below 4118 */ 4119 #define VDEV_PEER_PROTOCOL_RX_INGRESS_MASK 1 4120 #define VDEV_PEER_PROTOCOL_TX_INGRESS_MASK 2 4121 #define VDEV_PEER_PROTOCOL_RX_EGRESS_MASK 4 4122 #define VDEV_PEER_PROTOCOL_TX_EGRESS_MASK 8 4123 bool peer_protocol_count_track; 4124 int peer_protocol_count_dropmask; 4125 #endif 4126 /* callback to collect connectivity stats */ 4127 ol_txrx_stats_rx_fp stats_cb; 4128 uint32_t num_peers; 4129 /* entry to inactive_list*/ 4130 TAILQ_ENTRY(dp_vdev) inactive_list_elem; 4131 4132 #ifdef WLAN_SUPPORT_RX_FISA 4133 /** 4134 * Params used for controlling the fisa aggregation dynamically 4135 */ 4136 uint8_t fisa_disallowed[MAX_REO_DEST_RINGS]; 4137 uint8_t fisa_force_flushed[MAX_REO_DEST_RINGS]; 4138 #endif 4139 /* 4140 * Refcount for VDEV currently incremented when 4141 * peer is created for VDEV 4142 */ 4143 qdf_atomic_t ref_cnt; 4144 qdf_atomic_t mod_refs[DP_MOD_ID_MAX]; 4145 uint8_t num_latency_critical_conn; 4146 #ifdef WLAN_SUPPORT_MESH_LATENCY 4147 uint8_t peer_tid_latency_enabled; 4148 /* tid latency configuration parameters */ 4149 struct { 4150 uint32_t service_interval; 4151 uint32_t burst_size; 4152 uint8_t latency_tid; 4153 } mesh_tid_latency_config; 4154 #endif 4155 #ifdef WIFI_MONITOR_SUPPORT 4156 struct dp_mon_vdev *monitor_vdev; 4157 #endif 4158 #if defined(WLAN_FEATURE_TSF_AUTO_REPORT) || defined(WLAN_CONFIG_TX_DELAY) 4159 /* Delta between TQM clock and TSF clock */ 4160 uint32_t delta_tsf; 4161 #endif 4162 #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY 4163 /* Indicate if uplink delay report is enabled or not */ 4164 qdf_atomic_t ul_delay_report; 4165 /* accumulative delay for every TX completion */ 4166 qdf_atomic_t ul_delay_accum; 4167 /* accumulative number of packets delay has accumulated */ 4168 qdf_atomic_t ul_pkts_accum; 4169 #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */ 4170 4171 /* vdev_stats_id - ID used for stats collection by FW from HW*/ 4172 uint8_t vdev_stats_id; 4173 #ifdef HW_TX_DELAY_STATS_ENABLE 4174 /* hw tx delay stats enable */ 4175 uint8_t hw_tx_delay_stats_enabled; 4176 #endif 4177 #ifdef DP_RX_UDP_OVER_PEER_ROAM 4178 uint32_t roaming_peer_status; 4179 union dp_align_mac_addr roaming_peer_mac; 4180 #endif 4181 #ifdef DP_TRAFFIC_END_INDICATION 4182 /* per vdev feature enable/disable status */ 4183 bool traffic_end_ind_en; 4184 /* per vdev nbuf queue for traffic end indication packets */ 4185 qdf_nbuf_queue_t end_ind_pkt_q; 4186 #endif 4187 #ifdef FEATURE_DIRECT_LINK 4188 /* Flag to indicate if to_fw should be set for tx pkts on this vdev */ 4189 bool to_fw; 4190 #endif 4191 /* QDF VDEV operating mode */ 4192 enum QDF_OPMODE qdf_opmode; 4193 4194 #ifdef WLAN_TX_PKT_CAPTURE_ENH 4195 /* TX capture feature to over ride return buffer manager */ 4196 bool is_override_rbm_id; 4197 /* Return buffer manager ID */ 4198 uint8_t rbm_id; 4199 #endif 4200 4201 #ifdef WLAN_FEATURE_TX_LATENCY_STATS 4202 /* configuration for tx latency stats */ 4203 struct dp_tx_latency_config tx_latency_cfg; 4204 #endif 4205 }; 4206 4207 enum { 4208 dp_sec_mcast = 0, 4209 dp_sec_ucast 4210 }; 4211 4212 #ifdef WDS_VENDOR_EXTENSION 4213 typedef struct { 4214 uint8_t wds_tx_mcast_4addr:1, 4215 wds_tx_ucast_4addr:1, 4216 wds_rx_filter:1, /* enforce rx filter */ 4217 wds_rx_ucast_4addr:1, /* when set, accept 4addr unicast frames */ 4218 wds_rx_mcast_4addr:1; /* when set, accept 4addr multicast frames */ 4219 4220 } dp_ecm_policy; 4221 #endif 4222 4223 /** 4224 * struct dp_peer_cached_bufq - cached_bufq to enqueue rx packets 4225 * @cached_bufq: nbuff list to enqueue rx packets 4226 * @bufq_lock: spinlock for nbuff list access 4227 * @thresh: maximum threshold for number of rx buff to enqueue 4228 * @entries: number of entries 4229 * @dropped: number of packets dropped 4230 */ 4231 struct dp_peer_cached_bufq { 4232 qdf_list_t cached_bufq; 4233 qdf_spinlock_t bufq_lock; 4234 uint32_t thresh; 4235 uint32_t entries; 4236 uint32_t dropped; 4237 }; 4238 4239 /** 4240 * enum dp_peer_ast_flowq 4241 * @DP_PEER_AST_FLOWQ_HI_PRIO: Hi Priority flow queue 4242 * @DP_PEER_AST_FLOWQ_LOW_PRIO: Low priority flow queue 4243 * @DP_PEER_AST_FLOWQ_UDP: flow queue type is UDP 4244 * @DP_PEER_AST_FLOWQ_NON_UDP: flow queue type is Non UDP 4245 * @DP_PEER_AST_FLOWQ_MAX: max value 4246 */ 4247 enum dp_peer_ast_flowq { 4248 DP_PEER_AST_FLOWQ_HI_PRIO, 4249 DP_PEER_AST_FLOWQ_LOW_PRIO, 4250 DP_PEER_AST_FLOWQ_UDP, 4251 DP_PEER_AST_FLOWQ_NON_UDP, 4252 DP_PEER_AST_FLOWQ_MAX, 4253 }; 4254 4255 /** 4256 * struct dp_ast_flow_override_info - ast override info 4257 * @ast_idx: ast indexes in peer map message 4258 * @ast_valid_mask: ast valid mask for each ast index 4259 * @ast_flow_mask: ast flow mask for each ast index 4260 * @tid_valid_low_pri_mask: per tid mask for low priority flow 4261 * @tid_valid_hi_pri_mask: per tid mask for hi priority flow 4262 */ 4263 struct dp_ast_flow_override_info { 4264 uint16_t ast_idx[DP_PEER_AST_FLOWQ_MAX]; 4265 uint8_t ast_valid_mask; 4266 uint8_t ast_flow_mask[DP_PEER_AST_FLOWQ_MAX]; 4267 uint8_t tid_valid_low_pri_mask; 4268 uint8_t tid_valid_hi_pri_mask; 4269 }; 4270 4271 #if defined(WLAN_FEATURE_11BE_MLO) && defined(DP_MLO_LINK_STATS_SUPPORT) 4272 /** 4273 * struct dp_peer_ext_evt_info - peer extended event info 4274 * @peer_id: peer_id from firmware 4275 * @vdev_id: vdev ID 4276 * @link_id: Link ID 4277 * @link_id_valid: link_id_valid 4278 * @peer_mac_addr: mac address of the peer 4279 */ 4280 struct dp_peer_ext_evt_info { 4281 uint16_t peer_id; 4282 uint8_t vdev_id; 4283 uint8_t link_id; 4284 bool link_id_valid; 4285 uint8_t *peer_mac_addr; 4286 }; 4287 #endif 4288 4289 /** 4290 * struct dp_peer_ast_params - ast parameters for a msdu flow-queue 4291 * @ast_idx: ast index populated by FW 4292 * @is_valid: ast flow valid mask 4293 * @valid_tid_mask: per tid mask for this ast index 4294 * @flowQ: flow queue id associated with this ast index 4295 */ 4296 struct dp_peer_ast_params { 4297 uint16_t ast_idx; 4298 uint8_t is_valid; 4299 uint8_t valid_tid_mask; 4300 uint8_t flowQ; 4301 }; 4302 4303 #define DP_MLO_FLOW_INFO_MAX 3 4304 4305 /** 4306 * struct dp_mlo_flow_override_info - Flow override info 4307 * @ast_idx: Primary TCL AST Index 4308 * @ast_idx_valid: Is AST index valid 4309 * @chip_id: CHIP ID 4310 * @tidmask: tidmask 4311 * @cache_set_num: Cache set number 4312 */ 4313 struct dp_mlo_flow_override_info { 4314 uint16_t ast_idx; 4315 uint8_t ast_idx_valid; 4316 uint8_t chip_id; 4317 uint8_t tidmask; 4318 uint8_t cache_set_num; 4319 }; 4320 4321 /** 4322 * struct dp_mlo_link_info - Link info 4323 * @peer_chip_id: Peer Chip ID 4324 * @vdev_id: Vdev ID 4325 */ 4326 struct dp_mlo_link_info { 4327 uint8_t peer_chip_id; 4328 uint8_t vdev_id; 4329 }; 4330 4331 #ifdef WLAN_SUPPORT_MSCS 4332 /*MSCS Procedure based macros */ 4333 #define IEEE80211_MSCS_MAX_ELEM_SIZE 5 4334 #define IEEE80211_TCLAS_MASK_CLA_TYPE_4 4 4335 /** 4336 * struct dp_peer_mscs_parameter - MSCS database obtained from 4337 * MSCS Request and Response in the control path. This data is used 4338 * by the AP to find out what priority to set based on the tuple 4339 * classification during packet processing. 4340 * @user_priority_bitmap: User priority bitmap obtained during 4341 * handshake 4342 * @user_priority_limit: User priority limit obtained during 4343 * handshake 4344 * @classifier_mask: params to be compared during processing 4345 */ 4346 struct dp_peer_mscs_parameter { 4347 uint8_t user_priority_bitmap; 4348 uint8_t user_priority_limit; 4349 uint8_t classifier_mask; 4350 }; 4351 #endif 4352 4353 #ifdef QCA_SUPPORT_WDS_EXTENDED 4354 #define WDS_EXT_PEER_INIT_BIT 0 4355 4356 /** 4357 * struct dp_wds_ext_peer - wds ext peer structure 4358 * This is used when wds extended feature is enabled 4359 * both compile time and run time. It is created 4360 * when 1st 4 address frame is received from 4361 * wds backhaul. 4362 * @osif_peer: Handle to the OS shim SW's virtual device 4363 * @init: wds ext netdev state 4364 */ 4365 struct dp_wds_ext_peer { 4366 ol_osif_peer_handle osif_peer; 4367 unsigned long init; 4368 }; 4369 #endif /* QCA_SUPPORT_WDS_EXTENDED */ 4370 4371 #ifdef WLAN_SUPPORT_MESH_LATENCY 4372 /*Advanced Mesh latency feature based macros */ 4373 4374 /** 4375 * struct dp_peer_mesh_latency_parameter - Mesh latency related 4376 * parameters. This data is updated per peer per TID based on 4377 * the flow tuple classification in external rule database 4378 * during packet processing. 4379 * @service_interval_dl: Service interval associated with TID in DL 4380 * @burst_size_dl: Burst size additive over multiple flows in DL 4381 * @service_interval_ul: Service interval associated with TID in UL 4382 * @burst_size_ul: Burst size additive over multiple flows in UL 4383 * @ac: custom ac derived from service interval 4384 * @msduq: MSDU queue number within TID 4385 */ 4386 struct dp_peer_mesh_latency_parameter { 4387 uint32_t service_interval_dl; 4388 uint32_t burst_size_dl; 4389 uint32_t service_interval_ul; 4390 uint32_t burst_size_ul; 4391 uint8_t ac; 4392 uint8_t msduq; 4393 }; 4394 #endif 4395 4396 #ifdef WLAN_FEATURE_11BE_MLO 4397 /* Max number of links for MLO connection */ 4398 #define DP_MAX_MLO_LINKS 4 4399 4400 /** 4401 * struct dp_peer_link_info - link peer information for MLO 4402 * @mac_addr: Mac address 4403 * @vdev_id: Vdev ID for current link peer 4404 * @is_valid: flag for link peer info valid or not 4405 * @chip_id: chip id 4406 */ 4407 struct dp_peer_link_info { 4408 union dp_align_mac_addr mac_addr; 4409 uint8_t vdev_id; 4410 uint8_t is_valid; 4411 uint8_t chip_id; 4412 }; 4413 4414 /** 4415 * struct dp_mld_link_peers - this structure is used to get link peers 4416 * pointer from mld peer 4417 * @link_peers: link peers pointer array 4418 * @num_links: number of link peers fetched 4419 */ 4420 struct dp_mld_link_peers { 4421 struct dp_peer *link_peers[DP_MAX_MLO_LINKS]; 4422 uint8_t num_links; 4423 }; 4424 #else 4425 #define DP_MAX_MLO_LINKS 0 4426 #endif 4427 4428 typedef void *dp_txrx_ref_handle; 4429 4430 /** 4431 * struct dp_peer_per_pkt_tx_stats- Peer Tx stats updated in per pkt 4432 * Tx completion path 4433 * @ucast: Unicast Packet Count 4434 * @mcast: Multicast Packet Count 4435 * @bcast: Broadcast Packet Count 4436 * @nawds_mcast: NAWDS Multicast Packet Count 4437 * @tx_success: Successful Tx Packets 4438 * @nawds_mcast_drop: NAWDS Multicast Drop Count 4439 * @ofdma: Total Packets as ofdma 4440 * @non_amsdu_cnt: Number of MSDUs with no MSDU level aggregation 4441 * @amsdu_cnt: Number of MSDUs part of AMSDU 4442 * @dropped: Dropped packet statistics 4443 * @dropped.fw_rem: Discarded by firmware 4444 * @dropped.fw_rem_notx: firmware_discard_untransmitted 4445 * @dropped.fw_rem_tx: firmware_discard_transmitted 4446 * @dropped.age_out: aged out in mpdu/msdu queues 4447 * @dropped.fw_reason1: discarded by firmware reason 1 4448 * @dropped.fw_reason2: discarded by firmware reason 2 4449 * @dropped.fw_reason3: discarded by firmware reason 3 4450 * @dropped.fw_rem_no_match: dropped due to fw no match command 4451 * @dropped.drop_threshold: dropped due to HW threshold 4452 * @dropped.drop_link_desc_na: dropped due resource not available in HW 4453 * @dropped.invalid_drop: Invalid msdu drop 4454 * @dropped.mcast_vdev_drop: MCAST drop configured for VDEV in HW 4455 * @dropped.invalid_rr: Invalid TQM release reason 4456 * @failed_retry_count: packets failed due to retry above 802.11 retry limit 4457 * @retry_count: packets successfully send after one or more retry 4458 * @multiple_retry_count: packets successfully sent after more than one retry 4459 * @no_ack_count: no ack pkt count for different protocols 4460 * @tx_success_twt: Successful Tx Packets in TWT session 4461 * @last_tx_ts: last timestamp in jiffies when tx comp occurred 4462 * @avg_sojourn_msdu: Avg sojourn msdu stat 4463 * @protocol_trace_cnt: per-peer protocol counter 4464 * @release_src_not_tqm: Counter to keep track of release source is not TQM 4465 * in TX completion status processing 4466 * @inval_link_id_pkt_cnt: Counter to capture Invalid Link Id 4467 */ 4468 struct dp_peer_per_pkt_tx_stats { 4469 struct cdp_pkt_info ucast; 4470 struct cdp_pkt_info mcast; 4471 struct cdp_pkt_info bcast; 4472 struct cdp_pkt_info nawds_mcast; 4473 struct cdp_pkt_info tx_success; 4474 uint32_t nawds_mcast_drop; 4475 uint32_t ofdma; 4476 uint32_t non_amsdu_cnt; 4477 uint32_t amsdu_cnt; 4478 struct { 4479 struct cdp_pkt_info fw_rem; 4480 uint32_t fw_rem_notx; 4481 uint32_t fw_rem_tx; 4482 uint32_t age_out; 4483 uint32_t fw_reason1; 4484 uint32_t fw_reason2; 4485 uint32_t fw_reason3; 4486 uint32_t fw_rem_queue_disable; 4487 uint32_t fw_rem_no_match; 4488 uint32_t drop_threshold; 4489 uint32_t drop_link_desc_na; 4490 uint32_t invalid_drop; 4491 uint32_t mcast_vdev_drop; 4492 uint32_t invalid_rr; 4493 } dropped; 4494 uint32_t failed_retry_count; 4495 uint32_t retry_count; 4496 uint32_t multiple_retry_count; 4497 uint32_t no_ack_count[QDF_PROTO_SUBTYPE_MAX]; 4498 struct cdp_pkt_info tx_success_twt; 4499 unsigned long last_tx_ts; 4500 qdf_ewma_tx_lag avg_sojourn_msdu[CDP_DATA_TID_MAX]; 4501 #ifdef VDEV_PEER_PROTOCOL_COUNT 4502 struct protocol_trace_count protocol_trace_cnt[CDP_TRACE_MAX]; 4503 #endif 4504 uint32_t release_src_not_tqm; 4505 uint32_t inval_link_id_pkt_cnt; 4506 }; 4507 4508 /** 4509 * struct dp_peer_extd_tx_stats - Peer Tx stats updated in either 4510 * per pkt Tx completion path when macro QCA_ENHANCED_STATS_SUPPORT is 4511 * disabled or in HTT Tx PPDU completion path when macro is enabled 4512 * @stbc: Packets in STBC 4513 * @ldpc: Packets in LDPC 4514 * @retries: Packet retries 4515 * @pkt_type: pkt count for different .11 modes 4516 * @wme_ac_type: Wireless Multimedia type Count 4517 * @excess_retries_per_ac: Wireless Multimedia type Count 4518 * @ampdu_cnt: completion of aggregation 4519 * @non_ampdu_cnt: tx completion not aggregated 4520 * @num_ppdu_cookie_valid: no. of valid ppdu cookies rcvd from FW 4521 * @tx_ppdus: ppdus in tx 4522 * @tx_mpdus_success: mpdus successful in tx 4523 * @tx_mpdus_tried: mpdus tried in tx 4524 * @tx_rate: Tx Rate in kbps 4525 * @last_tx_rate: Last tx rate for unicast packets 4526 * @last_tx_rate_mcs: Tx rate mcs for unicast packets 4527 * @mcast_last_tx_rate: Last tx rate for multicast packets 4528 * @mcast_last_tx_rate_mcs: Last tx rate mcs for multicast 4529 * @rnd_avg_tx_rate: Rounded average tx rate 4530 * @avg_tx_rate: Average TX rate 4531 * @tx_ratecode: Tx rate code of last frame 4532 * @pream_punct_cnt: Preamble Punctured count 4533 * @sgi_count: SGI count 4534 * @nss: Packet count for different num_spatial_stream values 4535 * @bw: Packet Count for different bandwidths 4536 * @ru_start: RU start index 4537 * @ru_tones: RU tones size 4538 * @ru_loc: pkt info for RU location 26/ 52/ 106/ 242/ 484 counter 4539 * @transmit_type: pkt info for tx transmit type 4540 * @mu_group_id: mumimo mu group id 4541 * @last_ack_rssi: RSSI of last acked packet 4542 * @nss_info: NSS 1,2, ...8 4543 * @mcs_info: MCS index 4544 * @bw_info: Bandwidth 4545 * <enum 0 bw_20_MHz> 4546 * <enum 1 bw_40_MHz> 4547 * <enum 2 bw_80_MHz> 4548 * <enum 3 bw_160_MHz> 4549 * @gi_info: <enum 0 0_8_us_sgi > Legacy normal GI 4550 * <enum 1 0_4_us_sgi > Legacy short GI 4551 * <enum 2 1_6_us_sgi > HE related GI 4552 * <enum 3 3_2_us_sgi > HE 4553 * @preamble_info: preamble 4554 * @tx_ucast_total: total ucast count 4555 * @tx_ucast_success: total ucast success count 4556 * @retries_mpdu: mpdu number of successfully transmitted after retries 4557 * @mpdu_success_with_retries: mpdu retry count in case of successful tx 4558 * @su_be_ppdu_cnt: SU Tx packet count for 11BE 4559 * @mu_be_ppdu_cnt: MU Tx packet count for 11BE 4560 * @punc_bw: MSDU count for punctured bw 4561 * @rts_success: RTS success count 4562 * @rts_failure: RTS failure count 4563 * @bar_cnt: Block ACK Request frame count 4564 * @ndpa_cnt: NDP announcement frame count 4565 * @rssi_chain: rssi chain 4566 * @wme_ac_type_bytes: Wireless Multimedia bytes Count 4567 */ 4568 struct dp_peer_extd_tx_stats { 4569 uint32_t stbc; 4570 uint32_t ldpc; 4571 uint32_t retries; 4572 struct cdp_pkt_type pkt_type[DOT11_MAX]; 4573 uint32_t wme_ac_type[WME_AC_MAX]; 4574 uint32_t excess_retries_per_ac[WME_AC_MAX]; 4575 uint32_t ampdu_cnt; 4576 uint32_t non_ampdu_cnt; 4577 uint32_t num_ppdu_cookie_valid; 4578 uint32_t tx_ppdus; 4579 uint32_t tx_mpdus_success; 4580 uint32_t tx_mpdus_tried; 4581 4582 uint32_t tx_rate; 4583 uint32_t last_tx_rate; 4584 uint32_t last_tx_rate_mcs; 4585 uint32_t mcast_last_tx_rate; 4586 uint32_t mcast_last_tx_rate_mcs; 4587 uint64_t rnd_avg_tx_rate; 4588 uint64_t avg_tx_rate; 4589 uint16_t tx_ratecode; 4590 4591 uint32_t sgi_count[MAX_GI]; 4592 uint32_t pream_punct_cnt; 4593 uint32_t nss[SS_COUNT]; 4594 uint32_t bw[MAX_BW]; 4595 uint32_t ru_start; 4596 uint32_t ru_tones; 4597 struct cdp_tx_pkt_info ru_loc[MAX_RU_LOCATIONS]; 4598 4599 struct cdp_tx_pkt_info transmit_type[MAX_TRANSMIT_TYPES]; 4600 uint32_t mu_group_id[MAX_MU_GROUP_ID]; 4601 4602 uint32_t last_ack_rssi; 4603 4604 uint32_t nss_info:4, 4605 mcs_info:4, 4606 bw_info:4, 4607 gi_info:4, 4608 preamble_info:4; 4609 4610 uint32_t retries_mpdu; 4611 uint32_t mpdu_success_with_retries; 4612 struct cdp_pkt_info tx_ucast_total; 4613 struct cdp_pkt_info tx_ucast_success; 4614 #ifdef WLAN_FEATURE_11BE 4615 struct cdp_pkt_type su_be_ppdu_cnt; 4616 struct cdp_pkt_type mu_be_ppdu_cnt[TXRX_TYPE_MU_MAX]; 4617 uint32_t punc_bw[MAX_PUNCTURED_MODE]; 4618 #endif 4619 uint32_t rts_success; 4620 uint32_t rts_failure; 4621 uint32_t bar_cnt; 4622 uint32_t ndpa_cnt; 4623 int32_t rssi_chain[CDP_RSSI_CHAIN_LEN]; 4624 uint64_t wme_ac_type_bytes[WME_AC_MAX]; 4625 }; 4626 4627 /** 4628 * struct dp_peer_per_pkt_rx_stats - Peer Rx stats updated in per pkt Rx path 4629 * @rcvd_reo: Packets received on the reo ring 4630 * @rx_lmac: Packets received on each lmac 4631 * @unicast: Total unicast packets 4632 * @multicast: Total multicast packets 4633 * @bcast: Broadcast Packet Count 4634 * @raw: Raw Pakets received 4635 * @nawds_mcast_drop: Total NAWDS multicast packets dropped 4636 * @mec_drop: Total MEC packets dropped 4637 * @ppeds_drop: Total DS packets dropped 4638 * @last_rx_ts: last timestamp in jiffies when RX happened 4639 * @intra_bss: Intra BSS statistics 4640 * @intra_bss.pkts: Intra BSS packets received 4641 * @intra_bss.fail: Intra BSS packets failed 4642 * @intra_bss.mdns_no_fws: Intra BSS MDNS packets not forwarded 4643 * @err: error counters 4644 * @err.mic_err: Rx MIC errors CCMP 4645 * @err.decrypt_err: Rx Decryption Errors CRC 4646 * @err.fcserr: rx MIC check failed (CCMP) 4647 * @err.pn_err: pn check failed 4648 * @err.oor_err: Rx OOR errors 4649 * @err.jump_2k_err: 2k jump errors 4650 * @err.rxdma_wifi_parse_err: rxdma wifi parse errors 4651 * @non_amsdu_cnt: Number of MSDUs with no MSDU level aggregation 4652 * @amsdu_cnt: Number of MSDUs part of AMSDU 4653 * @rx_retries: retries of packet in rx 4654 * @multipass_rx_pkt_drop: Dropped multipass rx pkt 4655 * @peer_unauth_rx_pkt_drop: Unauth rx packet drops 4656 * @policy_check_drop: policy check drops 4657 * @to_stack_twt: Total packets sent up the stack in TWT session 4658 * @rx_success: Total RX success count 4659 * @protocol_trace_cnt: per-peer protocol counters 4660 * @mcast_3addr_drop: 4661 * @rx_total: total rx count 4662 * @inval_link_id_pkt_cnt: Counter to capture Invalid Link Id 4663 */ 4664 struct dp_peer_per_pkt_rx_stats { 4665 struct cdp_pkt_info rcvd_reo[CDP_MAX_RX_RINGS]; 4666 struct cdp_pkt_info rx_lmac[CDP_MAX_LMACS]; 4667 struct cdp_pkt_info unicast; 4668 struct cdp_pkt_info multicast; 4669 struct cdp_pkt_info bcast; 4670 struct cdp_pkt_info raw; 4671 uint32_t nawds_mcast_drop; 4672 struct cdp_pkt_info mec_drop; 4673 struct cdp_pkt_info ppeds_drop; 4674 unsigned long last_rx_ts; 4675 struct { 4676 struct cdp_pkt_info pkts; 4677 struct cdp_pkt_info fail; 4678 uint32_t mdns_no_fwd; 4679 } intra_bss; 4680 struct { 4681 uint32_t mic_err; 4682 uint32_t decrypt_err; 4683 uint32_t fcserr; 4684 uint32_t pn_err; 4685 uint32_t oor_err; 4686 uint32_t jump_2k_err; 4687 uint32_t rxdma_wifi_parse_err; 4688 } err; 4689 uint32_t non_amsdu_cnt; 4690 uint32_t amsdu_cnt; 4691 uint32_t rx_retries; 4692 uint32_t multipass_rx_pkt_drop; 4693 uint32_t peer_unauth_rx_pkt_drop; 4694 uint32_t policy_check_drop; 4695 struct cdp_pkt_info to_stack_twt; 4696 struct cdp_pkt_info rx_success; 4697 #ifdef VDEV_PEER_PROTOCOL_COUNT 4698 struct protocol_trace_count protocol_trace_cnt[CDP_TRACE_MAX]; 4699 #endif 4700 uint32_t mcast_3addr_drop; 4701 #ifdef IPA_OFFLOAD 4702 struct cdp_pkt_info rx_total; 4703 #endif 4704 uint32_t inval_link_id_pkt_cnt; 4705 }; 4706 4707 /** 4708 * struct dp_peer_extd_rx_stats - Peer Rx stats updated in either 4709 * per pkt Rx path when macro QCA_ENHANCED_STATS_SUPPORT is disabled or in 4710 * Rx monitor patch when macro is enabled 4711 * @pkt_type: pkt counter for different .11 modes 4712 * @wme_ac_type: Wireless Multimedia type Count 4713 * @mpdu_cnt_fcs_ok: SU Rx success mpdu count 4714 * @mpdu_cnt_fcs_err: SU Rx fail mpdu count 4715 * @non_ampdu_cnt: Number of MSDUs with no MPDU level aggregation 4716 * @ampdu_cnt: Number of MSDUs part of AMSPU 4717 * @rx_mpdus: mpdu in rx 4718 * @rx_ppdus: ppdu in rx 4719 * @su_ax_ppdu_cnt: SU Rx packet count for .11ax 4720 * @rx_mu: Rx MU stats 4721 * @reception_type: Reception type of packets 4722 * @ppdu_cnt: PPDU packet count in reception type 4723 * @sgi_count: sgi count 4724 * @nss: packet count in spatiel Streams 4725 * @ppdu_nss: PPDU packet count in spatial streams 4726 * @bw: Packet Count in different bandwidths 4727 * @rx_mpdu_cnt: rx mpdu count per MCS rate 4728 * @rx_rate: Rx rate 4729 * @last_rx_rate: Previous rx rate 4730 * @rnd_avg_rx_rate: Rounded average rx rate 4731 * @avg_rx_rate: Average Rx rate 4732 * @rx_ratecode: Rx rate code of last frame 4733 * @avg_snr: Average snr 4734 * @rx_snr_measured_time: Time at which snr is measured 4735 * @snr: SNR of received signal 4736 * @last_snr: Previous snr 4737 * @nss_info: NSS 1,2, ...8 4738 * @mcs_info: MCS index 4739 * @bw_info: Bandwidth 4740 * <enum 0 bw_20_MHz> 4741 * <enum 1 bw_40_MHz> 4742 * <enum 2 bw_80_MHz> 4743 * <enum 3 bw_160_MHz> 4744 * @gi_info: <enum 0 0_8_us_sgi > Legacy normal GI 4745 * <enum 1 0_4_us_sgi > Legacy short GI 4746 * <enum 2 1_6_us_sgi > HE related GI 4747 * <enum 3 3_2_us_sgi > HE 4748 * @preamble_info: preamble 4749 * @mpdu_retry_cnt: retries of mpdu in rx 4750 * @su_be_ppdu_cnt: SU Rx packet count for BE 4751 * @mu_be_ppdu_cnt: MU rx packet count for BE 4752 * @punc_bw: MSDU count for punctured bw 4753 * @bar_cnt: Block ACK Request frame count 4754 * @ndpa_cnt: NDP announcement frame count 4755 * @wme_ac_type_bytes: Wireless Multimedia type Bytes Count 4756 */ 4757 struct dp_peer_extd_rx_stats { 4758 struct cdp_pkt_type pkt_type[DOT11_MAX]; 4759 uint32_t wme_ac_type[WME_AC_MAX]; 4760 uint32_t mpdu_cnt_fcs_ok; 4761 uint32_t mpdu_cnt_fcs_err; 4762 uint32_t non_ampdu_cnt; 4763 uint32_t ampdu_cnt; 4764 uint32_t rx_mpdus; 4765 uint32_t rx_ppdus; 4766 4767 struct cdp_pkt_type su_ax_ppdu_cnt; 4768 struct cdp_rx_mu rx_mu[TXRX_TYPE_MU_MAX]; 4769 uint32_t reception_type[MAX_RECEPTION_TYPES]; 4770 uint32_t ppdu_cnt[MAX_RECEPTION_TYPES]; 4771 4772 uint32_t sgi_count[MAX_GI]; 4773 uint32_t nss[SS_COUNT]; 4774 uint32_t ppdu_nss[SS_COUNT]; 4775 uint32_t bw[MAX_BW]; 4776 uint32_t rx_mpdu_cnt[MAX_MCS]; 4777 4778 uint32_t rx_rate; 4779 uint32_t last_rx_rate; 4780 uint32_t rnd_avg_rx_rate; 4781 uint32_t avg_rx_rate; 4782 uint32_t rx_ratecode; 4783 4784 uint32_t avg_snr; 4785 unsigned long rx_snr_measured_time; 4786 uint8_t snr; 4787 uint8_t last_snr; 4788 4789 uint32_t nss_info:4, 4790 mcs_info:4, 4791 bw_info:4, 4792 gi_info:4, 4793 preamble_info:4; 4794 4795 uint32_t mpdu_retry_cnt; 4796 #ifdef WLAN_FEATURE_11BE 4797 struct cdp_pkt_type su_be_ppdu_cnt; 4798 struct cdp_pkt_type mu_be_ppdu_cnt[TXRX_TYPE_MU_MAX]; 4799 uint32_t punc_bw[MAX_PUNCTURED_MODE]; 4800 #endif 4801 uint32_t bar_cnt; 4802 uint32_t ndpa_cnt; 4803 uint64_t wme_ac_type_bytes[WME_AC_MAX]; 4804 }; 4805 4806 /** 4807 * struct dp_peer_per_pkt_stats - Per pkt stats for peer 4808 * @tx: Per pkt Tx stats 4809 * @rx: Per pkt Rx stats 4810 */ 4811 struct dp_peer_per_pkt_stats { 4812 struct dp_peer_per_pkt_tx_stats tx; 4813 struct dp_peer_per_pkt_rx_stats rx; 4814 }; 4815 4816 /** 4817 * struct dp_peer_extd_stats - Stats from extended path for peer 4818 * @tx: Extended path tx stats 4819 * @rx: Extended path rx stats 4820 */ 4821 struct dp_peer_extd_stats { 4822 struct dp_peer_extd_tx_stats tx; 4823 struct dp_peer_extd_rx_stats rx; 4824 }; 4825 4826 /** 4827 * struct dp_peer_stats - Peer stats 4828 * @per_pkt_stats: Per packet path stats 4829 * @extd_stats: Extended path stats 4830 * @tx_latency: transmit latency stats 4831 */ 4832 struct dp_peer_stats { 4833 struct dp_peer_per_pkt_stats per_pkt_stats; 4834 #ifndef QCA_ENHANCED_STATS_SUPPORT 4835 struct dp_peer_extd_stats extd_stats; 4836 #endif 4837 #ifdef WLAN_FEATURE_TX_LATENCY_STATS 4838 struct dp_tx_latency tx_latency; 4839 #endif 4840 }; 4841 4842 /** 4843 * struct dp_txrx_peer: DP txrx_peer structure used in per pkt path 4844 * @vdev: VDEV to which this peer is associated 4845 * @peer_id: peer ID for this peer 4846 * @authorize: Set when authorized 4847 * @in_twt: in TWT session 4848 * @hw_txrx_stats_en: Indicate HW offload vdev stats 4849 * @is_mld_peer:1: MLD peer 4850 * @tx_failed: Total Tx failure 4851 * @comp_pkt: Pkt Info for which completions were received 4852 * @to_stack: Total packets sent up the stack 4853 * @delay_stats: Peer delay stats 4854 * @jitter_stats: Peer jitter stats 4855 * @security: Security credentials 4856 * @nawds_enabled: NAWDS flag 4857 * @bss_peer: set for bss peer 4858 * @isolation: enable peer isolation for this peer 4859 * @wds_enabled: WDS peer 4860 * @wds_ecm: 4861 * @flush_in_progress: 4862 * @bufq_info: 4863 * @mpass_peer_list_elem: node in the special peer list element 4864 * @vlan_id: vlan id for key 4865 * @wds_ext: 4866 * @osif_rx: 4867 * @rx_tid: 4868 * @sawf_stats: 4869 * @bw: bandwidth of peer connection 4870 * @mpdu_retry_threshold: MPDU retry threshold to increment tx bad count 4871 * @band: Link ID to band mapping 4872 * @stats_arr_size: peer stats array size 4873 * @stats: Peer link and mld statistics 4874 */ 4875 struct dp_txrx_peer { 4876 struct dp_vdev *vdev; 4877 uint16_t peer_id; 4878 uint8_t authorize:1, 4879 in_twt:1, 4880 hw_txrx_stats_en:1, 4881 is_mld_peer:1; 4882 uint32_t tx_failed; 4883 struct cdp_pkt_info comp_pkt; 4884 struct cdp_pkt_info to_stack; 4885 4886 struct dp_peer_delay_stats *delay_stats; 4887 4888 struct cdp_peer_tid_stats *jitter_stats; 4889 4890 struct { 4891 enum cdp_sec_type sec_type; 4892 u_int32_t michael_key[2]; /* relevant for TKIP */ 4893 } security[2]; /* 0 -> multicast, 1 -> unicast */ 4894 4895 uint16_t nawds_enabled:1, 4896 bss_peer:1, 4897 isolation:1, 4898 wds_enabled:1; 4899 #ifdef WDS_VENDOR_EXTENSION 4900 dp_ecm_policy wds_ecm; 4901 #endif 4902 #ifdef PEER_CACHE_RX_PKTS 4903 qdf_atomic_t flush_in_progress; 4904 struct dp_peer_cached_bufq bufq_info; 4905 #endif 4906 #ifdef QCA_MULTIPASS_SUPPORT 4907 TAILQ_ENTRY(dp_txrx_peer) mpass_peer_list_elem; 4908 uint16_t vlan_id; 4909 #endif 4910 #ifdef QCA_SUPPORT_WDS_EXTENDED 4911 struct dp_wds_ext_peer wds_ext; 4912 ol_txrx_rx_fp osif_rx; 4913 #endif 4914 struct dp_rx_tid_defrag rx_tid[DP_MAX_TIDS]; 4915 #ifdef CONFIG_SAWF 4916 struct dp_peer_sawf_stats *sawf_stats; 4917 #endif 4918 #ifdef DP_PEER_EXTENDED_API 4919 enum cdp_peer_bw bw; 4920 uint8_t mpdu_retry_threshold; 4921 #endif 4922 #if defined WLAN_FEATURE_11BE_MLO && defined DP_MLO_LINK_STATS_SUPPORT 4923 /* Link ID to band mapping, (1 MLD + DP_MAX_MLO_LINKS) */ 4924 uint8_t band[DP_MAX_MLO_LINKS + 1]; 4925 #endif 4926 uint8_t stats_arr_size; 4927 4928 /* dp_peer_stats should be the last member in the structure */ 4929 struct dp_peer_stats stats[]; 4930 }; 4931 4932 /* Peer structure for data path state */ 4933 struct dp_peer { 4934 struct dp_txrx_peer *txrx_peer; 4935 #ifdef WIFI_MONITOR_SUPPORT 4936 struct dp_mon_peer *monitor_peer; 4937 #endif 4938 /* peer ID for this peer */ 4939 uint16_t peer_id; 4940 4941 /* VDEV to which this peer is associated */ 4942 struct dp_vdev *vdev; 4943 4944 struct dp_ast_entry *self_ast_entry; 4945 4946 qdf_atomic_t ref_cnt; 4947 4948 union dp_align_mac_addr mac_addr; 4949 4950 /* node in the vdev's list of peers */ 4951 TAILQ_ENTRY(dp_peer) peer_list_elem; 4952 /* node in the hash table bin's list of peers */ 4953 TAILQ_ENTRY(dp_peer) hash_list_elem; 4954 4955 /* TID structures pointer */ 4956 struct dp_rx_tid *rx_tid; 4957 4958 /* TBD: No transmit TID state required? */ 4959 4960 struct { 4961 enum cdp_sec_type sec_type; 4962 u_int32_t michael_key[2]; /* relevant for TKIP */ 4963 } security[2]; /* 0 -> multicast, 1 -> unicast */ 4964 4965 /* NAWDS Flag and Bss Peer bit */ 4966 uint16_t bss_peer:1, /* set for bss peer */ 4967 authorize:1, /* Set when authorized */ 4968 valid:1, /* valid bit */ 4969 delete_in_progress:1, /* Indicate kickout sent */ 4970 sta_self_peer:1, /* Indicate STA self peer */ 4971 is_tdls_peer:1; /* Indicate TDLS peer */ 4972 4973 #ifdef WLAN_FEATURE_11BE_MLO 4974 uint8_t first_link:1, /* first link peer for MLO */ 4975 primary_link:1; /* primary link for MLO */ 4976 #endif 4977 4978 /* MCL specific peer local id */ 4979 uint16_t local_id; 4980 enum ol_txrx_peer_state state; 4981 qdf_spinlock_t peer_info_lock; 4982 4983 /* Peer calibrated stats */ 4984 struct cdp_calibr_stats stats; 4985 4986 TAILQ_HEAD(, dp_ast_entry) ast_entry_list; 4987 /* TBD */ 4988 4989 /* Active Block ack sessions */ 4990 uint16_t active_ba_session_cnt; 4991 4992 /* Current HW buffersize setting */ 4993 uint16_t hw_buffer_size; 4994 4995 /* 4996 * Flag to check if sessions with 256 buffersize 4997 * should be terminated. 4998 */ 4999 uint8_t kill_256_sessions; 5000 qdf_atomic_t is_default_route_set; 5001 5002 #ifdef QCA_PEER_MULTIQ_SUPPORT 5003 struct dp_peer_ast_params peer_ast_flowq_idx[DP_PEER_AST_FLOWQ_MAX]; 5004 #endif 5005 /* entry to inactive_list*/ 5006 TAILQ_ENTRY(dp_peer) inactive_list_elem; 5007 5008 qdf_atomic_t mod_refs[DP_MOD_ID_MAX]; 5009 5010 uint8_t peer_state; 5011 qdf_spinlock_t peer_state_lock; 5012 #ifdef WLAN_SUPPORT_MSCS 5013 struct dp_peer_mscs_parameter mscs_ipv4_parameter, mscs_ipv6_parameter; 5014 bool mscs_active; 5015 #endif 5016 #ifdef WLAN_SUPPORT_MESH_LATENCY 5017 struct dp_peer_mesh_latency_parameter mesh_latency_params[DP_MAX_TIDS]; 5018 #endif 5019 #ifdef WLAN_FEATURE_11BE_MLO 5020 /* peer type */ 5021 enum cdp_peer_type peer_type; 5022 /*---------for link peer---------*/ 5023 struct dp_peer *mld_peer; 5024 5025 /*Link ID of link peer*/ 5026 uint8_t link_id; 5027 bool link_id_valid; 5028 5029 /*---------for mld peer----------*/ 5030 struct dp_peer_link_info link_peers[DP_MAX_MLO_LINKS]; 5031 uint8_t num_links; 5032 DP_MUTEX_TYPE link_peers_info_lock; 5033 #endif 5034 #ifdef CONFIG_SAWF_DEF_QUEUES 5035 struct dp_peer_sawf *sawf; 5036 #endif 5037 /* AST hash index for peer in HW */ 5038 uint16_t ast_idx; 5039 5040 /* AST hash value for peer in HW */ 5041 uint16_t ast_hash; 5042 5043 /* Peer Frequency */ 5044 uint32_t freq; 5045 }; 5046 5047 /** 5048 * struct dp_invalid_peer_msg - Invalid peer message 5049 * @nbuf: data buffer 5050 * @wh: 802.11 header 5051 * @vdev_id: id of vdev 5052 */ 5053 struct dp_invalid_peer_msg { 5054 qdf_nbuf_t nbuf; 5055 struct ieee80211_frame *wh; 5056 uint8_t vdev_id; 5057 }; 5058 5059 /** 5060 * struct dp_tx_me_buf_t - ME buffer 5061 * @next: pointer to next buffer 5062 * @data: Destination Mac address 5063 * @paddr_macbuf: physical address for dest_mac 5064 */ 5065 struct dp_tx_me_buf_t { 5066 /* Note: ME buf pool initialization logic expects next pointer to 5067 * be the first element. Dont add anything before next */ 5068 struct dp_tx_me_buf_t *next; 5069 uint8_t data[QDF_MAC_ADDR_SIZE]; 5070 qdf_dma_addr_t paddr_macbuf; 5071 }; 5072 5073 #if defined(WLAN_SUPPORT_RX_FLOW_TAG) || defined(WLAN_SUPPORT_RX_FISA) 5074 struct hal_rx_fst; 5075 #endif /* WLAN_SUPPORT_RX_FLOW_TAG || WLAN_SUPPORT_RX_FISA */ 5076 5077 #ifdef WLAN_SUPPORT_RX_FLOW_TAG 5078 struct dp_rx_fse { 5079 /* HAL Rx Flow Search Entry which matches HW definition */ 5080 void *hal_rx_fse; 5081 /* Toeplitz hash value */ 5082 uint32_t flow_hash; 5083 /* Flow index, equivalent to hash value truncated to FST size */ 5084 uint32_t flow_id; 5085 /* Stats tracking for this flow */ 5086 struct cdp_flow_stats stats; 5087 /* Flag indicating whether flow is IPv4 address tuple */ 5088 uint8_t is_ipv4_addr_entry; 5089 /* Flag indicating whether flow is valid */ 5090 uint8_t is_valid; 5091 }; 5092 5093 struct dp_rx_fst { 5094 /* Software (DP) FST */ 5095 uint8_t *base; 5096 /* Pointer to HAL FST */ 5097 struct hal_rx_fst *hal_rx_fst; 5098 /* Base physical address of HAL RX HW FST */ 5099 uint64_t hal_rx_fst_base_paddr; 5100 /* Maximum number of flows FSE supports */ 5101 uint16_t max_entries; 5102 /* Num entries in flow table */ 5103 uint16_t num_entries; 5104 /* SKID Length */ 5105 uint16_t max_skid_length; 5106 /* Hash mask to obtain legitimate hash entry */ 5107 uint32_t hash_mask; 5108 /* Timer for bundling of flows */ 5109 qdf_timer_t cache_invalidate_timer; 5110 /** 5111 * Flag which tracks whether cache update 5112 * is needed on timer expiry 5113 */ 5114 qdf_atomic_t is_cache_update_pending; 5115 /* Flag to indicate completion of FSE setup in HW/FW */ 5116 bool fse_setup_done; 5117 /* Last ring id used to add a flow */ 5118 uint8_t ring_id; 5119 }; 5120 5121 #define DP_RX_GET_SW_FT_ENTRY_SIZE sizeof(struct dp_rx_fse) 5122 5123 #endif /* WLAN_SUPPORT_RX_FLOW_TAG */ 5124 5125 #ifdef WLAN_FEATURE_STATS_EXT 5126 /** 5127 * struct dp_req_rx_hw_stats_t - RX peer HW stats query structure 5128 * @pending_tid_stats_cnt: pending tid stats count which waits for REO status 5129 * @is_query_timeout: flag to show is stats query timeout 5130 */ 5131 struct dp_req_rx_hw_stats_t { 5132 qdf_atomic_t pending_tid_stats_cnt; 5133 bool is_query_timeout; 5134 }; 5135 #endif 5136 /* soc level structure to declare arch specific ops for DP */ 5137 5138 #ifndef WLAN_SOFTUMAC_SUPPORT 5139 /** 5140 * dp_hw_link_desc_pool_banks_free() - Free h/w link desc pool banks 5141 * @soc: DP SOC handle 5142 * @mac_id: mac id 5143 * 5144 * Return: none 5145 */ 5146 void dp_hw_link_desc_pool_banks_free(struct dp_soc *soc, uint32_t mac_id); 5147 5148 /** 5149 * dp_hw_link_desc_pool_banks_alloc() - Allocate h/w link desc pool banks 5150 * @soc: DP SOC handle 5151 * @mac_id: mac id 5152 * 5153 * Allocates memory pages for link descriptors, the page size is 4K for 5154 * MCL and 2MB for WIN. if the mac_id is invalid link descriptor pages are 5155 * allocated for regular RX/TX and if the there is a proper mac_id link 5156 * descriptors are allocated for RX monitor mode. 5157 * 5158 * Return: QDF_STATUS_SUCCESS: Success 5159 * QDF_STATUS_E_FAILURE: Failure 5160 */ 5161 QDF_STATUS dp_hw_link_desc_pool_banks_alloc(struct dp_soc *soc, 5162 uint32_t mac_id); 5163 #else 5164 static inline void dp_hw_link_desc_pool_banks_free(struct dp_soc *soc, 5165 uint32_t mac_id) 5166 { 5167 } 5168 5169 static inline QDF_STATUS dp_hw_link_desc_pool_banks_alloc(struct dp_soc *soc, 5170 uint32_t mac_id) 5171 { 5172 return QDF_STATUS_SUCCESS; 5173 } 5174 #endif 5175 5176 /** 5177 * dp_link_desc_ring_replenish() - Replenish hw link desc rings 5178 * @soc: DP SOC handle 5179 * @mac_id: mac id 5180 * 5181 * Return: None 5182 */ 5183 void dp_link_desc_ring_replenish(struct dp_soc *soc, uint32_t mac_id); 5184 5185 #ifdef WLAN_FEATURE_RX_PREALLOC_BUFFER_POOL 5186 void dp_rx_refill_buff_pool_enqueue(struct dp_soc *soc); 5187 #else 5188 static inline void dp_rx_refill_buff_pool_enqueue(struct dp_soc *soc) {} 5189 #endif 5190 5191 /** 5192 * dp_srng_alloc() - Allocate memory for SRNG 5193 * @soc : Data path soc handle 5194 * @srng : SRNG pointer 5195 * @ring_type : Ring Type 5196 * @num_entries: Number of entries 5197 * @cached: cached flag variable 5198 * 5199 * Return: QDF_STATUS 5200 */ 5201 QDF_STATUS dp_srng_alloc(struct dp_soc *soc, struct dp_srng *srng, 5202 int ring_type, uint32_t num_entries, 5203 bool cached); 5204 5205 /** 5206 * dp_srng_free() - Free SRNG memory 5207 * @soc: Data path soc handle 5208 * @srng: SRNG pointer 5209 * 5210 * Return: None 5211 */ 5212 void dp_srng_free(struct dp_soc *soc, struct dp_srng *srng); 5213 5214 /** 5215 * dp_srng_init() - Initialize SRNG 5216 * @soc : Data path soc handle 5217 * @srng : SRNG pointer 5218 * @ring_type : Ring Type 5219 * @ring_num: Ring number 5220 * @mac_id: mac_id 5221 * 5222 * Return: QDF_STATUS 5223 */ 5224 QDF_STATUS dp_srng_init(struct dp_soc *soc, struct dp_srng *srng, 5225 int ring_type, int ring_num, int mac_id); 5226 5227 /** 5228 * dp_srng_init_idx() - Initialize SRNG 5229 * @soc : Data path soc handle 5230 * @srng : SRNG pointer 5231 * @ring_type : Ring Type 5232 * @ring_num: Ring number 5233 * @mac_id: mac_id 5234 * @idx: ring index 5235 * 5236 * Return: QDF_STATUS 5237 */ 5238 QDF_STATUS dp_srng_init_idx(struct dp_soc *soc, struct dp_srng *srng, 5239 int ring_type, int ring_num, int mac_id, 5240 uint32_t idx); 5241 5242 /** 5243 * dp_srng_deinit() - Internal function to deinit SRNG rings used by data path 5244 * @soc: DP SOC handle 5245 * @srng: source ring structure 5246 * @ring_type: type of ring 5247 * @ring_num: ring number 5248 * 5249 * Return: None 5250 */ 5251 void dp_srng_deinit(struct dp_soc *soc, struct dp_srng *srng, 5252 int ring_type, int ring_num); 5253 5254 void dp_print_peer_txrx_stats_be(struct cdp_peer_stats *peer_stats, 5255 enum peer_stats_type stats_type); 5256 void dp_print_peer_txrx_stats_li(struct cdp_peer_stats *peer_stats, 5257 enum peer_stats_type stats_type); 5258 5259 void dp_print_peer_txrx_stats_rh(struct cdp_peer_stats *peer_stats, 5260 enum peer_stats_type stats_type); 5261 5262 /** 5263 * dp_should_timer_irq_yield() - Decide if the bottom half should yield 5264 * @soc: DP soc handle 5265 * @work_done: work done in softirq context 5266 * @start_time: start time for the softirq 5267 * 5268 * Return: enum with yield code 5269 */ 5270 enum timer_yield_status 5271 dp_should_timer_irq_yield(struct dp_soc *soc, uint32_t work_done, 5272 uint64_t start_time); 5273 5274 /** 5275 * dp_vdev_get_default_reo_hash() - get reo dest ring and hash values for a vdev 5276 * @vdev: Datapath VDEV handle 5277 * @reo_dest: pointer to default reo_dest ring for vdev to be populated 5278 * @hash_based: pointer to hash value (enabled/disabled) to be populated 5279 * 5280 * Return: None 5281 */ 5282 void dp_vdev_get_default_reo_hash(struct dp_vdev *vdev, 5283 enum cdp_host_reo_dest_ring *reo_dest, 5284 bool *hash_based); 5285 5286 /** 5287 * dp_reo_remap_config() - configure reo remap register value based 5288 * nss configuration. 5289 * @soc: DP soc handle 5290 * @remap0: output parameter indicates reo remap 0 register value 5291 * @remap1: output parameter indicates reo remap 1 register value 5292 * @remap2: output parameter indicates reo remap 2 register value 5293 * 5294 * based on offload_radio value below remap configuration 5295 * get applied. 5296 * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4) 5297 * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4) 5298 * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4) 5299 * 3 - both Radios handled by NSS (remap not required) 5300 * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3) 5301 * 5302 * Return: bool type, true if remap is configured else false. 5303 */ 5304 5305 bool dp_reo_remap_config(struct dp_soc *soc, uint32_t *remap0, 5306 uint32_t *remap1, uint32_t *remap2); 5307 5308 #ifdef QCA_DP_TX_HW_SW_NBUF_DESC_PREFETCH 5309 /** 5310 * dp_tx_comp_get_prefetched_params_from_hal_desc() - Get prefetched TX desc 5311 * @soc: DP soc handle 5312 * @tx_comp_hal_desc: HAL TX Comp Descriptor 5313 * @r_tx_desc: SW Tx Descriptor retrieved from HAL desc. 5314 * 5315 * Return: None 5316 */ 5317 void dp_tx_comp_get_prefetched_params_from_hal_desc( 5318 struct dp_soc *soc, 5319 void *tx_comp_hal_desc, 5320 struct dp_tx_desc_s **r_tx_desc); 5321 #endif 5322 #endif /* _DP_TYPES_H_ */ 5323