1 /* 2 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HAL_BE_API_MON_H_ 19 #define _HAL_BE_API_MON_H_ 20 21 #include "hal_be_hw_headers.h" 22 #if defined(WLAN_PKT_CAPTURE_TX_2_0) || \ 23 defined(WLAN_PKT_CAPTURE_RX_2_0) 24 #include <mon_ingress_ring.h> 25 #include <mon_destination_ring.h> 26 #include <mon_drop.h> 27 #endif 28 #include <hal_be_hw_headers.h> 29 #include "hal_api_mon.h" 30 #include <hal_generic_api.h> 31 #include <hal_generic_api.h> 32 #include <hal_api_mon.h> 33 34 #if defined(WLAN_PKT_CAPTURE_TX_2_0) || \ 35 defined(WLAN_PKT_CAPTURE_RX_2_0) || \ 36 defined(QCA_SINGLE_WIFI_3_0) 37 #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000 38 #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0 39 #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff 40 41 #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004 42 #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0 43 #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff 44 45 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 46 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 47 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 48 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 49 50 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c 51 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 52 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 53 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 54 55 #define HAL_MON_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 56 ((*(((unsigned int *) buff_addr_info) + \ 57 (HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 58 ((paddr_lo) << HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \ 59 HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK) 60 61 #define HAL_MON_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 62 ((*(((unsigned int *) buff_addr_info) + \ 63 (HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 64 ((paddr_hi) << HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \ 65 HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) 66 67 #define HAL_MON_VADDR_LO_SET(buff_addr_info, vaddr_lo) \ 68 ((*(((unsigned int *) buff_addr_info) + \ 69 (HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET >> 2))) = \ 70 ((vaddr_lo) << HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB) & \ 71 HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK) 72 73 #define HAL_MON_VADDR_HI_SET(buff_addr_info, vaddr_hi) \ 74 ((*(((unsigned int *) buff_addr_info) + \ 75 (HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET >> 2))) = \ 76 ((vaddr_hi) << HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB) & \ 77 HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK) 78 #endif 79 80 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 81 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 82 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 83 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 84 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 85 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 86 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 87 PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 88 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 89 PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 90 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 91 PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 92 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 93 PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 94 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 95 PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 96 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 97 PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 98 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 99 PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 100 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 101 PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 102 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 103 PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 104 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 105 PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 106 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 107 PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 108 109 110 #define RX_MON_MPDU_START_WMASK 0x07F0 111 #define RX_MON_MPDU_END_WMASK 0x7 112 #define RX_MON_MPDU_START_WMASK_V2 0x007F0 113 #define RX_MON_MPDU_END_WMASK_V2 0xFF 114 #define RX_MON_MSDU_END_WMASK 0x0AE1 115 #define RX_MON_PPDU_END_USR_STATS_WMASK 0xB7E 116 117 #ifdef CONFIG_MON_WORD_BASED_TLV 118 #ifndef BIG_ENDIAN_HOST 119 struct rx_mpdu_start_mon_data { 120 uint32_t peer_meta_data : 32; 121 uint32_t rxpcu_mpdu_filter_in_category : 2, 122 sw_frame_group_id : 7, 123 ndp_frame : 1, 124 phy_err : 1, 125 phy_err_during_mpdu_header : 1, 126 protocol_version_err : 1, 127 ast_based_lookup_valid : 1, 128 reserved_0a : 2, 129 phy_ppdu_id : 16; 130 uint32_t ast_index : 16, 131 sw_peer_id : 16; 132 uint32_t mpdu_frame_control_valid : 1, 133 mpdu_duration_valid : 1, 134 mac_addr_ad1_valid : 1, 135 mac_addr_ad2_valid : 1, 136 mac_addr_ad3_valid : 1, 137 mac_addr_ad4_valid : 1, 138 mpdu_sequence_control_valid : 1, 139 mpdu_qos_control_valid : 1, 140 mpdu_ht_control_valid : 1, 141 frame_encryption_info_valid : 1, 142 mpdu_fragment_number : 4, 143 more_fragment_flag : 1, 144 reserved_11a : 1, 145 fr_ds : 1, 146 to_ds : 1, 147 encrypted : 1, 148 mpdu_retry : 1, 149 mpdu_sequence_number : 12; 150 uint32_t key_id_octet : 8, 151 new_peer_entry : 1, 152 decrypt_needed : 1, 153 decap_type : 2, 154 rx_insert_vlan_c_tag_padding : 1, 155 rx_insert_vlan_s_tag_padding : 1, 156 strip_vlan_c_tag_decap : 1, 157 strip_vlan_s_tag_decap : 1, 158 pre_delim_count : 12, 159 ampdu_flag : 1, 160 bar_frame : 1, 161 raw_mpdu : 1, 162 reserved_12 : 1; 163 uint32_t mpdu_length : 14, 164 first_mpdu : 1, 165 mcast_bcast : 1, 166 ast_index_not_found : 1, 167 ast_index_timeout : 1, 168 power_mgmt : 1, 169 non_qos : 1, 170 null_data : 1, 171 mgmt_type : 1, 172 ctrl_type : 1, 173 more_data : 1, 174 eosp : 1, 175 fragment_flag : 1, 176 order : 1, 177 u_apsd_trigger : 1, 178 encrypt_required : 1, 179 directed : 1, 180 amsdu_present : 1, 181 reserved_13 : 1; 182 uint32_t mpdu_frame_control_field : 16, 183 mpdu_duration_field : 16; 184 uint32_t mac_addr_ad1_31_0 : 32; 185 uint32_t mac_addr_ad1_47_32 : 16, 186 mac_addr_ad2_15_0 : 16; 187 uint32_t mac_addr_ad2_47_16 : 32; 188 uint32_t mac_addr_ad3_31_0 : 32; 189 uint32_t mac_addr_ad3_47_32 : 16, 190 mpdu_sequence_control_field : 16; 191 uint32_t mac_addr_ad4_31_0 : 32; 192 uint32_t mac_addr_ad4_47_32 : 16, 193 mpdu_qos_control_field : 16; 194 }; 195 196 struct rx_msdu_end_mon_data { 197 uint32_t rxpcu_mpdu_filter_in_category : 2, 198 sw_frame_group_id : 7, 199 reserved_0 : 7, 200 phy_ppdu_id : 16; 201 uint32_t ip_hdr_chksum : 16, 202 reported_mpdu_length : 14, 203 reserved_1a : 2; 204 uint32_t sa_sw_peer_id : 16, 205 sa_idx_timeout : 1, 206 da_idx_timeout : 1, 207 to_ds : 1, 208 tid : 4, 209 sa_is_valid : 1, 210 da_is_valid : 1, 211 da_is_mcbc : 1, 212 l3_header_padding : 2, 213 first_msdu : 1, 214 last_msdu : 1, 215 fr_ds : 1, 216 ip_chksum_fail_copy : 1; 217 uint32_t sa_idx : 16, 218 da_idx_or_sw_peer_id : 16; 219 uint32_t msdu_drop : 1, 220 reo_destination_indication : 5, 221 flow_idx : 20, 222 use_ppe : 1, 223 mesh_sta : 2, 224 vlan_ctag_stripped : 1, 225 vlan_stag_stripped : 1, 226 fragment_flag : 1; 227 uint32_t fse_metadata : 32; 228 uint32_t cce_metadata : 16, 229 tcp_udp_chksum : 16; 230 uint32_t aggregation_count : 8, 231 flow_aggregation_continuation : 1, 232 fisa_timeout : 1, 233 tcp_udp_chksum_fail_copy : 1, 234 msdu_limit_error : 1, 235 flow_idx_timeout : 1, 236 flow_idx_invalid : 1, 237 cce_match : 1, 238 amsdu_parser_error : 1, 239 cumulative_ip_length : 16; 240 uint32_t msdu_length : 14, 241 stbc : 1, 242 ipsec_esp : 1, 243 l3_offset : 7, 244 ipsec_ah : 1, 245 l4_offset : 8; 246 uint32_t msdu_number : 8, 247 decap_format : 2, 248 ipv4_proto : 1, 249 ipv6_proto : 1, 250 tcp_proto : 1, 251 udp_proto : 1, 252 ip_frag : 1, 253 tcp_only_ack : 1, 254 da_is_bcast_mcast : 1, 255 toeplitz_hash_sel : 2, 256 ip_fixed_header_valid : 1, 257 ip_extn_header_valid : 1, 258 tcp_udp_header_valid : 1, 259 mesh_control_present : 1, 260 ldpc : 1, 261 ip4_protocol_ip6_next_header : 8; 262 uint32_t user_rssi : 8, 263 pkt_type : 4, 264 sgi : 2, 265 rate_mcs : 4, 266 receive_bandwidth : 3, 267 reception_type : 3, 268 mimo_ss_bitmap : 7, 269 msdu_done_copy : 1; 270 uint32_t flow_id_toeplitz : 32; 271 }; 272 273 struct rx_ppdu_end_user_mon_data { 274 uint32_t sw_peer_id : 16, 275 mpdu_cnt_fcs_err : 11, 276 sw2rxdma0_buf_source_used : 1, 277 fw2rxdma_pmac0_buf_source_used : 1, 278 sw2rxdma1_buf_source_used : 1, 279 sw2rxdma_exception_buf_source_used: 1, 280 fw2rxdma_pmac1_buf_source_used : 1; 281 uint32_t mpdu_cnt_fcs_ok : 11, 282 frame_control_info_valid : 1, 283 qos_control_info_valid : 1, 284 ht_control_info_valid : 1, 285 data_sequence_control_info_valid : 1, 286 ht_control_info_null_valid : 1, 287 rxdma2fw_pmac1_ring_used : 1, 288 rxdma2reo_ring_used : 1, 289 rxdma2fw_pmac0_ring_used : 1, 290 rxdma2sw_ring_used : 1, 291 rxdma_release_ring_used : 1, 292 ht_control_field_pkt_type : 4, 293 rxdma2reo_remote0_ring_used : 1, 294 rxdma2reo_remote1_ring_used : 1, 295 reserved_3b : 5; 296 uint32_t ast_index : 16, 297 frame_control_field : 16; 298 uint32_t first_data_seq_ctrl : 16, 299 qos_control_field : 16; 300 uint32_t ht_control_field : 32; 301 uint32_t fcs_ok_bitmap_31_0 : 32; 302 uint32_t fcs_ok_bitmap_63_32 : 32; 303 uint32_t udp_msdu_count : 16, 304 tcp_msdu_count : 16; 305 uint32_t other_msdu_count : 16, 306 tcp_ack_msdu_count : 16; 307 uint32_t sw_response_reference_ptr : 32; 308 uint32_t received_qos_data_tid_bitmap : 16, 309 received_qos_data_tid_eosp_bitmap : 16; 310 uint32_t qosctrl_15_8_tid0 : 8, 311 qosctrl_15_8_tid1 : 8, 312 qosctrl_15_8_tid2 : 8, 313 qosctrl_15_8_tid3 : 8; 314 uint32_t qosctrl_15_8_tid12 : 8, 315 qosctrl_15_8_tid13 : 8, 316 qosctrl_15_8_tid14 : 8, 317 qosctrl_15_8_tid15 : 8; 318 uint32_t mpdu_ok_byte_count : 25, 319 ampdu_delim_ok_count_6_0 : 7; 320 uint32_t ampdu_delim_err_count : 25, 321 ampdu_delim_ok_count_13_7 : 7; 322 uint32_t mpdu_err_byte_count : 25, 323 ampdu_delim_ok_count_20_14 : 7; 324 uint32_t sw_response_reference_ptr_ext : 32; 325 uint32_t corrupted_due_to_fifo_delay : 1, 326 frame_control_info_null_valid : 1, 327 frame_control_field_null : 16, 328 retried_mpdu_count : 11, 329 reserved_23a : 3; 330 }; 331 #else 332 struct rx_mpdu_start_mon_data { 333 uint32_t peer_meta_data : 32; 334 uint32_t phy_ppdu_id : 16, 335 reserved_0a : 2, 336 ast_based_lookup_valid : 1, 337 protocol_version_err : 1, 338 phy_err_during_mpdu_header : 1, 339 phy_err : 1, 340 ndp_frame : 1, 341 sw_frame_group_id : 7, 342 rxpcu_mpdu_filter_in_category : 2; 343 uint32_t sw_peer_id : 16, 344 ast_index : 16; 345 uint32_t mpdu_sequence_number : 12, 346 mpdu_retry : 1, 347 encrypted : 1, 348 to_ds : 1, 349 fr_ds : 1, 350 reserved_11a : 1, 351 more_fragment_flag : 1, 352 mpdu_fragment_number : 4, 353 frame_encryption_info_valid : 1, 354 mpdu_ht_control_valid : 1, 355 mpdu_qos_control_valid : 1, 356 mpdu_sequence_control_valid : 1, 357 mac_addr_ad4_valid : 1, 358 mac_addr_ad3_valid : 1, 359 mac_addr_ad2_valid : 1, 360 mac_addr_ad1_valid : 1, 361 mpdu_duration_valid : 1, 362 mpdu_frame_control_valid : 1; 363 uint32_t reserved_12 : 1, 364 raw_mpdu : 1, 365 bar_frame : 1, 366 ampdu_flag : 1, 367 pre_delim_count : 12, 368 strip_vlan_s_tag_decap : 1, 369 strip_vlan_c_tag_decap : 1, 370 rx_insert_vlan_s_tag_padding : 1, 371 rx_insert_vlan_c_tag_padding : 1, 372 decap_type : 2, 373 decrypt_needed : 1, 374 new_peer_entry : 1, 375 key_id_octet : 8; 376 uint32_t reserved_13 : 1, 377 amsdu_present : 1, 378 directed : 1, 379 encrypt_required : 1, 380 u_apsd_trigger : 1, 381 order : 1, 382 fragment_flag : 1, 383 eosp : 1, 384 more_data : 1, 385 ctrl_type : 1, 386 mgmt_type : 1, 387 null_data : 1, 388 non_qos : 1, 389 power_mgmt : 1, 390 ast_index_timeout : 1, 391 ast_index_not_found : 1, 392 mcast_bcast : 1, 393 first_mpdu : 1, 394 mpdu_length : 14; 395 uint32_t mpdu_duration_field : 16, 396 mpdu_frame_control_field : 16; 397 uint32_t mac_addr_ad1_31_0 : 32; 398 uint32_t mac_addr_ad2_15_0 : 16, 399 mac_addr_ad1_47_32 : 16; 400 uint32_t mac_addr_ad2_47_16 : 32; 401 uint32_t mac_addr_ad3_31_0 : 32; 402 uint32_t mpdu_sequence_control_field : 16, 403 mac_addr_ad3_47_32 : 16; 404 uint32_t mac_addr_ad4_31_0 : 32; 405 uint32_t mpdu_qos_control_field : 16, 406 mac_addr_ad4_47_32 : 16; 407 }; 408 409 struct rx_msdu_end_mon_data { 410 uint32_t phy_ppdu_id : 16, 411 reserved_0 : 7, 412 sw_frame_group_id : 7, 413 rxpcu_mpdu_filter_in_category : 2; 414 uint32_t reserved_1a : 2, 415 reported_mpdu_length : 14, 416 ip_hdr_chksum : 16; 417 uint32_t ip_chksum_fail_copy : 1, 418 fr_ds : 1, 419 last_msdu : 1, 420 first_msdu : 1, 421 l3_header_padding : 2, 422 da_is_mcbc : 1, 423 da_is_valid : 1, 424 sa_is_valid : 1, 425 tid : 4, 426 to_ds : 1, 427 da_idx_timeout : 1, 428 sa_idx_timeout : 1, 429 sa_sw_peer_id : 16; 430 uint32_t da_idx_or_sw_peer_id : 16, 431 sa_idx : 16; 432 uint32_t fragment_flag : 1, 433 vlan_stag_stripped : 1, 434 vlan_ctag_stripped : 1, 435 mesh_sta : 2, 436 use_ppe : 1, 437 flow_idx : 20, 438 reo_destination_indication : 5, 439 msdu_drop : 1; 440 uint32_t fse_metadata : 32; 441 uint32_t cce_metadata : 16, 442 tcp_udp_chksum : 16; 443 uint32_t cumulative_ip_length : 16, 444 amsdu_parser_error : 1, 445 cce_match : 1, 446 flow_idx_invalid : 1, 447 flow_idx_timeout : 1, 448 msdu_limit_error : 1, 449 tcp_udp_chksum_fail_copy : 1, 450 fisa_timeout : 1, 451 flow_aggregation_continuation : 1, 452 aggregation_count : 8; 453 uint32_t l4_offset : 8, 454 ipsec_ah : 1, 455 l3_offset : 7, 456 ipsec_esp : 1, 457 stbc : 1, 458 msdu_length : 14; 459 uint32_t ip4_protocol_ip6_next_header : 8, 460 ldpc : 1, 461 mesh_control_present : 1, 462 tcp_udp_header_valid : 1, 463 ip_extn_header_valid : 1, 464 ip_fixed_header_valid : 1, 465 toeplitz_hash_sel : 2, 466 da_is_bcast_mcast : 1, 467 tcp_only_ack : 1, 468 ip_frag : 1, 469 udp_proto : 1, 470 tcp_proto : 1, 471 ipv6_proto : 1, 472 ipv4_proto : 1, 473 decap_format : 2, 474 msdu_number : 8; 475 uint32_t msdu_done_copy : 1, 476 mimo_ss_bitmap : 7, 477 reception_type : 3, 478 receive_bandwidth : 3, 479 rate_mcs : 4, 480 sgi : 2, 481 pkt_type : 4, 482 user_rssi : 8; 483 uint32_t flow_id_toeplitz : 32; 484 }; 485 486 struct rx_ppdu_end_user_mon_data { 487 uint32_t fw2rxdma_pmac1_buf_source_used : 1, 488 sw2rxdma_exception_buf_source_used: 1, 489 sw2rxdma1_buf_source_used : 1, 490 fw2rxdma_pmac0_buf_source_used : 1, 491 sw2rxdma0_buf_source_used : 1, 492 mpdu_cnt_fcs_err : 11, 493 sw_peer_id : 16; 494 uint32_t reserved_3b : 5, 495 rxdma2reo_remote1_ring_used : 1, 496 rxdma2reo_remote0_ring_used : 1, 497 ht_control_field_pkt_type : 4, 498 rxdma_release_ring_used : 1, 499 rxdma2sw_ring_used : 1, 500 rxdma2fw_pmac0_ring_used : 1, 501 rxdma2reo_ring_used : 1, 502 rxdma2fw_pmac1_ring_used : 1, 503 ht_control_info_null_valid : 1, 504 data_sequence_control_info_valid : 1, 505 ht_control_info_valid : 1, 506 qos_control_info_valid : 1, 507 frame_control_info_valid : 1, 508 mpdu_cnt_fcs_ok : 11; 509 uint32_t frame_control_field : 16, 510 ast_index : 16; 511 uint32_t qos_control_field : 16, 512 first_data_seq_ctrl : 16; 513 uint32_t ht_control_field : 32; 514 uint32_t fcs_ok_bitmap_31_0 : 32; 515 uint32_t fcs_ok_bitmap_63_32 : 32; 516 uint32_t tcp_msdu_count : 16, 517 udp_msdu_count : 16; 518 uint32_t tcp_ack_msdu_count : 16, 519 other_msdu_count : 16; 520 uint32_t sw_response_reference_ptr : 32; 521 uint32_t received_qos_data_tid_eosp_bitmap : 16, 522 received_qos_data_tid_bitmap : 16; 523 uint32_t qosctrl_15_8_tid3 : 8, 524 qosctrl_15_8_tid2 : 8, 525 qosctrl_15_8_tid1 : 8, 526 qosctrl_15_8_tid0 : 8; 527 uint32_t qosctrl_15_8_tid15 : 8, 528 qosctrl_15_8_tid14 : 8, 529 qosctrl_15_8_tid13 : 8, 530 qosctrl_15_8_tid12 : 8; 531 uint32_t ampdu_delim_ok_count_6_0 : 7, 532 mpdu_ok_byte_count : 25; 533 uint32_t ampdu_delim_ok_count_13_7 : 7, 534 ampdu_delim_err_count : 25; 535 uint32_t ampdu_delim_ok_count_20_14 : 7, 536 mpdu_err_byte_count : 25; 537 uint32_t sw_response_reference_ptr_ext : 32; 538 uint32_t reserved_23a : 3, 539 retried_mpdu_count : 11, 540 frame_control_field_null : 16, 541 frame_control_info_null_valid : 1, 542 corrupted_due_to_fifo_delay : 1; 543 }; 544 #endif 545 546 struct rx_mpdu_start_mon_data_t { 547 struct rx_mpdu_start_mon_data rx_mpdu_info_details; 548 }; 549 550 struct rx_msdu_end_mon_data_t { 551 struct rx_msdu_end_mon_data rx_mpdu_info_details; 552 }; 553 /* TLV struct for word based Tlv */ 554 typedef struct rx_mpdu_start_mon_data_t hal_rx_mon_mpdu_start_t; 555 typedef struct rx_msdu_end_mon_data hal_rx_mon_msdu_end_t; 556 typedef struct rx_ppdu_end_user_mon_data hal_rx_mon_ppdu_end_user_t; 557 558 #else 559 560 typedef struct rx_mpdu_start hal_rx_mon_mpdu_start_t; 561 typedef struct rx_msdu_end hal_rx_mon_msdu_end_t; 562 typedef struct rx_ppdu_end_user_stats hal_rx_mon_ppdu_end_user_t; 563 #endif 564 565 /* 566 * struct mon_destination_drop - monitor drop descriptor 567 * 568 * @ppdu_drop_cnt: PPDU drop count 569 * @mpdu_drop_cnt: MPDU drop count 570 * @tlv_drop_cnt: TLV drop count 571 * @end_of_ppdu_seen: end of ppdu seen 572 * @reserved_0a: rsvd 573 * @reserved_1a: rsvd 574 * @ppdu_id: PPDU ID 575 * @reserved_3a: rsvd 576 * @initiator: initiator ppdu 577 * @empty_descriptor: empty descriptor 578 * @ring_id: ring id 579 * @looping_count: looping count 580 */ 581 struct mon_destination_drop { 582 uint32_t ppdu_drop_cnt : 10, 583 mpdu_drop_cnt : 10, 584 tlv_drop_cnt : 10, 585 end_of_ppdu_seen : 1, 586 reserved_0a : 1; 587 uint32_t reserved_1a : 32; 588 uint32_t ppdu_id : 32; 589 uint32_t reserved_3a : 18, 590 initiator : 1, 591 empty_descriptor : 1, 592 ring_id : 8, 593 looping_count : 4; 594 }; 595 596 #define HAL_MON_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 597 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 598 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET)), \ 599 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK, \ 600 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB)) 601 602 #define HAL_MON_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 603 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 604 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET)), \ 605 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK, \ 606 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB)) 607 608 /** 609 * struct hal_rx_status_buffer_done - status buffer done tlv 610 * placeholder structure 611 * 612 * @ppdu_start_offset: ppdu start 613 * @first_ppdu_start_user_info_offset: 614 * @mult_ppdu_start_user_info: 615 * @end_offset: 616 * @ppdu_end_detected: 617 * @flush_detected: 618 * @rsvd: 619 */ 620 struct hal_rx_status_buffer_done { 621 uint32_t ppdu_start_offset : 3, 622 first_ppdu_start_user_info_offset : 6, 623 mult_ppdu_start_user_info : 1, 624 end_offset : 13, 625 ppdu_end_detected : 1, 626 flush_detected : 1, 627 rsvd : 7; 628 }; 629 630 /** 631 * enum hal_mon_status_end_reason - ppdu status buffer end reason 632 * 633 * @HAL_MON_STATUS_BUFFER_FULL: status buffer full 634 * @HAL_MON_FLUSH_DETECTED: flush detected 635 * @HAL_MON_END_OF_PPDU: end of ppdu detected 636 * @HAL_MON_PPDU_TRUNCATED: truncated ppdu status 637 */ 638 enum hal_mon_status_end_reason { 639 HAL_MON_STATUS_BUFFER_FULL, 640 HAL_MON_FLUSH_DETECTED, 641 HAL_MON_END_OF_PPDU, 642 HAL_MON_PPDU_TRUNCATED, 643 }; 644 645 /** 646 * struct hal_mon_desc - HAL Monitor descriptor 647 * 648 * @buf_addr: virtual buffer address 649 * @ppdu_id: ppdu id 650 * - TxMon fills scheduler id 651 * - RxMON fills phy_ppdu_id 652 * @end_offset: offset (units in 4 bytes) where status buffer ended 653 * i.e offset of TLV + last TLV size 654 * @reserved_3a: reserved bits 655 * @end_reason: ppdu end reason 656 * 0 - status buffer is full 657 * 1 - flush detected 658 * 2 - TX_FES_STATUS_END or RX_PPDU_END 659 * 3 - PPDU truncated due to system error 660 * @initiator: 1 - descriptor belongs to TX FES 661 * 0 - descriptor belongs to TX RESPONSE 662 * @empty_descriptor: 0 - this descriptor is written on a flush 663 * or end of ppdu or end of status buffer 664 * 1 - descriptor provided to indicate drop 665 * @ring_id: ring id for debugging 666 * @looping_count: count to indicate number of times producer 667 * of entries has looped around the ring 668 * @flush_detected: if flush detected 669 * @end_of_ppdu_dropped: if end_of_ppdu is dropped 670 * @ppdu_drop_count: PPDU drop count 671 * @mpdu_drop_count: MPDU drop count 672 * @tlv_drop_count: TLV drop count 673 */ 674 struct hal_mon_desc { 675 uint64_t buf_addr; 676 uint32_t ppdu_id; 677 uint32_t end_offset:12, 678 reserved_3a:4, 679 end_reason:2, 680 initiator:1, 681 empty_descriptor:1, 682 ring_id:8, 683 looping_count:4; 684 uint16_t flush_detected:1, 685 end_of_ppdu_dropped:1; 686 uint32_t ppdu_drop_count; 687 uint32_t mpdu_drop_count; 688 uint32_t tlv_drop_count; 689 }; 690 691 typedef struct hal_mon_desc *hal_mon_desc_t; 692 693 /** 694 * struct hal_mon_buf_addr_status - HAL buffer address tlv get status 695 * 696 * @buffer_virt_addr_31_0: Lower 32 bits of virtual address of status buffer 697 * @buffer_virt_addr_63_32: Upper 32 bits of virtual address of status buffer 698 * @dma_length: DMA length 699 * @reserved_2a: reserved bits 700 * @msdu_continuation: is msdu size more than fragment size 701 * @truncated: is msdu got truncated 702 * @reserved_2b: reserved bits 703 * @tlv64_padding: tlv paddding 704 */ 705 struct hal_mon_buf_addr_status { 706 uint32_t buffer_virt_addr_31_0; 707 uint32_t buffer_virt_addr_63_32; 708 uint32_t dma_length:12, 709 reserved_2a:4, 710 msdu_continuation:1, 711 truncated:1, 712 reserved_2b:14; 713 uint32_t tlv64_padding; 714 }; 715 716 #if defined(WLAN_PKT_CAPTURE_TX_2_0) || \ 717 defined(WLAN_PKT_CAPTURE_RX_2_0) 718 719 /** 720 * hal_be_get_mon_dest_status() - Get monitor descriptor status 721 * @hal_soc: HAL Soc handle 722 * @hw_desc: HAL monitor descriptor 723 * @status: pointer to write descriptor status 724 * 725 * Return: none 726 */ 727 static inline void 728 hal_be_get_mon_dest_status(hal_soc_handle_t hal_soc, 729 void *hw_desc, 730 struct hal_mon_desc *status) 731 { 732 struct mon_destination_ring *desc = hw_desc; 733 734 status->empty_descriptor = desc->empty_descriptor; 735 if (status->empty_descriptor) { 736 struct mon_destination_drop *drop_desc = hw_desc; 737 738 status->buf_addr = 0; 739 status->ppdu_drop_count = drop_desc->ppdu_drop_cnt; 740 status->mpdu_drop_count = drop_desc->mpdu_drop_cnt; 741 status->tlv_drop_count = drop_desc->tlv_drop_cnt; 742 status->end_of_ppdu_dropped = drop_desc->end_of_ppdu_seen; 743 } else { 744 status->buf_addr = HAL_RX_GET(desc, MON_DESTINATION_RING_STAT,BUF_VIRT_ADDR_31_0) | 745 (((uint64_t)HAL_RX_GET(desc, 746 MON_DESTINATION_RING_STAT, 747 BUF_VIRT_ADDR_63_32)) << 32); 748 status->end_reason = desc->end_reason; 749 status->end_offset = desc->end_offset; 750 } 751 status->ppdu_id = desc->ppdu_id; 752 status->initiator = desc->initiator; 753 status->looping_count = desc->looping_count; 754 } 755 #endif 756 757 #if defined(RX_PPDU_END_USER_STATS_OFDMA_INFO_VALID_OFFSET) && \ 758 defined(RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET) 759 760 static inline void 761 hal_rx_handle_mu_ul_info(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user, 762 struct mon_rx_user_status *mon_rx_user_status) 763 { 764 mon_rx_user_status->mu_ul_user_v0_word0 = 765 rx_ppdu_end_user->sw_response_reference_ptr; 766 767 mon_rx_user_status->mu_ul_user_v0_word1 = 768 rx_ppdu_end_user->sw_response_reference_ptr_ext; 769 } 770 #else 771 static inline void 772 hal_rx_handle_mu_ul_info(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user, 773 struct mon_rx_user_status *mon_rx_user_status) 774 { 775 } 776 #endif 777 778 static inline void 779 hal_rx_populate_byte_count(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user, 780 void *ppduinfo, 781 struct mon_rx_user_status *mon_rx_user_status) 782 { 783 mon_rx_user_status->mpdu_ok_byte_count = 784 rx_ppdu_end_user->mpdu_ok_byte_count; 785 mon_rx_user_status->mpdu_err_byte_count = 786 rx_ppdu_end_user->mpdu_err_byte_count; 787 } 788 789 static inline void 790 hal_rx_populate_mu_user_info(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user, 791 void *ppduinfo, uint32_t user_id, 792 struct mon_rx_user_status *mon_rx_user_status) 793 { 794 struct mon_rx_info *mon_rx_info; 795 struct mon_rx_user_info *mon_rx_user_info; 796 struct hal_rx_ppdu_info *ppdu_info = 797 (struct hal_rx_ppdu_info *)ppduinfo; 798 799 mon_rx_info = &ppdu_info->rx_info; 800 mon_rx_user_info = &ppdu_info->rx_user_info[user_id]; 801 mon_rx_user_info->qos_control_info_valid = 802 mon_rx_info->qos_control_info_valid; 803 mon_rx_user_info->qos_control = mon_rx_info->qos_control; 804 805 mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index; 806 mon_rx_user_status->tid = ppdu_info->rx_status.tid; 807 mon_rx_user_status->tcp_msdu_count = 808 ppdu_info->rx_status.tcp_msdu_count; 809 mon_rx_user_status->udp_msdu_count = 810 ppdu_info->rx_status.udp_msdu_count; 811 mon_rx_user_status->other_msdu_count = 812 ppdu_info->rx_status.other_msdu_count; 813 mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control; 814 mon_rx_user_status->frame_control_info_valid = 815 ppdu_info->rx_status.frame_control_info_valid; 816 mon_rx_user_status->data_sequence_control_info_valid = 817 ppdu_info->rx_status.data_sequence_control_info_valid; 818 mon_rx_user_status->first_data_seq_ctrl = 819 ppdu_info->rx_status.first_data_seq_ctrl; 820 mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type; 821 mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags; 822 mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags; 823 mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags; 824 if (mon_rx_user_status->vht_flags) { 825 mon_rx_user_status->vht_flag_values2 = 826 ppdu_info->rx_status.vht_flag_values2; 827 qdf_mem_copy(mon_rx_user_status->vht_flag_values3, 828 ppdu_info->rx_status.vht_flag_values3, 829 sizeof(mon_rx_user_status->vht_flag_values3)); 830 mon_rx_user_status->vht_flag_values4 = 831 ppdu_info->rx_status.vht_flag_values4; 832 mon_rx_user_status->vht_flag_values5 = 833 ppdu_info->rx_status.vht_flag_values5; 834 mon_rx_user_status->vht_flag_values6 = 835 ppdu_info->rx_status.vht_flag_values6; 836 } 837 mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags; 838 mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags; 839 840 mon_rx_user_status->mpdu_cnt_fcs_ok = 841 ppdu_info->com_info.mpdu_cnt_fcs_ok; 842 mon_rx_user_status->mpdu_cnt_fcs_err = 843 ppdu_info->com_info.mpdu_cnt_fcs_err; 844 qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap, 845 &ppdu_info->com_info.mpdu_fcs_ok_bitmap, 846 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 847 sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0])); 848 mon_rx_user_status->retry_mpdu = 849 ppdu_info->rx_status.mpdu_retry_cnt; 850 hal_rx_populate_byte_count(rx_ppdu_end_user, ppdu_info, 851 mon_rx_user_status); 852 } 853 854 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, \ 855 ppdu_info, rssi_info_tlv) \ 856 { \ 857 ppdu_info->rx_status.rssi_chain[chain][0] = \ 858 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 859 RSSI_PRI20_CHAIN##chain); \ 860 ppdu_info->rx_status.rssi_chain[chain][1] = \ 861 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 862 RSSI_EXT20_CHAIN##chain); \ 863 ppdu_info->rx_status.rssi_chain[chain][2] = \ 864 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 865 RSSI_EXT40_LOW20_CHAIN##chain); \ 866 ppdu_info->rx_status.rssi_chain[chain][3] = \ 867 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 868 RSSI_EXT40_HIGH20_CHAIN##chain); \ 869 } \ 870 871 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ 872 {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, ppdu_info, rssi_info_tlv) \ 873 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, ppdu_info, rssi_info_tlv) \ 874 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, ppdu_info, rssi_info_tlv) \ 875 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, ppdu_info, rssi_info_tlv) \ 876 } \ 877 878 static inline uint32_t 879 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, 880 uint8_t *rssi_info_tlv) 881 { 882 HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) 883 return 0; 884 } 885 886 #ifdef WLAN_TX_PKT_CAPTURE_ENH 887 static inline void 888 hal_get_qos_control(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user, 889 struct hal_rx_ppdu_info *ppdu_info) 890 { 891 ppdu_info->rx_info.qos_control_info_valid = 892 rx_ppdu_end_user->qos_control_info_valid; 893 894 if (ppdu_info->rx_info.qos_control_info_valid) 895 ppdu_info->rx_info.qos_control = 896 rx_ppdu_end_user->qos_control_field; 897 } 898 899 static inline void 900 hal_get_mac_addr1(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 901 struct hal_rx_ppdu_info *ppdu_info) 902 { 903 if ((ppdu_info->sw_frame_group_id 904 == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) || 905 (ppdu_info->sw_frame_group_id == 906 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) { 907 ppdu_info->rx_info.mac_addr1_valid = 908 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_valid; 909 910 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] = 911 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_31_0; 912 if (ppdu_info->sw_frame_group_id == 913 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) { 914 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] = 915 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_47_32; 916 } 917 } 918 } 919 #else 920 static inline void 921 hal_get_qos_control(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user, 922 struct hal_rx_ppdu_info *ppdu_info) 923 { 924 } 925 926 static inline void 927 hal_get_mac_addr1(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 928 struct hal_rx_ppdu_info *ppdu_info) 929 { 930 } 931 #endif 932 933 #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS 934 static inline void 935 hal_update_frame_type_cnt(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 936 struct hal_rx_ppdu_info *ppdu_info) 937 { 938 uint16_t frame_ctrl; 939 uint8_t fc_type; 940 941 if (rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_valid) { 942 frame_ctrl = rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_field; 943 fc_type = HAL_RX_GET_FRAME_CTRL_TYPE(frame_ctrl); 944 if (fc_type == HAL_RX_FRAME_CTRL_TYPE_MGMT) 945 ppdu_info->frm_type_info.rx_mgmt_cnt++; 946 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_CTRL) 947 ppdu_info->frm_type_info.rx_ctrl_cnt++; 948 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_DATA) 949 ppdu_info->frm_type_info.rx_data_cnt++; 950 } 951 } 952 #else 953 static inline void 954 hal_update_frame_type_cnt(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 955 struct hal_rx_ppdu_info *ppdu_info) 956 { 957 } 958 #endif 959 960 #if defined(WLAN_PKT_CAPTURE_TX_2_0) || \ 961 defined(WLAN_PKT_CAPTURE_RX_2_0) 962 /** 963 * hal_mon_buff_addr_info_set() - set desc address in cookie 964 * @hal_soc_hdl: HAL Soc handle 965 * @mon_entry: monitor srng 966 * @mon_desc_addr: HAL monitor descriptor virtual address 967 * @phy_addr: HAL monitor descriptor physical address 968 * 969 * Return: none 970 */ 971 static inline 972 void hal_mon_buff_addr_info_set(hal_soc_handle_t hal_soc_hdl, 973 void *mon_entry, 974 unsigned long long mon_desc_addr, 975 qdf_dma_addr_t phy_addr) 976 { 977 uint32_t paddr_lo = ((uintptr_t)phy_addr & 0x00000000ffffffff); 978 uint32_t paddr_hi = ((uintptr_t)phy_addr & 0xffffffff00000000) >> 32; 979 uint32_t vaddr_lo = ((unsigned long long)mon_desc_addr & 0x00000000ffffffff); 980 uint32_t vaddr_hi = ((unsigned long long)mon_desc_addr & 0xffffffff00000000) >> 32; 981 982 HAL_MON_PADDR_LO_SET(mon_entry, paddr_lo); 983 HAL_MON_PADDR_HI_SET(mon_entry, paddr_hi); 984 HAL_MON_VADDR_LO_SET(mon_entry, vaddr_lo); 985 HAL_MON_VADDR_HI_SET(mon_entry, vaddr_hi); 986 } 987 #endif 988 989 #ifdef WLAN_PKT_CAPTURE_TX_2_0 990 991 /* TX monitor */ 992 #define TX_MON_STATUS_BUF_SIZE 2048 993 994 #define HAL_INVALID_PPDU_ID 0xFFFFFFFF 995 996 #define HAL_MAX_DL_MU_USERS 37 997 #define HAL_MAX_RU_INDEX 7 998 999 enum hal_tx_tlv_status { 1000 HAL_MON_TX_FES_SETUP, 1001 HAL_MON_TX_FES_STATUS_END, 1002 HAL_MON_RX_RESPONSE_REQUIRED_INFO, 1003 HAL_MON_RESPONSE_END_STATUS_INFO, 1004 1005 HAL_MON_TX_PCU_PPDU_SETUP_INIT, 1006 1007 HAL_MON_TX_MPDU_START, 1008 HAL_MON_TX_MSDU_START, 1009 HAL_MON_TX_BUFFER_ADDR, 1010 HAL_MON_TX_DATA, 1011 1012 HAL_MON_TX_FES_STATUS_START, 1013 1014 HAL_MON_TX_FES_STATUS_PROT, 1015 HAL_MON_TX_FES_STATUS_START_PROT, 1016 1017 HAL_MON_TX_FES_STATUS_START_PPDU, 1018 HAL_MON_TX_FES_STATUS_USER_PPDU, 1019 HAL_MON_TX_QUEUE_EXTENSION, 1020 1021 HAL_MON_RX_FRAME_BITMAP_ACK, 1022 HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_256, 1023 HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_1K, 1024 HAL_MON_COEX_TX_STATUS, 1025 1026 HAL_MON_MACTX_HE_SIG_A_SU, 1027 HAL_MON_MACTX_HE_SIG_A_MU_DL, 1028 HAL_MON_MACTX_HE_SIG_B1_MU, 1029 HAL_MON_MACTX_HE_SIG_B2_MU, 1030 HAL_MON_MACTX_HE_SIG_B2_OFDMA, 1031 HAL_MON_MACTX_L_SIG_A, 1032 HAL_MON_MACTX_L_SIG_B, 1033 HAL_MON_MACTX_HT_SIG, 1034 HAL_MON_MACTX_VHT_SIG_A, 1035 1036 HAL_MON_MACTX_USER_DESC_PER_USER, 1037 HAL_MON_MACTX_USER_DESC_COMMON, 1038 HAL_MON_MACTX_PHY_DESC, 1039 1040 HAL_MON_TX_FW2SW, 1041 HAL_MON_TX_STATUS_PPDU_NOT_DONE, 1042 }; 1043 1044 enum txmon_coex_tx_status_reason { 1045 COEX_FES_TX_START, 1046 COEX_FES_TX_END, 1047 COEX_FES_END, 1048 COEX_RESPONSE_TX_START, 1049 COEX_RESPONSE_TX_END, 1050 COEX_NO_TX_ONGOING, 1051 }; 1052 1053 enum txmon_transmission_type { 1054 TXMON_SU_TRANSMISSION = 0, 1055 TXMON_MU_TRANSMISSION, 1056 TXMON_MU_SU_TRANSMISSION, 1057 TXMON_MU_MIMO_TRANSMISSION = 1, 1058 TXMON_MU_OFDMA_TRANMISSION 1059 }; 1060 1061 enum txmon_he_ppdu_subtype { 1062 TXMON_HE_SUBTYPE_SU = 0, 1063 TXMON_HE_SUBTYPE_TRIG, 1064 TXMON_HE_SUBTYPE_MU, 1065 TXMON_HE_SUBTYPE_EXT_SU 1066 }; 1067 1068 enum txmon_pkt_type { 1069 TXMON_PKT_TYPE_11A = 0, 1070 TXMON_PKT_TYPE_11B, 1071 TXMON_PKT_TYPE_11N_MM, 1072 TXMON_PKT_TYPE_11AC, 1073 TXMON_PKT_TYPE_11AX, 1074 TXMON_PKT_TYPE_11BA, 1075 TXMON_PKT_TYPE_11BE, 1076 TXMON_PKT_TYPE_11AZ 1077 }; 1078 1079 enum txmon_generated_response { 1080 TXMON_GEN_RESP_SELFGEN_ACK = 0, 1081 TXMON_GEN_RESP_SELFGEN_CTS, 1082 TXMON_GEN_RESP_SELFGEN_BA, 1083 TXMON_GEN_RESP_SELFGEN_MBA, 1084 TXMON_GEN_RESP_SELFGEN_CBF, 1085 TXMON_GEN_RESP_SELFGEN_TRIG, 1086 TXMON_GEN_RESP_SELFGEN_NDP_LMR 1087 }; 1088 1089 #ifdef MONITOR_TLV_RECORDING_ENABLE 1090 1091 /* 1092 * Please make sure that the maximum total size of fields in each TLV 1093 * is 22 bits. 1094 * 10 bits are reserved for tlv_tag 1095 */ 1096 struct hal_ppdu_start_tlv_record { 1097 uint32_t ppdu_id:10; 1098 }; 1099 1100 struct hal_ppdu_start_user_info_tlv_record { 1101 uint32_t user_id:6, 1102 rate_mcs:4, 1103 nss:3, 1104 reception_type:3, 1105 sgi:2; 1106 }; 1107 1108 struct hal_mpdu_start_tlv_record { 1109 uint32_t user_id:6, 1110 wrap_flag:1; 1111 }; 1112 1113 struct hal_mpdu_end_tlv_record { 1114 uint32_t user_id:6, 1115 fcs_err:1, 1116 wrap_flag:1; 1117 }; 1118 1119 struct hal_header_tlv_record { 1120 uint32_t wrap_flag:1; 1121 }; 1122 1123 struct hal_msdu_end_tlv_record { 1124 uint32_t user_id:6, 1125 msdu_num:8, 1126 tid:4, 1127 tcp_proto:1, 1128 udp_proto:1, 1129 wrap_flag:1; 1130 }; 1131 1132 struct hal_mon_buffer_addr_tlv_record { 1133 uint32_t dma_length:12, 1134 truncation:1, 1135 continuation:1, 1136 wrap_flag:1; 1137 }; 1138 1139 struct hal_phy_location_tlv_record { 1140 uint32_t rtt_cfr_status:8, 1141 rtt_num_streams:8, 1142 rx_location_info_valid:1; 1143 }; 1144 1145 struct hal_ppdu_end_user_stats_tlv_record { 1146 uint32_t ast_index:16, 1147 pkt_type:4; 1148 }; 1149 1150 struct hal_pcu_ppdu_end_info_tlv_record { 1151 uint32_t dialog_topken:8, 1152 bb_captured_reason:3, 1153 bb_captured_channel:1, 1154 bb_captured_timeout:1, 1155 mpdu_delimiter_error_seen:1; 1156 }; 1157 1158 struct hal_phy_rx_ht_sig_tlv_record { 1159 uint32_t crc:8, 1160 mcs:7, 1161 stbc:2, 1162 aggregation:1, 1163 short_gi:1, 1164 fes_coding:1, 1165 cbw:1; 1166 }; 1167 1168 /* Tx TLVs - structs of Tx TLV with fields to be added here*/ 1169 1170 /* 1171 * enum hal_ppdu_tlv_category - Categories of TLV 1172 * @PPDU_START: PPDU start level TLV 1173 * @MPDU: MPDU level TLV 1174 * @PPDU_END: PPDU end level TLV 1175 * 1176 */ 1177 enum hal_ppdu_tlv_category { 1178 CATEGORY_PPDU_START = 1, 1179 CATEGORY_MPDU, 1180 CATEGORY_PPDU_END 1181 }; 1182 #endif 1183 1184 /** 1185 * struct hal_txmon_user_desc_per_user - user desc per user information 1186 * @psdu_length: PSDU length of the user in octet 1187 * @ru_start_index: RU number to which user is assigned 1188 * @ru_size: Size of the RU for that user 1189 * @ofdma_mu_mimo_enabled: mu mimo transmission within the RU 1190 * @nss: Number of spatial stream occupied by the user 1191 * @stream_offset: Stream Offset from which the User occupies the Streams 1192 * @mcs: Modulation Coding Scheme for the User 1193 * @dcm: Indicates whether dual sub-carrier modulation is applied 1194 * @fec_type: Indicates whether it is BCC or LDPC 1195 * @user_bf_type: user beamforming type 1196 * @drop_user_cbf: frame dropped because of CBF FCS failure 1197 * @ldpc_extra_symbol: LDPC encoding process 1198 * @force_extra_symbol: force an extra OFDM symbol 1199 * @reserved: reserved 1200 * @sw_peer_id: user sw peer id 1201 * @per_user_subband_mask: Per user sub band mask 1202 */ 1203 struct hal_txmon_user_desc_per_user { 1204 uint32_t psdu_length; 1205 uint32_t ru_start_index :8, 1206 ru_size :4, 1207 ofdma_mu_mimo_enabled :1, 1208 nss :3, 1209 stream_offset :3, 1210 mcs :4, 1211 dcm :1, 1212 fec_type :1, 1213 user_bf_type :2, 1214 drop_user_cbf :1, 1215 ldpc_extra_symbol :1, 1216 force_extra_symbol :1, 1217 reserved :2; 1218 uint32_t sw_peer_id :16, 1219 per_user_subband_mask :16; 1220 }; 1221 1222 /** 1223 * struct hal_txmon_usr_desc_common - user desc common information 1224 * @num_users: Number of users 1225 * @ltf_size: LTF size 1226 * @pkt_extn_pe: packet extension duration of the trigger-based PPDU 1227 * @a_factor: packet extension duration of the trigger-based PPDU 1228 * @center_ru_0: Center RU is occupied in the lower 80 MHz band 1229 * @center_ru_1: Center RU is occupied in the upper 80 MHz band 1230 * @num_ltf_symbols: number of LTF symbols 1231 * @doppler_indication: doppler indication 1232 * @reserved: reserved 1233 * @spatial_reuse: spatial reuse 1234 * @ru_channel_0: RU arrangement for band 0 1235 * @ru_channel_1: RU arrangement for band 1 1236 */ 1237 struct hal_txmon_usr_desc_common { 1238 uint32_t num_users :6, 1239 ltf_size :2, 1240 pkt_extn_pe :1, 1241 a_factor :2, 1242 center_ru_0 :1, 1243 center_ru_1 :1, 1244 num_ltf_symbols :16, 1245 doppler_indication :1, 1246 reserved :2; 1247 uint16_t spatial_reuse; 1248 uint16_t ru_channel_0[8]; 1249 uint16_t ru_channel_1[8]; 1250 }; 1251 1252 #define IS_MULTI_USERS(num_users) (!!(0xFFFE & num_users)) 1253 1254 #define TXMON_HAL(hal_tx_ppdu_info, field) \ 1255 hal_tx_ppdu_info->field 1256 #define TXMON_HAL_STATUS(hal_tx_ppdu_info, field) \ 1257 hal_tx_ppdu_info->rx_status.field 1258 #define TXMON_HAL_USER(hal_tx_ppdu_info, user_id, field) \ 1259 hal_tx_ppdu_info->rx_user_status[user_id].field 1260 1261 #define TXMON_STATUS_INFO(hal_tx_status_info, field) \ 1262 hal_tx_status_info->field 1263 1264 #ifdef MONITOR_TLV_RECORDING_ENABLE 1265 struct hal_tx_tlv_info { 1266 uint32_t tlv_tag; 1267 uint8_t tlv_category; 1268 uint8_t is_data_ppdu_info; 1269 }; 1270 #endif 1271 1272 /** 1273 * struct hal_tx_status_info - status info that wasn't populated in rx_status 1274 * @reception_type: su or uplink mu reception type 1275 * @transmission_type: su or mu transmission type 1276 * @medium_prot_type: medium protection type 1277 * @generated_response: Generated frame in response window 1278 * @band_center_freq1: 1279 * @band_center_freq2: 1280 * @freq: 1281 * @phy_mode: 1282 * @schedule_id: 1283 * @no_bitmap_avail: Bitmap available flag 1284 * @explicit_ack: Explicit Acknowledge flag 1285 * @explicit_ack_type: Explicit Acknowledge type 1286 * @r2r_end_status_follow: Response to Response status flag 1287 * @response_type: Response type in response window 1288 * @ndp_frame: NDP frame 1289 * @num_users: number of users 1290 * @reserved: reserved bits 1291 * @mba_count: MBA count 1292 * @mba_fake_bitmap_count: MBA fake bitmap count 1293 * @sw_frame_group_id: software frame group ID 1294 * @r2r_to_follow: Response to Response follow flag 1295 * @phy_abort_reason: Reason for PHY abort 1296 * @phy_abort_user_number: User number for PHY abort 1297 * @buffer: Packet buffer pointer address 1298 * @offset: Packet buffer offset 1299 * @length: Packet buffer length 1300 * @protection_addr: Protection Address flag 1301 * @addr1: MAC address 1 1302 * @addr2: MAC address 2 1303 * @addr3: MAC address 3 1304 * @addr4: MAC address 4 1305 */ 1306 struct hal_tx_status_info { 1307 uint8_t reception_type; 1308 uint8_t transmission_type; 1309 uint8_t medium_prot_type; 1310 uint8_t generated_response; 1311 1312 uint16_t band_center_freq1; 1313 uint16_t band_center_freq2; 1314 uint16_t freq; 1315 uint16_t phy_mode; 1316 uint32_t schedule_id; 1317 1318 uint32_t no_bitmap_avail :1, 1319 explicit_ack :1, 1320 explicit_ack_type :4, 1321 r2r_end_status_follow :1, 1322 response_type :5, 1323 ndp_frame :2, 1324 num_users :8, 1325 reserved :10; 1326 1327 uint8_t mba_count; 1328 uint8_t mba_fake_bitmap_count; 1329 1330 uint8_t sw_frame_group_id; 1331 uint32_t r2r_to_follow; 1332 1333 uint16_t phy_abort_reason; 1334 uint8_t phy_abort_user_number; 1335 1336 void *buffer; 1337 uint32_t offset; 1338 uint32_t length; 1339 1340 uint8_t protection_addr; 1341 uint8_t addr1[QDF_MAC_ADDR_SIZE]; 1342 uint8_t addr2[QDF_MAC_ADDR_SIZE]; 1343 uint8_t addr3[QDF_MAC_ADDR_SIZE]; 1344 uint8_t addr4[QDF_MAC_ADDR_SIZE]; 1345 }; 1346 1347 /** 1348 * struct hal_tx_ppdu_info - tx monitor ppdu information 1349 * @ppdu_id: Id of the PLCP protocol data unit 1350 * @num_users: number of users 1351 * @is_used: boolean flag to identify valid ppdu info 1352 * @is_data: boolean flag to identify data frame 1353 * @cur_usr_idx: Current user index of the PPDU 1354 * @reserved: for future purpose 1355 * @prot_tlv_status: protection tlv status 1356 * @tx_tlv_info: store tx tlv info for recording 1357 * @packet_info: packet information 1358 * @rx_status: monitor mode rx status information 1359 * @rx_user_status: monitor mode rx user status information 1360 */ 1361 struct hal_tx_ppdu_info { 1362 uint32_t ppdu_id; 1363 uint32_t num_users :8, 1364 is_used :1, 1365 is_data :1, 1366 cur_usr_idx :8, 1367 reserved :15; 1368 1369 uint32_t prot_tlv_status; 1370 1371 #ifdef MONITOR_TLV_RECORDING_ENABLE 1372 struct hal_tx_tlv_info tx_tlv_info; 1373 #endif 1374 /* placeholder to hold packet buffer info */ 1375 struct hal_mon_packet_info packet_info; 1376 struct mon_rx_status rx_status; 1377 struct mon_rx_user_status rx_user_status[]; 1378 }; 1379 1380 /** 1381 * hal_tx_status_get_next_tlv() - get next tx status TLV 1382 * @tx_tlv: pointer to TLV header 1383 * @is_tlv_hdr_64_bit: Flag to indicate tlv hdr 64 bit 1384 * 1385 * Return: pointer to next tlv info 1386 */ 1387 static inline uint8_t* 1388 hal_tx_status_get_next_tlv(uint8_t *tx_tlv, bool is_tlv_hdr_64_bit) { 1389 uint32_t tlv_len, tlv_hdr_size; 1390 1391 tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv); 1392 tlv_hdr_size = is_tlv_hdr_64_bit ? HAL_RX_TLV64_HDR_SIZE : 1393 HAL_RX_TLV32_HDR_SIZE; 1394 1395 return (uint8_t *)(uintptr_t)qdf_align((uint64_t)((uintptr_t)tx_tlv + 1396 tlv_len + 1397 tlv_hdr_size), 1398 tlv_hdr_size); 1399 } 1400 1401 /** 1402 * hal_txmon_status_parse_tlv() - process transmit info TLV 1403 * @hal_soc_hdl: HAL soc handle 1404 * @data_ppdu_info: pointer to hal data ppdu info 1405 * @prot_ppdu_info: pointer to hal prot ppdu info 1406 * @data_status_info: pointer to data status info 1407 * @prot_status_info: pointer to prot status info 1408 * @tx_tlv_hdr: pointer to TLV header 1409 * @status_frag: pointer to status frag 1410 * 1411 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE 1412 */ 1413 static inline uint32_t 1414 hal_txmon_status_parse_tlv(hal_soc_handle_t hal_soc_hdl, 1415 void *data_ppdu_info, 1416 void *prot_ppdu_info, 1417 void *data_status_info, 1418 void *prot_status_info, 1419 void *tx_tlv_hdr, 1420 qdf_frag_t status_frag) 1421 { 1422 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1423 1424 return hal_soc->ops->hal_txmon_status_parse_tlv(data_ppdu_info, 1425 prot_ppdu_info, 1426 data_status_info, 1427 prot_status_info, 1428 tx_tlv_hdr, 1429 status_frag); 1430 } 1431 1432 /** 1433 * hal_txmon_status_get_num_users() - api to get num users from start of fes 1434 * window 1435 * @hal_soc_hdl: HAL soc handle 1436 * @tx_tlv_hdr: pointer to TLV header 1437 * @num_users: reference to number of user 1438 * 1439 * Return: status 1440 */ 1441 static inline uint32_t 1442 hal_txmon_status_get_num_users(hal_soc_handle_t hal_soc_hdl, 1443 void *tx_tlv_hdr, uint8_t *num_users) 1444 { 1445 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1446 1447 return hal_soc->ops->hal_txmon_status_get_num_users(tx_tlv_hdr, 1448 num_users); 1449 } 1450 1451 /** 1452 * hal_tx_status_get_tlv_tag() - api to get tlv tag 1453 * @tx_tlv_hdr: pointer to TLV header 1454 * 1455 * Return tlv_tag 1456 */ 1457 static inline uint32_t 1458 hal_tx_status_get_tlv_tag(void *tx_tlv_hdr) 1459 { 1460 uint32_t tlv_tag = 0; 1461 1462 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr); 1463 1464 return tlv_tag; 1465 } 1466 1467 /** 1468 * hal_txmon_get_word_mask() - api to get word mask for tx monitor 1469 * @hal_soc_hdl: HAL soc handle 1470 * @wmask: pointer to hal_txmon_word_mask_config_t 1471 * 1472 * Return: bool 1473 */ 1474 static inline bool 1475 hal_txmon_get_word_mask(hal_soc_handle_t hal_soc_hdl, 1476 hal_txmon_word_mask_config_t *wmask) 1477 { 1478 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1479 1480 if (hal_soc->ops->hal_txmon_get_word_mask) { 1481 hal_soc->ops->hal_txmon_get_word_mask(wmask); 1482 return true; 1483 } 1484 1485 return false; 1486 } 1487 1488 /** 1489 * hal_txmon_is_mon_buf_addr_tlv() - api to find packet buffer addr tlv 1490 * @hal_soc_hdl: HAL soc handle 1491 * @tx_tlv_hdr: pointer to TLV header 1492 * 1493 * Return: bool 1494 */ 1495 static inline bool 1496 hal_txmon_is_mon_buf_addr_tlv(hal_soc_handle_t hal_soc_hdl, void *tx_tlv_hdr) 1497 { 1498 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1499 1500 if (qdf_unlikely(!hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv)) 1501 return false; 1502 1503 return hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv(tx_tlv_hdr); 1504 } 1505 1506 /** 1507 * hal_txmon_populate_packet_info() - api to populate packet info 1508 * @hal_soc_hdl: HAL soc handle 1509 * @tx_tlv_hdr: pointer to TLV header 1510 * @packet_info: pointer to placeholder for packet info 1511 * 1512 * Return void 1513 */ 1514 static inline void 1515 hal_txmon_populate_packet_info(hal_soc_handle_t hal_soc_hdl, 1516 void *tx_tlv_hdr, 1517 void *packet_info) 1518 { 1519 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1520 1521 if (qdf_unlikely(!hal_soc->ops->hal_txmon_populate_packet_info)) 1522 return; 1523 1524 hal_soc->ops->hal_txmon_populate_packet_info(tx_tlv_hdr, packet_info); 1525 } 1526 #endif 1527 1528 static inline uint32_t 1529 hal_rx_parse_u_sig_cmn(struct hal_soc *hal_soc, void *rx_tlv, 1530 struct hal_rx_ppdu_info *ppdu_info) 1531 { 1532 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1533 struct hal_mon_usig_cmn *usig_1 = &usig->usig_1; 1534 uint8_t bad_usig_crc; 1535 1536 bad_usig_crc = HAL_RX_MON_USIG_GET_RX_INTEGRITY_CHECK_PASSED(rx_tlv) ? 1537 0 : 1; 1538 ppdu_info->rx_status.usig_common |= 1539 QDF_MON_STATUS_USIG_PHY_VERSION_KNOWN | 1540 QDF_MON_STATUS_USIG_BW_KNOWN | 1541 QDF_MON_STATUS_USIG_UL_DL_KNOWN | 1542 QDF_MON_STATUS_USIG_BSS_COLOR_KNOWN | 1543 QDF_MON_STATUS_USIG_TXOP_KNOWN; 1544 1545 ppdu_info->rx_status.usig_common |= (usig_1->phy_version << 1546 QDF_MON_STATUS_USIG_PHY_VERSION_SHIFT); 1547 ppdu_info->rx_status.usig_common |= (usig_1->bw << 1548 QDF_MON_STATUS_USIG_BW_SHIFT); 1549 ppdu_info->rx_status.usig_common |= (usig_1->ul_dl << 1550 QDF_MON_STATUS_USIG_UL_DL_SHIFT); 1551 ppdu_info->rx_status.usig_common |= (usig_1->bss_color << 1552 QDF_MON_STATUS_USIG_BSS_COLOR_SHIFT); 1553 ppdu_info->rx_status.usig_common |= (usig_1->txop << 1554 QDF_MON_STATUS_USIG_TXOP_SHIFT); 1555 ppdu_info->rx_status.usig_common |= bad_usig_crc; 1556 1557 ppdu_info->u_sig_info.ul_dl = usig_1->ul_dl; 1558 ppdu_info->u_sig_info.bw = usig_1->bw; 1559 ppdu_info->rx_status.bw = usig_1->bw; 1560 1561 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1562 } 1563 1564 static inline uint32_t 1565 hal_rx_parse_u_sig_tb(struct hal_soc *hal_soc, void *rx_tlv, 1566 struct hal_rx_ppdu_info *ppdu_info) 1567 { 1568 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1569 struct hal_mon_usig_tb *usig_tb = &usig->usig_2.tb; 1570 1571 ppdu_info->rx_status.usig_mask |= 1572 QDF_MON_STATUS_USIG_DISREGARD_KNOWN | 1573 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN | 1574 QDF_MON_STATUS_USIG_VALIDATE_KNOWN | 1575 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_KNOWN | 1576 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_KNOWN | 1577 QDF_MON_STATUS_USIG_TB_DISREGARD1_KNOWN | 1578 QDF_MON_STATUS_USIG_CRC_KNOWN | 1579 QDF_MON_STATUS_USIG_TAIL_KNOWN; 1580 1581 ppdu_info->rx_status.usig_value |= (0x3F << 1582 QDF_MON_STATUS_USIG_DISREGARD_SHIFT); 1583 ppdu_info->rx_status.usig_value |= (usig_tb->ppdu_type_comp_mode << 1584 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT); 1585 ppdu_info->rx_status.usig_value |= (0x1 << 1586 QDF_MON_STATUS_USIG_VALIDATE_SHIFT); 1587 ppdu_info->rx_status.usig_value |= (usig_tb->spatial_reuse_1 << 1588 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_SHIFT); 1589 ppdu_info->rx_status.usig_value |= (usig_tb->spatial_reuse_2 << 1590 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_SHIFT); 1591 ppdu_info->rx_status.usig_value |= (0x1F << 1592 QDF_MON_STATUS_USIG_TB_DISREGARD1_SHIFT); 1593 ppdu_info->rx_status.usig_value |= (usig_tb->crc << 1594 QDF_MON_STATUS_USIG_CRC_SHIFT); 1595 ppdu_info->rx_status.usig_value |= (usig_tb->tail << 1596 QDF_MON_STATUS_USIG_TAIL_SHIFT); 1597 1598 ppdu_info->u_sig_info.ppdu_type_comp_mode = 1599 usig_tb->ppdu_type_comp_mode; 1600 1601 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1602 } 1603 1604 static inline uint32_t 1605 hal_rx_parse_u_sig_mu(struct hal_soc *hal_soc, void *rx_tlv, 1606 struct hal_rx_ppdu_info *ppdu_info) 1607 { 1608 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1609 struct hal_mon_usig_mu *usig_mu = &usig->usig_2.mu; 1610 1611 ppdu_info->rx_status.usig_mask |= 1612 QDF_MON_STATUS_USIG_DISREGARD_KNOWN | 1613 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN | 1614 QDF_MON_STATUS_USIG_VALIDATE_KNOWN | 1615 QDF_MON_STATUS_USIG_MU_VALIDATE1_KNOWN | 1616 QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_KNOWN | 1617 QDF_MON_STATUS_USIG_MU_VALIDATE2_KNOWN | 1618 QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_KNOWN | 1619 QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_KNOWN | 1620 QDF_MON_STATUS_USIG_CRC_KNOWN | 1621 QDF_MON_STATUS_USIG_TAIL_KNOWN; 1622 1623 ppdu_info->rx_status.usig_value |= (0x1F << 1624 QDF_MON_STATUS_USIG_DISREGARD_SHIFT); 1625 ppdu_info->rx_status.usig_value |= (0x1 << 1626 QDF_MON_STATUS_USIG_MU_VALIDATE1_SHIFT); 1627 ppdu_info->rx_status.usig_value |= (usig_mu->ppdu_type_comp_mode << 1628 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT); 1629 ppdu_info->rx_status.usig_value |= (0x1 << 1630 QDF_MON_STATUS_USIG_VALIDATE_SHIFT); 1631 ppdu_info->rx_status.usig_value |= (usig_mu->punc_ch_info << 1632 QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_SHIFT); 1633 ppdu_info->rx_status.usig_value |= (0x1 << 1634 QDF_MON_STATUS_USIG_MU_VALIDATE2_SHIFT); 1635 ppdu_info->rx_status.usig_value |= (usig_mu->eht_sig_mcs << 1636 QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_SHIFT); 1637 ppdu_info->rx_status.usig_value |= (usig_mu->num_eht_sig_sym << 1638 QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_SHIFT); 1639 ppdu_info->rx_status.usig_value |= (usig_mu->crc << 1640 QDF_MON_STATUS_USIG_CRC_SHIFT); 1641 ppdu_info->rx_status.usig_value |= (usig_mu->tail << 1642 QDF_MON_STATUS_USIG_TAIL_SHIFT); 1643 1644 ppdu_info->u_sig_info.ppdu_type_comp_mode = 1645 usig_mu->ppdu_type_comp_mode; 1646 ppdu_info->u_sig_info.eht_sig_mcs = usig_mu->eht_sig_mcs; 1647 ppdu_info->u_sig_info.num_eht_sig_sym = usig_mu->num_eht_sig_sym; 1648 1649 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1650 } 1651 1652 static inline uint32_t 1653 hal_rx_parse_u_sig_hdr(struct hal_soc *hal_soc, void *rx_tlv, 1654 struct hal_rx_ppdu_info *ppdu_info) 1655 { 1656 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1657 struct hal_mon_usig_cmn *usig_1 = &usig->usig_1; 1658 1659 ppdu_info->rx_status.usig_flags = 1; 1660 1661 hal_rx_parse_u_sig_cmn(hal_soc, rx_tlv, ppdu_info); 1662 1663 if (HAL_RX_MON_USIG_GET_PPDU_TYPE_N_COMP_MODE(rx_tlv) == 0 && 1664 usig_1->ul_dl == 1) 1665 return hal_rx_parse_u_sig_tb(hal_soc, rx_tlv, ppdu_info); 1666 else 1667 return hal_rx_parse_u_sig_mu(hal_soc, rx_tlv, ppdu_info); 1668 } 1669 1670 static inline uint32_t 1671 hal_rx_parse_usig_overflow(struct hal_soc *hal_soc, void *tlv, 1672 struct hal_rx_ppdu_info *ppdu_info) 1673 { 1674 struct hal_eht_sig_cc_usig_overflow *usig_ovflow = 1675 (struct hal_eht_sig_cc_usig_overflow *)tlv; 1676 1677 ppdu_info->rx_status.eht_known |= 1678 QDF_MON_STATUS_EHT_SPATIAL_REUSE_KNOWN | 1679 QDF_MON_STATUS_EHT_EHT_LTF_KNOWN | 1680 QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_KNOWN | 1681 QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_KNOWN | 1682 QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_KNOWN | 1683 QDF_MON_STATUS_EHT_DISREARD_KNOWN; 1684 1685 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->spatial_reuse << 1686 QDF_MON_STATUS_EHT_SPATIAL_REUSE_SHIFT); 1687 /* 1688 * GI and LTF size are separately indicated in radiotap header 1689 * and hence will be parsed from other TLV 1690 **/ 1691 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->num_ltf_sym << 1692 QDF_MON_STATUS_EHT_EHT_LTF_SHIFT); 1693 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->ldpc_extra_sym << 1694 QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_SHIFT); 1695 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->pre_fec_pad_factor << 1696 QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_SHIFT); 1697 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->pe_disambiguity << 1698 QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_SHIFT); 1699 ppdu_info->rx_status.eht_data[0] |= (0xF << 1700 QDF_MON_STATUS_EHT_DISREGARD_SHIFT); 1701 1702 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1703 } 1704 1705 static inline uint32_t 1706 hal_rx_parse_non_ofdma_users(struct hal_soc *hal_soc, void *tlv, 1707 struct hal_rx_ppdu_info *ppdu_info) 1708 { 1709 struct hal_eht_sig_non_ofdma_cmn_eb *non_ofdma_cmn_eb = 1710 (struct hal_eht_sig_non_ofdma_cmn_eb *)tlv; 1711 1712 ppdu_info->rx_status.eht_known |= 1713 QDF_MON_STATUS_EHT_NUM_NON_OFDMA_USERS_KNOWN; 1714 1715 ppdu_info->rx_status.eht_data[4] |= (non_ofdma_cmn_eb->num_users << 1716 QDF_MON_STATUS_EHT_NUM_NON_OFDMA_USERS_SHIFT); 1717 1718 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1719 } 1720 1721 static inline uint32_t 1722 hal_rx_parse_ru_allocation(struct hal_soc *hal_soc, void *tlv, 1723 struct hal_rx_ppdu_info *ppdu_info) 1724 { 1725 uint64_t *ehtsig_tlv = (uint64_t *)tlv; 1726 struct hal_eht_sig_ofdma_cmn_eb1 *ofdma_cmn_eb1; 1727 struct hal_eht_sig_ofdma_cmn_eb2 *ofdma_cmn_eb2; 1728 uint8_t num_ru_allocation_known = 0; 1729 1730 ofdma_cmn_eb1 = (struct hal_eht_sig_ofdma_cmn_eb1 *)ehtsig_tlv; 1731 ofdma_cmn_eb2 = (struct hal_eht_sig_ofdma_cmn_eb2 *)(ehtsig_tlv + 1); 1732 1733 switch (ppdu_info->u_sig_info.bw) { 1734 case HAL_EHT_BW_320_2: 1735 case HAL_EHT_BW_320_1: 1736 num_ru_allocation_known += 4; 1737 1738 ppdu_info->rx_status.eht_data[3] |= 1739 (ofdma_cmn_eb2->ru_allocation2_6 << 1740 QDF_MON_STATUS_EHT_RU_ALLOCATION2_6_SHIFT); 1741 ppdu_info->rx_status.eht_data[3] |= 1742 (ofdma_cmn_eb2->ru_allocation2_5 << 1743 QDF_MON_STATUS_EHT_RU_ALLOCATION2_5_SHIFT); 1744 ppdu_info->rx_status.eht_data[3] |= 1745 (ofdma_cmn_eb2->ru_allocation2_4 << 1746 QDF_MON_STATUS_EHT_RU_ALLOCATION2_4_SHIFT); 1747 ppdu_info->rx_status.eht_data[2] |= 1748 (ofdma_cmn_eb2->ru_allocation2_3 << 1749 QDF_MON_STATUS_EHT_RU_ALLOCATION2_3_SHIFT); 1750 fallthrough; 1751 case HAL_EHT_BW_160: 1752 num_ru_allocation_known += 2; 1753 1754 ppdu_info->rx_status.eht_data[2] |= 1755 (ofdma_cmn_eb2->ru_allocation2_2 << 1756 QDF_MON_STATUS_EHT_RU_ALLOCATION2_2_SHIFT); 1757 ppdu_info->rx_status.eht_data[2] |= 1758 (ofdma_cmn_eb2->ru_allocation2_1 << 1759 QDF_MON_STATUS_EHT_RU_ALLOCATION2_1_SHIFT); 1760 fallthrough; 1761 case HAL_EHT_BW_80: 1762 num_ru_allocation_known += 1; 1763 1764 ppdu_info->rx_status.eht_data[1] |= 1765 (ofdma_cmn_eb1->ru_allocation1_2 << 1766 QDF_MON_STATUS_EHT_RU_ALLOCATION1_2_SHIFT); 1767 fallthrough; 1768 case HAL_EHT_BW_40: 1769 case HAL_EHT_BW_20: 1770 num_ru_allocation_known += 1; 1771 1772 ppdu_info->rx_status.eht_data[1] |= 1773 (ofdma_cmn_eb1->ru_allocation1_1 << 1774 QDF_MON_STATUS_EHT_RU_ALLOCATION1_1_SHIFT); 1775 break; 1776 default: 1777 break; 1778 } 1779 1780 ppdu_info->rx_status.eht_known |= (num_ru_allocation_known << 1781 QDF_MON_STATUS_EHT_NUM_KNOWN_RU_ALLOCATIONS_SHIFT); 1782 1783 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1784 } 1785 1786 static inline uint32_t 1787 hal_rx_parse_eht_sig_mumimo_user_info(struct hal_soc *hal_soc, void *tlv, 1788 struct hal_rx_ppdu_info *ppdu_info) 1789 { 1790 struct hal_eht_sig_mu_mimo_user_info *user_info; 1791 uint32_t user_idx = ppdu_info->rx_status.num_eht_user_info_valid; 1792 1793 user_info = (struct hal_eht_sig_mu_mimo_user_info *)tlv; 1794 1795 ppdu_info->rx_status.eht_user_info[user_idx] |= 1796 QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN | 1797 QDF_MON_STATUS_EHT_USER_MCS_KNOWN | 1798 QDF_MON_STATUS_EHT_USER_CODING_KNOWN | 1799 QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_KNOWN; 1800 1801 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->sta_id << 1802 QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT); 1803 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->mcs << 1804 QDF_MON_STATUS_EHT_USER_MCS_SHIFT); 1805 ppdu_info->rx_status.mcs = user_info->mcs; 1806 1807 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->coding << 1808 QDF_MON_STATUS_EHT_USER_CODING_SHIFT); 1809 ppdu_info->rx_status.eht_user_info[user_idx] |= 1810 (user_info->spatial_coding << 1811 QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_SHIFT); 1812 1813 /* CRC for matched user block */ 1814 ppdu_info->rx_status.eht_known |= 1815 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_KNOWN | 1816 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_TAIL_KNOWN; 1817 ppdu_info->rx_status.eht_data[4] |= (user_info->crc << 1818 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_SHIFT); 1819 1820 ppdu_info->rx_status.num_eht_user_info_valid++; 1821 1822 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1823 } 1824 1825 static inline uint32_t 1826 hal_rx_parse_eht_sig_non_mumimo_user_info(struct hal_soc *hal_soc, void *tlv, 1827 struct hal_rx_ppdu_info *ppdu_info) 1828 { 1829 struct hal_eht_sig_non_mu_mimo_user_info *user_info; 1830 uint32_t user_idx = ppdu_info->rx_status.num_eht_user_info_valid; 1831 1832 user_info = (struct hal_eht_sig_non_mu_mimo_user_info *)tlv; 1833 1834 ppdu_info->rx_status.eht_user_info[user_idx] |= 1835 QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN | 1836 QDF_MON_STATUS_EHT_USER_MCS_KNOWN | 1837 QDF_MON_STATUS_EHT_USER_CODING_KNOWN | 1838 QDF_MON_STATUS_EHT_USER_NSS_KNOWN | 1839 QDF_MON_STATUS_EHT_USER_BEAMFORMING_KNOWN; 1840 1841 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->sta_id << 1842 QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT); 1843 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->mcs << 1844 QDF_MON_STATUS_EHT_USER_MCS_SHIFT); 1845 ppdu_info->rx_status.mcs = user_info->mcs; 1846 1847 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->nss << 1848 QDF_MON_STATUS_EHT_USER_NSS_SHIFT); 1849 ppdu_info->rx_status.nss = user_info->nss + 1; 1850 1851 ppdu_info->rx_status.eht_user_info[user_idx] |= 1852 (user_info->beamformed << 1853 QDF_MON_STATUS_EHT_USER_BEAMFORMING_SHIFT); 1854 ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->coding << 1855 QDF_MON_STATUS_EHT_USER_CODING_SHIFT); 1856 1857 /* CRC for matched user block */ 1858 ppdu_info->rx_status.eht_known |= 1859 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_KNOWN | 1860 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_TAIL_KNOWN; 1861 ppdu_info->rx_status.eht_data[4] |= (user_info->crc << 1862 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_SHIFT); 1863 1864 ppdu_info->rx_status.num_eht_user_info_valid++; 1865 1866 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1867 } 1868 1869 static inline bool hal_rx_is_ofdma(struct hal_soc *hal_soc, 1870 struct hal_rx_ppdu_info *ppdu_info) 1871 { 1872 if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 0 && 1873 ppdu_info->u_sig_info.ul_dl == 0) 1874 return true; 1875 1876 return false; 1877 } 1878 1879 static inline bool hal_rx_is_non_ofdma(struct hal_soc *hal_soc, 1880 struct hal_rx_ppdu_info *ppdu_info) 1881 { 1882 uint32_t ppdu_type_comp_mode = 1883 ppdu_info->u_sig_info.ppdu_type_comp_mode; 1884 uint32_t ul_dl = ppdu_info->u_sig_info.ul_dl; 1885 1886 if ((ppdu_type_comp_mode == 1 && ul_dl == 0) || 1887 (ppdu_type_comp_mode == 2 && ul_dl == 0) || 1888 (ppdu_type_comp_mode == 1 && ul_dl == 1)) 1889 return true; 1890 1891 return false; 1892 } 1893 1894 static inline bool hal_rx_is_mu_mimo_user(struct hal_soc *hal_soc, 1895 struct hal_rx_ppdu_info *ppdu_info) 1896 { 1897 if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 2 && 1898 ppdu_info->u_sig_info.ul_dl == 0) 1899 return true; 1900 1901 return false; 1902 } 1903 1904 static inline bool 1905 hal_rx_is_frame_type_ndp(struct hal_soc *hal_soc, 1906 struct hal_rx_ppdu_info *ppdu_info) 1907 { 1908 if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 1 && 1909 ppdu_info->u_sig_info.eht_sig_mcs == 0 && 1910 ppdu_info->u_sig_info.num_eht_sig_sym == 0) 1911 return true; 1912 1913 return false; 1914 } 1915 1916 static inline uint32_t 1917 hal_rx_parse_eht_sig_ndp(struct hal_soc *hal_soc, void *tlv, 1918 struct hal_rx_ppdu_info *ppdu_info) 1919 { 1920 struct hal_eht_sig_ndp_cmn_eb *eht_sig_ndp = 1921 (struct hal_eht_sig_ndp_cmn_eb *)tlv; 1922 1923 ppdu_info->rx_status.eht_known |= 1924 QDF_MON_STATUS_EHT_SPATIAL_REUSE_KNOWN | 1925 QDF_MON_STATUS_EHT_EHT_LTF_KNOWN | 1926 QDF_MON_STATUS_EHT_NDP_NSS_KNOWN | 1927 QDF_MON_STATUS_EHT_NDP_BEAMFORMED_KNOWN | 1928 QDF_MON_STATUS_EHT_NDP_DISREGARD_KNOWN | 1929 QDF_MON_STATUS_EHT_CRC1_KNOWN | 1930 QDF_MON_STATUS_EHT_TAIL1_KNOWN; 1931 1932 ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->spatial_reuse << 1933 QDF_MON_STATUS_EHT_SPATIAL_REUSE_SHIFT); 1934 /* 1935 * GI and LTF size are separately indicated in radiotap header 1936 * and hence will be parsed from other TLV 1937 **/ 1938 ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->num_ltf_sym << 1939 QDF_MON_STATUS_EHT_EHT_LTF_SHIFT); 1940 ppdu_info->rx_status.eht_data[0] |= (0xF << 1941 QDF_MON_STATUS_EHT_NDP_DISREGARD_SHIFT); 1942 1943 ppdu_info->rx_status.eht_data[4] |= (eht_sig_ndp->nss << 1944 QDF_MON_STATUS_EHT_NDP_NSS_SHIFT); 1945 ppdu_info->rx_status.eht_data[4] |= (eht_sig_ndp->beamformed << 1946 QDF_MON_STATUS_EHT_NDP_BEAMFORMED_SHIFT); 1947 1948 ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->crc << 1949 QDF_MON_STATUS_EHT_CRC1_SHIFT); 1950 1951 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1952 } 1953 1954 static inline uint32_t 1955 hal_rx_parse_eht_sig_non_ofdma(struct hal_soc *hal_soc, void *tlv, 1956 struct hal_rx_ppdu_info *ppdu_info) 1957 { 1958 void *user_info = (void *)((uint8_t *)tlv + 4); 1959 1960 hal_rx_parse_usig_overflow(hal_soc, tlv, ppdu_info); 1961 hal_rx_parse_non_ofdma_users(hal_soc, tlv, ppdu_info); 1962 1963 if (hal_rx_is_mu_mimo_user(hal_soc, ppdu_info)) 1964 hal_rx_parse_eht_sig_mumimo_user_info(hal_soc, user_info, 1965 ppdu_info); 1966 else 1967 hal_rx_parse_eht_sig_non_mumimo_user_info(hal_soc, user_info, 1968 ppdu_info); 1969 1970 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1971 } 1972 1973 static inline uint32_t 1974 hal_rx_parse_eht_sig_ofdma(struct hal_soc *hal_soc, void *tlv, 1975 struct hal_rx_ppdu_info *ppdu_info) 1976 { 1977 uint64_t *eht_sig_tlv = (uint64_t *)tlv; 1978 void *user_info = (void *)(eht_sig_tlv + 2); 1979 1980 hal_rx_parse_usig_overflow(hal_soc, tlv, ppdu_info); 1981 hal_rx_parse_ru_allocation(hal_soc, tlv, ppdu_info); 1982 hal_rx_parse_eht_sig_non_mumimo_user_info(hal_soc, user_info, 1983 ppdu_info); 1984 1985 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1986 } 1987 1988 static inline uint32_t 1989 hal_rx_parse_eht_sig_hdr(struct hal_soc *hal_soc, uint8_t *tlv, 1990 struct hal_rx_ppdu_info *ppdu_info) 1991 { 1992 ppdu_info->rx_status.eht_flags = 1; 1993 1994 if (hal_rx_is_frame_type_ndp(hal_soc, ppdu_info)) 1995 hal_rx_parse_eht_sig_ndp(hal_soc, tlv, ppdu_info); 1996 else if (hal_rx_is_non_ofdma(hal_soc, ppdu_info)) 1997 hal_rx_parse_eht_sig_non_ofdma(hal_soc, tlv, ppdu_info); 1998 else if (hal_rx_is_ofdma(hal_soc, ppdu_info)) 1999 hal_rx_parse_eht_sig_ofdma(hal_soc, tlv, ppdu_info); 2000 2001 return HAL_TLV_STATUS_PPDU_NOT_DONE; 2002 } 2003 2004 #ifdef WLAN_FEATURE_11BE 2005 static inline void 2006 hal_rx_parse_punctured_pattern(struct phyrx_common_user_info *cmn_usr_info, 2007 struct hal_rx_ppdu_info *ppdu_info) 2008 { 2009 ppdu_info->rx_status.punctured_pattern = cmn_usr_info->puncture_bitmap; 2010 } 2011 #else 2012 static inline void 2013 hal_rx_parse_punctured_pattern(struct phyrx_common_user_info *cmn_usr_info, 2014 struct hal_rx_ppdu_info *ppdu_info) 2015 { 2016 } 2017 #endif 2018 static inline uint32_t 2019 hal_rx_parse_cmn_usr_info(struct hal_soc *hal_soc, uint8_t *tlv, 2020 struct hal_rx_ppdu_info *ppdu_info) 2021 { 2022 struct phyrx_common_user_info *cmn_usr_info = 2023 (struct phyrx_common_user_info *)tlv; 2024 2025 ppdu_info->rx_status.eht_known |= 2026 QDF_MON_STATUS_EHT_GUARD_INTERVAL_KNOWN | 2027 QDF_MON_STATUS_EHT_LTF_KNOWN; 2028 2029 ppdu_info->rx_status.eht_data[0] |= (cmn_usr_info->cp_setting << 2030 QDF_MON_STATUS_EHT_GI_SHIFT); 2031 if (!ppdu_info->rx_status.sgi) 2032 ppdu_info->rx_status.sgi = cmn_usr_info->cp_setting; 2033 2034 ppdu_info->rx_status.eht_data[0] |= (cmn_usr_info->ltf_size << 2035 QDF_MON_STATUS_EHT_LTF_SHIFT); 2036 if (!ppdu_info->rx_status.ltf_size) 2037 ppdu_info->rx_status.ltf_size = cmn_usr_info->ltf_size; 2038 2039 hal_rx_parse_punctured_pattern(cmn_usr_info, ppdu_info); 2040 2041 return HAL_TLV_STATUS_PPDU_NOT_DONE; 2042 } 2043 2044 #ifdef WLAN_FEATURE_11BE 2045 static inline void 2046 hal_rx_ul_ofdma_ru_size_to_width(uint32_t ru_size, 2047 uint32_t *ru_width) 2048 { 2049 uint32_t width; 2050 2051 width = 0; 2052 switch (ru_size) { 2053 case IEEE80211_EHT_RU_26: 2054 width = RU_26; 2055 break; 2056 case IEEE80211_EHT_RU_52: 2057 width = RU_52; 2058 break; 2059 case IEEE80211_EHT_RU_52_26: 2060 width = RU_52_26; 2061 break; 2062 case IEEE80211_EHT_RU_106: 2063 width = RU_106; 2064 break; 2065 case IEEE80211_EHT_RU_106_26: 2066 width = RU_106_26; 2067 break; 2068 case IEEE80211_EHT_RU_242: 2069 width = RU_242; 2070 break; 2071 case IEEE80211_EHT_RU_484: 2072 width = RU_484; 2073 break; 2074 case IEEE80211_EHT_RU_484_242: 2075 width = RU_484_242; 2076 break; 2077 case IEEE80211_EHT_RU_996: 2078 width = RU_996; 2079 break; 2080 case IEEE80211_EHT_RU_996_484: 2081 width = RU_996_484; 2082 break; 2083 case IEEE80211_EHT_RU_996_484_242: 2084 width = RU_996_484_242; 2085 break; 2086 case IEEE80211_EHT_RU_996x2: 2087 width = RU_2X996; 2088 break; 2089 case IEEE80211_EHT_RU_996x2_484: 2090 width = RU_2X996_484; 2091 break; 2092 case IEEE80211_EHT_RU_996x3: 2093 width = RU_3X996; 2094 break; 2095 case IEEE80211_EHT_RU_996x3_484: 2096 width = RU_3X996_484; 2097 break; 2098 case IEEE80211_EHT_RU_996x4: 2099 width = RU_4X996; 2100 break; 2101 default: 2102 hal_err_rl("RU size(%d) to width convert err", ru_size); 2103 break; 2104 } 2105 *ru_width = width; 2106 } 2107 #else 2108 static inline void 2109 hal_rx_ul_ofdma_ru_size_to_width(uint32_t ru_size, 2110 uint32_t *ru_width) 2111 { 2112 *ru_width = 0; 2113 } 2114 #endif 2115 2116 static inline enum ieee80211_eht_ru_size 2117 hal_rx_mon_hal_ru_size_to_ieee80211_ru_size(struct hal_soc *hal_soc, 2118 uint32_t hal_ru_size) 2119 { 2120 switch (hal_ru_size) { 2121 case HAL_EHT_RU_26: 2122 return IEEE80211_EHT_RU_26; 2123 case HAL_EHT_RU_52: 2124 return IEEE80211_EHT_RU_52; 2125 case HAL_EHT_RU_78: 2126 return IEEE80211_EHT_RU_52_26; 2127 case HAL_EHT_RU_106: 2128 return IEEE80211_EHT_RU_106; 2129 case HAL_EHT_RU_132: 2130 return IEEE80211_EHT_RU_106_26; 2131 case HAL_EHT_RU_242: 2132 return IEEE80211_EHT_RU_242; 2133 case HAL_EHT_RU_484: 2134 return IEEE80211_EHT_RU_484; 2135 case HAL_EHT_RU_726: 2136 return IEEE80211_EHT_RU_484_242; 2137 case HAL_EHT_RU_996: 2138 return IEEE80211_EHT_RU_996; 2139 case HAL_EHT_RU_996x2: 2140 return IEEE80211_EHT_RU_996x2; 2141 case HAL_EHT_RU_996x3: 2142 return IEEE80211_EHT_RU_996x3; 2143 case HAL_EHT_RU_996x4: 2144 return IEEE80211_EHT_RU_996x4; 2145 case HAL_EHT_RU_NONE: 2146 return IEEE80211_EHT_RU_INVALID; 2147 case HAL_EHT_RU_996_484: 2148 return IEEE80211_EHT_RU_996_484; 2149 case HAL_EHT_RU_996x2_484: 2150 return IEEE80211_EHT_RU_996x2_484; 2151 case HAL_EHT_RU_996x3_484: 2152 return IEEE80211_EHT_RU_996x3_484; 2153 case HAL_EHT_RU_996_484_242: 2154 return IEEE80211_EHT_RU_996_484_242; 2155 default: 2156 return IEEE80211_EHT_RU_INVALID; 2157 } 2158 } 2159 2160 #define HAL_SET_RU_PER80(ru_320mhz, ru_per80, ru_idx_per80mhz, num_80mhz) \ 2161 ((ru_320mhz) |= ((uint64_t)(ru_per80) << \ 2162 (((num_80mhz) * NUM_RU_BITS_PER80) + \ 2163 ((ru_idx_per80mhz) * NUM_RU_BITS_PER20)))) 2164 2165 static inline uint32_t 2166 hal_rx_parse_receive_user_info(struct hal_soc *hal_soc, uint8_t *tlv, 2167 struct hal_rx_ppdu_info *ppdu_info, 2168 uint32_t user_id) 2169 { 2170 struct receive_user_info *rx_usr_info = (struct receive_user_info *)tlv; 2171 struct mon_rx_user_status *mon_rx_user_status = NULL; 2172 uint64_t ru_index_320mhz = 0; 2173 uint16_t ru_index_per80mhz; 2174 uint32_t ru_size = 0, num_80mhz_with_ru = 0; 2175 uint32_t ru_index = HAL_EHT_RU_INVALID; 2176 uint32_t rtap_ru_size = IEEE80211_EHT_RU_INVALID; 2177 uint32_t ru_width; 2178 2179 ppdu_info->rx_status.eht_known |= 2180 QDF_MON_STATUS_EHT_CONTENT_CH_INDEX_KNOWN; 2181 ppdu_info->rx_status.eht_data[0] |= 2182 (rx_usr_info->dl_ofdma_content_channel << 2183 QDF_MON_STATUS_EHT_CONTENT_CH_INDEX_SHIFT); 2184 2185 switch (rx_usr_info->reception_type) { 2186 case HAL_RECEPTION_TYPE_SU: 2187 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 2188 break; 2189 case HAL_RECEPTION_TYPE_DL_MU_MIMO: 2190 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_DL; 2191 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 2192 break; 2193 case HAL_RECEPTION_TYPE_UL_MU_MIMO: 2194 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_UL; 2195 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 2196 break; 2197 case HAL_RECEPTION_TYPE_DL_MU_OFMA: 2198 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_DL; 2199 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 2200 break; 2201 case HAL_RECEPTION_TYPE_UL_MU_OFDMA: 2202 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_UL; 2203 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 2204 break; 2205 case HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO: 2206 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_DL; 2207 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA_MIMO; 2208 break; 2209 case HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO: 2210 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_UL; 2211 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA_MIMO; 2212 break; 2213 } 2214 2215 ppdu_info->start_user_info_cnt++; 2216 2217 ppdu_info->rx_status.is_stbc = rx_usr_info->stbc; 2218 ppdu_info->rx_status.ldpc = rx_usr_info->ldpc; 2219 ppdu_info->rx_status.dcm = rx_usr_info->sta_dcm; 2220 ppdu_info->rx_status.mcs = rx_usr_info->rate_mcs; 2221 ppdu_info->rx_status.nss = rx_usr_info->nss + 1; 2222 2223 if (user_id < HAL_MAX_UL_MU_USERS) { 2224 mon_rx_user_status = 2225 &ppdu_info->rx_user_status[user_id]; 2226 mon_rx_user_status->mcs = ppdu_info->rx_status.mcs; 2227 mon_rx_user_status->nss = ppdu_info->rx_status.nss; 2228 } 2229 2230 if (!(ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_MIMO || 2231 ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_OFDMA || 2232 ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_OFDMA_MIMO)) 2233 return HAL_TLV_STATUS_PPDU_NOT_DONE; 2234 2235 /* RU allocation present only for OFDMA reception */ 2236 if (rx_usr_info->ru_type_80_0 != HAL_EHT_RU_NONE) { 2237 ru_size += rx_usr_info->ru_type_80_0; 2238 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_0; 2239 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_0, 2240 ru_index_per80mhz, 0); 2241 num_80mhz_with_ru++; 2242 } 2243 2244 if (rx_usr_info->ru_type_80_1 != HAL_EHT_RU_NONE) { 2245 ru_size += rx_usr_info->ru_type_80_1; 2246 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_1; 2247 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_1, 2248 ru_index_per80mhz, 1); 2249 num_80mhz_with_ru++; 2250 } 2251 2252 if (rx_usr_info->ru_type_80_2 != HAL_EHT_RU_NONE) { 2253 ru_size += rx_usr_info->ru_type_80_2; 2254 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_2; 2255 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_2, 2256 ru_index_per80mhz, 2); 2257 num_80mhz_with_ru++; 2258 } 2259 2260 if (rx_usr_info->ru_type_80_3 != HAL_EHT_RU_NONE) { 2261 ru_size += rx_usr_info->ru_type_80_3; 2262 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_3; 2263 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_3, 2264 ru_index_per80mhz, 3); 2265 num_80mhz_with_ru++; 2266 } 2267 2268 if (num_80mhz_with_ru > 1) { 2269 /* Calculate the MRU index */ 2270 switch (ru_index_320mhz) { 2271 case HAL_EHT_RU_996_484_0: 2272 case HAL_EHT_RU_996x2_484_0: 2273 case HAL_EHT_RU_996x3_484_0: 2274 ru_index = 0; 2275 break; 2276 case HAL_EHT_RU_996_484_1: 2277 case HAL_EHT_RU_996x2_484_1: 2278 case HAL_EHT_RU_996x3_484_1: 2279 ru_index = 1; 2280 break; 2281 case HAL_EHT_RU_996_484_2: 2282 case HAL_EHT_RU_996x2_484_2: 2283 case HAL_EHT_RU_996x3_484_2: 2284 ru_index = 2; 2285 break; 2286 case HAL_EHT_RU_996_484_3: 2287 case HAL_EHT_RU_996x2_484_3: 2288 case HAL_EHT_RU_996x3_484_3: 2289 ru_index = 3; 2290 break; 2291 case HAL_EHT_RU_996_484_4: 2292 case HAL_EHT_RU_996x2_484_4: 2293 case HAL_EHT_RU_996x3_484_4: 2294 ru_index = 4; 2295 break; 2296 case HAL_EHT_RU_996_484_5: 2297 case HAL_EHT_RU_996x2_484_5: 2298 case HAL_EHT_RU_996x3_484_5: 2299 ru_index = 5; 2300 break; 2301 case HAL_EHT_RU_996_484_6: 2302 case HAL_EHT_RU_996x2_484_6: 2303 case HAL_EHT_RU_996x3_484_6: 2304 ru_index = 6; 2305 break; 2306 case HAL_EHT_RU_996_484_7: 2307 case HAL_EHT_RU_996x2_484_7: 2308 case HAL_EHT_RU_996x3_484_7: 2309 ru_index = 7; 2310 break; 2311 case HAL_EHT_RU_996x2_484_8: 2312 ru_index = 8; 2313 break; 2314 case HAL_EHT_RU_996x2_484_9: 2315 ru_index = 9; 2316 break; 2317 case HAL_EHT_RU_996x2_484_10: 2318 ru_index = 10; 2319 break; 2320 case HAL_EHT_RU_996x2_484_11: 2321 ru_index = 11; 2322 break; 2323 default: 2324 ru_index = HAL_EHT_RU_INVALID; 2325 dp_debug("Invalid RU index"); 2326 qdf_assert(0); 2327 break; 2328 } 2329 ru_size += 4; 2330 } 2331 2332 rtap_ru_size = hal_rx_mon_hal_ru_size_to_ieee80211_ru_size(hal_soc, 2333 ru_size); 2334 if (rtap_ru_size != IEEE80211_EHT_RU_INVALID) { 2335 ppdu_info->rx_status.eht_known |= 2336 QDF_MON_STATUS_EHT_RU_MRU_SIZE_KNOWN; 2337 ppdu_info->rx_status.eht_data[1] |= (rtap_ru_size << 2338 QDF_MON_STATUS_EHT_RU_MRU_SIZE_SHIFT); 2339 } 2340 2341 if (ru_index != HAL_EHT_RU_INVALID) { 2342 ppdu_info->rx_status.eht_known |= 2343 QDF_MON_STATUS_EHT_RU_MRU_INDEX_KNOWN; 2344 ppdu_info->rx_status.eht_data[1] |= (ru_index << 2345 QDF_MON_STATUS_EHT_RU_MRU_INDEX_SHIFT); 2346 } 2347 2348 if (mon_rx_user_status && ru_index != HAL_EHT_RU_INVALID && 2349 rtap_ru_size != IEEE80211_EHT_RU_INVALID) { 2350 mon_rx_user_status->ofdma_ru_start_index = ru_index; 2351 mon_rx_user_status->ofdma_ru_size = rtap_ru_size; 2352 hal_rx_ul_ofdma_ru_size_to_width(rtap_ru_size, &ru_width); 2353 mon_rx_user_status->ofdma_ru_width = ru_width; 2354 mon_rx_user_status->mu_ul_info_valid = 1; 2355 } 2356 2357 return HAL_TLV_STATUS_PPDU_NOT_DONE; 2358 } 2359 2360 #ifdef WLAN_PKT_CAPTURE_RX_2_0 2361 static inline void 2362 hal_rx_status_get_mpdu_retry_cnt(struct hal_rx_ppdu_info *ppdu_info, 2363 hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user) 2364 { 2365 ppdu_info->rx_status.mpdu_retry_cnt = 2366 rx_ppdu_end_user->retried_mpdu_count; 2367 } 2368 2369 static inline void 2370 hal_rx_status_get_mon_buf_addr(uint8_t *rx_tlv, 2371 struct hal_rx_ppdu_info *ppdu_info) 2372 { 2373 struct mon_buffer_addr *addr = (struct mon_buffer_addr *)rx_tlv; 2374 2375 ppdu_info->packet_info.sw_cookie = 2376 (((uint64_t)addr->buffer_virt_addr_63_32 << 32) | 2377 (addr->buffer_virt_addr_31_0)); 2378 /* HW DMA length is '-1' of actual DMA length*/ 2379 ppdu_info->packet_info.dma_length = addr->dma_length + 1; 2380 ppdu_info->packet_info.msdu_continuation = addr->msdu_continuation; 2381 ppdu_info->packet_info.truncated = addr->truncated; 2382 2383 } 2384 2385 static inline void 2386 hal_rx_update_ppdu_drop_cnt(uint8_t *rx_tlv, 2387 struct hal_rx_ppdu_info *ppdu_info) 2388 { 2389 struct mon_drop *drop_cnt = (struct mon_drop *)rx_tlv; 2390 2391 ppdu_info->drop_cnt.ppdu_drop_cnt = drop_cnt->ppdu_drop_cnt; 2392 ppdu_info->drop_cnt.mpdu_drop_cnt = drop_cnt->mpdu_drop_cnt; 2393 ppdu_info->drop_cnt.end_of_ppdu_drop_cnt = drop_cnt->end_of_ppdu_seen; 2394 ppdu_info->drop_cnt.tlv_drop_cnt = drop_cnt->tlv_drop_cnt; 2395 } 2396 #else 2397 static inline void 2398 hal_rx_status_get_mpdu_retry_cnt(struct hal_rx_ppdu_info *ppdu_info, 2399 hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user) 2400 { 2401 ppdu_info->rx_status.mpdu_retry_cnt = 0; 2402 } 2403 static inline void 2404 hal_rx_status_get_mon_buf_addr(uint8_t *rx_tlv, 2405 struct hal_rx_ppdu_info *ppdu_info) 2406 { 2407 } 2408 2409 static inline void 2410 hal_rx_update_ppdu_drop_cnt(uint8_t *rx_tlv, 2411 struct hal_rx_ppdu_info *ppdu_info) 2412 { 2413 } 2414 #endif 2415 2416 #ifdef WLAN_SUPPORT_CTRL_FRAME_STATS 2417 static inline void 2418 hal_update_rx_ctrl_frame_stats(struct hal_rx_ppdu_info *ppdu_info, 2419 uint32_t user_id) 2420 { 2421 uint16_t fc = ppdu_info->nac_info.frame_control; 2422 2423 if (HAL_RX_GET_FRAME_CTRL_TYPE(fc) == HAL_RX_FRAME_CTRL_TYPE_CTRL) { 2424 if ((fc & QDF_IEEE80211_FC0_SUBTYPE_MASK) == 2425 QDF_IEEE80211_FC0_SUBTYPE_VHT_NDP_AN) 2426 ppdu_info->ctrl_frm_info[user_id].ndpa = 1; 2427 if ((fc & QDF_IEEE80211_FC0_SUBTYPE_MASK) == 2428 QDF_IEEE80211_FC0_SUBTYPE_BAR) 2429 ppdu_info->ctrl_frm_info[user_id].bar = 1; 2430 } 2431 } 2432 #else 2433 static inline void 2434 hal_update_rx_ctrl_frame_stats(struct hal_rx_ppdu_info *ppdu_info, 2435 uint32_t user_id) 2436 { 2437 } 2438 #endif /* WLAN_SUPPORT_CTRL_FRAME_STATS */ 2439 2440 #ifdef MONITOR_TLV_RECORDING_ENABLE 2441 /** 2442 * hal_rx_record_tlv_info() - Record received TLV info 2443 * @ppdu_info: pointer to ppdu_info 2444 * @tlv_tag: TLV tag of the TLV to record 2445 * 2446 * Return 2447 */ 2448 static inline void 2449 hal_rx_record_tlv_info(struct hal_rx_ppdu_info *ppdu_info, uint32_t tlv_tag) { 2450 ppdu_info->rx_tlv_info.tlv_tag = tlv_tag; 2451 switch (tlv_tag) { 2452 case WIFIRX_PPDU_START_E: 2453 case WIFIRX_PPDU_START_USER_INFO_E: 2454 ppdu_info->rx_tlv_info.tlv_category = CATEGORY_PPDU_START; 2455 break; 2456 2457 case WIFIRX_HEADER_E: 2458 case WIFIRX_MPDU_START_E: 2459 case WIFIMON_BUFFER_ADDR_E: 2460 case WIFIRX_MSDU_END_E: 2461 case WIFIRX_MPDU_END_E: 2462 ppdu_info->rx_tlv_info.tlv_category = CATEGORY_MPDU; 2463 break; 2464 2465 case WIFIRX_USER_PPDU_END_E: 2466 case WIFIRX_PPDU_END_E: 2467 case WIFIPHYRX_RSSI_LEGACY_E: 2468 case WIFIPHYRX_L_SIG_B_E: 2469 case WIFIPHYRX_COMMON_USER_INFO_E: 2470 case WIFIPHYRX_DATA_DONE_E: 2471 case WIFIPHYRX_PKT_END_PART1_E: 2472 case WIFIPHYRX_PKT_END_E: 2473 case WIFIRXPCU_PPDU_END_INFO_E: 2474 case WIFIRX_PPDU_END_USER_STATS_E: 2475 case WIFIRX_PPDU_END_STATUS_DONE_E: 2476 ppdu_info->rx_tlv_info.tlv_category = CATEGORY_PPDU_END; 2477 break; 2478 } 2479 } 2480 #else 2481 static inline void 2482 hal_rx_record_tlv_info(struct hal_rx_ppdu_info *ppdu_info, uint32_t tlv_tag) { 2483 } 2484 #endif 2485 2486 /** 2487 * hal_rx_status_get_tlv_info_generic_be() - process receive info TLV 2488 * @rx_tlv_hdr: pointer to TLV header 2489 * @ppduinfo: pointer to ppdu_info 2490 * @hal_soc_hdl: HAL version of the SOC pointer 2491 * @nbuf: Network buffer 2492 * 2493 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 2494 */ 2495 static inline uint32_t 2496 hal_rx_status_get_tlv_info_generic_be(void *rx_tlv_hdr, void *ppduinfo, 2497 hal_soc_handle_t hal_soc_hdl, 2498 qdf_nbuf_t nbuf) 2499 { 2500 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2501 uint32_t tlv_tag, user_id, tlv_len, value; 2502 uint8_t group_id = 0; 2503 uint8_t he_dcm = 0; 2504 uint8_t he_stbc = 0; 2505 uint16_t he_gi = 0; 2506 uint16_t he_ltf = 0; 2507 void *rx_tlv; 2508 struct mon_rx_user_status *mon_rx_user_status; 2509 struct hal_rx_ppdu_info *ppdu_info = 2510 (struct hal_rx_ppdu_info *)ppduinfo; 2511 2512 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 2513 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 2514 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 2515 2516 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV_HDR_SIZE; 2517 2518 ppdu_info->user_id = user_id; 2519 switch (tlv_tag) { 2520 case WIFIRX_PPDU_START_E: 2521 { 2522 if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id == 2523 HAL_RX_GET_64(rx_tlv, RX_PPDU_START, PHY_PPDU_ID))) 2524 hal_err("Matching ppdu_id(%u) detected", 2525 ppdu_info->com_info.last_ppdu_id); 2526 2527 ppdu_info->com_info.last_ppdu_id = 2528 ppdu_info->com_info.ppdu_id = 2529 HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 2530 PHY_PPDU_ID); 2531 2532 /* channel number is set in PHY meta data */ 2533 ppdu_info->rx_status.chan_num = 2534 (HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 2535 SW_PHY_META_DATA) & 0x0000FFFF); 2536 ppdu_info->rx_status.chan_freq = 2537 (HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 2538 SW_PHY_META_DATA) & 0xFFFF0000) >> 16; 2539 if (ppdu_info->rx_status.chan_num && 2540 ppdu_info->rx_status.chan_freq) { 2541 ppdu_info->rx_status.chan_freq = 2542 hal_rx_radiotap_num_to_freq( 2543 ppdu_info->rx_status.chan_num, 2544 ppdu_info->rx_status.chan_freq); 2545 } 2546 2547 ppdu_info->com_info.ppdu_timestamp = 2548 HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 2549 PPDU_START_TIMESTAMP_31_0); 2550 ppdu_info->rx_status.ppdu_timestamp = 2551 ppdu_info->com_info.ppdu_timestamp; 2552 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 2553 2554 break; 2555 } 2556 2557 case WIFIRX_PPDU_START_USER_INFO_E: 2558 hal_rx_parse_receive_user_info(hal, rx_tlv, ppdu_info, user_id); 2559 break; 2560 2561 case WIFIRX_PPDU_END_E: 2562 /* This is followed by sub-TLVs of PPDU_END */ 2563 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 2564 break; 2565 2566 case WIFIPHYRX_LOCATION_E: 2567 hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info); 2568 break; 2569 2570 case WIFIRXPCU_PPDU_END_INFO_E: 2571 ppdu_info->rx_status.rx_antenna = 2572 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, RX_ANTENNA); 2573 ppdu_info->rx_status.tsft = 2574 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, 2575 WB_TIMESTAMP_UPPER_32); 2576 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 2577 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, 2578 WB_TIMESTAMP_LOWER_32); 2579 ppdu_info->rx_status.duration = 2580 HAL_RX_GET_64(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 2581 RX_PPDU_DURATION); 2582 hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info); 2583 break; 2584 2585 /* 2586 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received. 2587 * for MU, based on num users we see this tlv that many times. 2588 */ 2589 case WIFIRX_PPDU_END_USER_STATS_E: 2590 { 2591 hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user = rx_tlv; 2592 unsigned long tid = 0; 2593 uint16_t seq = 0; 2594 2595 ppdu_info->rx_status.ast_index = 2596 rx_ppdu_end_user->ast_index; 2597 2598 tid = rx_ppdu_end_user->received_qos_data_tid_bitmap; 2599 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, 2600 sizeof(tid) * 8); 2601 2602 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 2603 ppdu_info->rx_status.tid = HAL_TID_INVALID; 2604 2605 ppdu_info->rx_status.tcp_msdu_count = 2606 rx_ppdu_end_user->tcp_msdu_count + 2607 rx_ppdu_end_user->tcp_ack_msdu_count; 2608 2609 ppdu_info->rx_status.udp_msdu_count = 2610 rx_ppdu_end_user->udp_msdu_count; 2611 2612 ppdu_info->rx_status.other_msdu_count = 2613 rx_ppdu_end_user->other_msdu_count; 2614 2615 hal_rx_status_get_mpdu_retry_cnt(ppdu_info, rx_ppdu_end_user); 2616 2617 if (ppdu_info->sw_frame_group_id 2618 != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 2619 ppdu_info->rx_status.frame_control_info_valid = 2620 rx_ppdu_end_user->frame_control_info_valid; 2621 2622 if (ppdu_info->rx_status.frame_control_info_valid) 2623 ppdu_info->rx_status.frame_control = 2624 rx_ppdu_end_user->frame_control_field; 2625 2626 hal_get_qos_control(rx_ppdu_end_user, ppdu_info); 2627 } 2628 2629 ppdu_info->rx_status.data_sequence_control_info_valid = 2630 rx_ppdu_end_user->data_sequence_control_info_valid; 2631 2632 seq = rx_ppdu_end_user->first_data_seq_ctrl; 2633 2634 if (ppdu_info->rx_status.data_sequence_control_info_valid) 2635 ppdu_info->rx_status.first_data_seq_ctrl = seq; 2636 2637 ppdu_info->rx_status.preamble_type = 2638 rx_ppdu_end_user->ht_control_field_pkt_type; 2639 2640 ppdu_info->end_user_stats_cnt++; 2641 2642 switch (ppdu_info->rx_status.preamble_type) { 2643 case HAL_RX_PKT_TYPE_11N: 2644 ppdu_info->rx_status.ht_flags = 1; 2645 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 2646 break; 2647 case HAL_RX_PKT_TYPE_11AC: 2648 ppdu_info->rx_status.vht_flags = 1; 2649 break; 2650 case HAL_RX_PKT_TYPE_11AX: 2651 ppdu_info->rx_status.he_flags = 1; 2652 break; 2653 default: 2654 break; 2655 } 2656 2657 ppdu_info->com_info.mpdu_cnt_fcs_ok = 2658 rx_ppdu_end_user->mpdu_cnt_fcs_ok; 2659 ppdu_info->com_info.mpdu_cnt_fcs_err = 2660 rx_ppdu_end_user->mpdu_cnt_fcs_err; 2661 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 2662 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 2663 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 2664 else 2665 ppdu_info->rx_status.rs_flags &= 2666 (~IEEE80211_AMPDU_FLAG); 2667 2668 ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] = 2669 rx_ppdu_end_user->fcs_ok_bitmap_31_0; 2670 2671 ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] = 2672 rx_ppdu_end_user->fcs_ok_bitmap_63_32; 2673 2674 if (user_id < HAL_MAX_UL_MU_USERS) { 2675 mon_rx_user_status = 2676 &ppdu_info->rx_user_status[user_id]; 2677 2678 hal_rx_handle_mu_ul_info(rx_ppdu_end_user, 2679 mon_rx_user_status); 2680 2681 ppdu_info->com_info.num_users++; 2682 2683 hal_rx_populate_mu_user_info(rx_ppdu_end_user, ppdu_info, 2684 user_id, 2685 mon_rx_user_status); 2686 } 2687 break; 2688 } 2689 2690 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 2691 ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] = 2692 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2693 FCS_OK_BITMAP_95_64); 2694 2695 ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] = 2696 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2697 FCS_OK_BITMAP_127_96); 2698 2699 ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] = 2700 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2701 FCS_OK_BITMAP_159_128); 2702 2703 ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] = 2704 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2705 FCS_OK_BITMAP_191_160); 2706 2707 ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] = 2708 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2709 FCS_OK_BITMAP_223_192); 2710 2711 ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] = 2712 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2713 FCS_OK_BITMAP_255_224); 2714 break; 2715 2716 case WIFIRX_PPDU_END_STATUS_DONE_E: 2717 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 2718 return HAL_TLV_STATUS_PPDU_DONE; 2719 2720 case WIFIPHYRX_PKT_END_E: 2721 break; 2722 2723 case WIFIDUMMY_E: 2724 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 2725 return HAL_TLV_STATUS_BUF_DONE; 2726 2727 case WIFIPHYRX_HT_SIG_E: 2728 { 2729 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 2730 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 2731 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 2732 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO, FEC_CODING); 2733 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 2734 1 : 0; 2735 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 2736 HT_SIG_INFO, MCS); 2737 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 2738 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 2739 HT_SIG_INFO, CBW); 2740 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 2741 HT_SIG_INFO, SHORT_GI); 2742 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 2743 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 2744 HT_SIG_SU_NSS_SHIFT) + 1; 2745 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 2746 break; 2747 } 2748 2749 case WIFIPHYRX_L_SIG_B_E: 2750 { 2751 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 2752 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 2753 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 2754 2755 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO, RATE); 2756 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 2757 switch (value) { 2758 case 1: 2759 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 2760 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 2761 break; 2762 case 2: 2763 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 2764 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 2765 break; 2766 case 3: 2767 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 2768 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 2769 break; 2770 case 4: 2771 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 2772 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 2773 break; 2774 case 5: 2775 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 2776 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 2777 break; 2778 case 6: 2779 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 2780 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 2781 break; 2782 case 7: 2783 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 2784 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 2785 break; 2786 default: 2787 break; 2788 } 2789 ppdu_info->rx_status.cck_flag = 1; 2790 break; 2791 } 2792 2793 case WIFIPHYRX_L_SIG_A_E: 2794 { 2795 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 2796 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 2797 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 2798 2799 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO, RATE); 2800 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 2801 switch (value) { 2802 case 8: 2803 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 2804 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 2805 break; 2806 case 9: 2807 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 2808 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 2809 break; 2810 case 10: 2811 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 2812 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 2813 break; 2814 case 11: 2815 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 2816 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 2817 break; 2818 case 12: 2819 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 2820 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 2821 break; 2822 case 13: 2823 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 2824 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 2825 break; 2826 case 14: 2827 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 2828 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 2829 break; 2830 case 15: 2831 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 2832 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 2833 break; 2834 default: 2835 break; 2836 } 2837 ppdu_info->rx_status.ofdm_flag = 1; 2838 break; 2839 } 2840 2841 case WIFIPHYRX_VHT_SIG_A_E: 2842 { 2843 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 2844 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 2845 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 2846 2847 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO, 2848 SU_MU_CODING); 2849 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 2850 1 : 0; 2851 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO, GROUP_ID); 2852 ppdu_info->rx_status.vht_flag_values5 = group_id; 2853 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 2854 VHT_SIG_A_INFO, MCS); 2855 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 2856 VHT_SIG_A_INFO, 2857 GI_SETTING); 2858 2859 switch (hal->target_type) { 2860 case TARGET_TYPE_QCA8074: 2861 case TARGET_TYPE_QCA8074V2: 2862 case TARGET_TYPE_QCA6018: 2863 case TARGET_TYPE_QCA5018: 2864 case TARGET_TYPE_QCN9000: 2865 case TARGET_TYPE_QCN6122: 2866 case TARGET_TYPE_QCN6432: 2867 #ifdef QCA_WIFI_QCA6390 2868 case TARGET_TYPE_QCA6390: 2869 #endif 2870 ppdu_info->rx_status.is_stbc = 2871 HAL_RX_GET(vht_sig_a_info, 2872 VHT_SIG_A_INFO, STBC); 2873 value = HAL_RX_GET(vht_sig_a_info, 2874 VHT_SIG_A_INFO, N_STS); 2875 value = value & VHT_SIG_SU_NSS_MASK; 2876 if (ppdu_info->rx_status.is_stbc && (value > 0)) 2877 value = ((value + 1) >> 1) - 1; 2878 ppdu_info->rx_status.nss = 2879 ((value & VHT_SIG_SU_NSS_MASK) + 1); 2880 2881 break; 2882 case TARGET_TYPE_QCA6290: 2883 #if !defined(QCA_WIFI_QCA6290_11AX) 2884 ppdu_info->rx_status.is_stbc = 2885 HAL_RX_GET(vht_sig_a_info, 2886 VHT_SIG_A_INFO, STBC); 2887 value = HAL_RX_GET(vht_sig_a_info, 2888 VHT_SIG_A_INFO, N_STS); 2889 value = value & VHT_SIG_SU_NSS_MASK; 2890 if (ppdu_info->rx_status.is_stbc && (value > 0)) 2891 value = ((value + 1) >> 1) - 1; 2892 ppdu_info->rx_status.nss = 2893 ((value & VHT_SIG_SU_NSS_MASK) + 1); 2894 #else 2895 ppdu_info->rx_status.nss = 0; 2896 #endif 2897 break; 2898 case TARGET_TYPE_KIWI: 2899 case TARGET_TYPE_MANGO: 2900 case TARGET_TYPE_PEACH: 2901 ppdu_info->rx_status.is_stbc = 2902 HAL_RX_GET(vht_sig_a_info, 2903 VHT_SIG_A_INFO, STBC); 2904 value = HAL_RX_GET(vht_sig_a_info, 2905 VHT_SIG_A_INFO, N_STS); 2906 value = value & VHT_SIG_SU_NSS_MASK; 2907 if (ppdu_info->rx_status.is_stbc && (value > 0)) 2908 value = ((value + 1) >> 1) - 1; 2909 ppdu_info->rx_status.nss = 2910 ((value & VHT_SIG_SU_NSS_MASK) + 1); 2911 2912 break; 2913 case TARGET_TYPE_QCA6490: 2914 case TARGET_TYPE_QCA6750: 2915 ppdu_info->rx_status.nss = 0; 2916 break; 2917 default: 2918 break; 2919 } 2920 ppdu_info->rx_status.vht_flag_values3[0] = 2921 (((ppdu_info->rx_status.mcs) << 4) 2922 | ppdu_info->rx_status.nss); 2923 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 2924 VHT_SIG_A_INFO, BANDWIDTH); 2925 ppdu_info->rx_status.vht_flag_values2 = 2926 ppdu_info->rx_status.bw; 2927 ppdu_info->rx_status.vht_flag_values4 = 2928 HAL_RX_GET(vht_sig_a_info, 2929 VHT_SIG_A_INFO, SU_MU_CODING); 2930 2931 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 2932 VHT_SIG_A_INFO, 2933 BEAMFORMED); 2934 if (group_id == 0 || group_id == 63) 2935 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 2936 else 2937 ppdu_info->rx_status.reception_type = 2938 HAL_RX_TYPE_MU_MIMO; 2939 2940 break; 2941 } 2942 case WIFIPHYRX_HE_SIG_A_SU_E: 2943 { 2944 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 2945 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 2946 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 2947 ppdu_info->rx_status.he_flags = 1; 2948 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 2949 FORMAT_INDICATION); 2950 if (value == 0) { 2951 ppdu_info->rx_status.he_data1 = 2952 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 2953 } else { 2954 ppdu_info->rx_status.he_data1 = 2955 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 2956 } 2957 2958 /* data1 */ 2959 ppdu_info->rx_status.he_data1 |= 2960 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 2961 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 2962 QDF_MON_STATUS_HE_DL_UL_KNOWN | 2963 QDF_MON_STATUS_HE_MCS_KNOWN | 2964 QDF_MON_STATUS_HE_DCM_KNOWN | 2965 QDF_MON_STATUS_HE_CODING_KNOWN | 2966 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 2967 QDF_MON_STATUS_HE_STBC_KNOWN | 2968 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 2969 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 2970 2971 /* data2 */ 2972 ppdu_info->rx_status.he_data2 = 2973 QDF_MON_STATUS_HE_GI_KNOWN; 2974 ppdu_info->rx_status.he_data2 |= 2975 QDF_MON_STATUS_TXBF_KNOWN | 2976 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 2977 QDF_MON_STATUS_TXOP_KNOWN | 2978 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 2979 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 2980 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 2981 2982 /* data3 */ 2983 value = HAL_RX_GET(he_sig_a_su_info, 2984 HE_SIG_A_SU_INFO, BSS_COLOR_ID); 2985 ppdu_info->rx_status.he_data3 = value; 2986 value = HAL_RX_GET(he_sig_a_su_info, 2987 HE_SIG_A_SU_INFO, BEAM_CHANGE); 2988 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 2989 ppdu_info->rx_status.he_data3 |= value; 2990 value = HAL_RX_GET(he_sig_a_su_info, 2991 HE_SIG_A_SU_INFO, DL_UL_FLAG); 2992 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 2993 ppdu_info->rx_status.he_data3 |= value; 2994 2995 value = HAL_RX_GET(he_sig_a_su_info, 2996 HE_SIG_A_SU_INFO, TRANSMIT_MCS); 2997 ppdu_info->rx_status.mcs = value; 2998 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 2999 ppdu_info->rx_status.he_data3 |= value; 3000 3001 value = HAL_RX_GET(he_sig_a_su_info, 3002 HE_SIG_A_SU_INFO, DCM); 3003 he_dcm = value; 3004 value = value << QDF_MON_STATUS_DCM_SHIFT; 3005 ppdu_info->rx_status.he_data3 |= value; 3006 value = HAL_RX_GET(he_sig_a_su_info, 3007 HE_SIG_A_SU_INFO, CODING); 3008 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 3009 1 : 0; 3010 value = value << QDF_MON_STATUS_CODING_SHIFT; 3011 ppdu_info->rx_status.he_data3 |= value; 3012 value = HAL_RX_GET(he_sig_a_su_info, 3013 HE_SIG_A_SU_INFO, 3014 LDPC_EXTRA_SYMBOL); 3015 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 3016 ppdu_info->rx_status.he_data3 |= value; 3017 value = HAL_RX_GET(he_sig_a_su_info, 3018 HE_SIG_A_SU_INFO, STBC); 3019 he_stbc = value; 3020 value = value << QDF_MON_STATUS_STBC_SHIFT; 3021 ppdu_info->rx_status.he_data3 |= value; 3022 3023 /* data4 */ 3024 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 3025 SPATIAL_REUSE); 3026 ppdu_info->rx_status.he_data4 = value; 3027 3028 /* data5 */ 3029 value = HAL_RX_GET(he_sig_a_su_info, 3030 HE_SIG_A_SU_INFO, TRANSMIT_BW); 3031 ppdu_info->rx_status.he_data5 = value; 3032 ppdu_info->rx_status.bw = value; 3033 value = HAL_RX_GET(he_sig_a_su_info, 3034 HE_SIG_A_SU_INFO, CP_LTF_SIZE); 3035 switch (value) { 3036 case 0: 3037 he_gi = HE_GI_0_8; 3038 he_ltf = HE_LTF_1_X; 3039 break; 3040 case 1: 3041 he_gi = HE_GI_0_8; 3042 he_ltf = HE_LTF_2_X; 3043 break; 3044 case 2: 3045 he_gi = HE_GI_1_6; 3046 he_ltf = HE_LTF_2_X; 3047 break; 3048 case 3: 3049 if (he_dcm && he_stbc) { 3050 he_gi = HE_GI_0_8; 3051 he_ltf = HE_LTF_4_X; 3052 } else { 3053 he_gi = HE_GI_3_2; 3054 he_ltf = HE_LTF_4_X; 3055 } 3056 break; 3057 } 3058 ppdu_info->rx_status.sgi = he_gi; 3059 ppdu_info->rx_status.ltf_size = he_ltf; 3060 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 3061 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 3062 ppdu_info->rx_status.he_data5 |= value; 3063 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 3064 ppdu_info->rx_status.he_data5 |= value; 3065 3066 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS); 3067 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 3068 ppdu_info->rx_status.he_data5 |= value; 3069 3070 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 3071 PACKET_EXTENSION_A_FACTOR); 3072 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 3073 ppdu_info->rx_status.he_data5 |= value; 3074 3075 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, TXBF); 3076 value = value << QDF_MON_STATUS_TXBF_SHIFT; 3077 ppdu_info->rx_status.he_data5 |= value; 3078 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 3079 PACKET_EXTENSION_PE_DISAMBIGUITY); 3080 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 3081 ppdu_info->rx_status.he_data5 |= value; 3082 3083 /* data6 */ 3084 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS); 3085 value++; 3086 ppdu_info->rx_status.nss = value; 3087 ppdu_info->rx_status.he_data6 = value; 3088 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 3089 DOPPLER_INDICATION); 3090 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 3091 ppdu_info->rx_status.he_data6 |= value; 3092 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 3093 TXOP_DURATION); 3094 value = value << QDF_MON_STATUS_TXOP_SHIFT; 3095 ppdu_info->rx_status.he_data6 |= value; 3096 3097 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 3098 HE_SIG_A_SU_INFO, 3099 TXBF); 3100 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 3101 break; 3102 } 3103 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 3104 { 3105 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 3106 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 3107 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 3108 3109 ppdu_info->rx_status.he_mu_flags = 1; 3110 3111 /* HE Flags */ 3112 /*data1*/ 3113 ppdu_info->rx_status.he_data1 = 3114 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 3115 ppdu_info->rx_status.he_data1 |= 3116 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 3117 QDF_MON_STATUS_HE_DL_UL_KNOWN | 3118 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 3119 QDF_MON_STATUS_HE_STBC_KNOWN | 3120 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 3121 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 3122 3123 /* data2 */ 3124 ppdu_info->rx_status.he_data2 = 3125 QDF_MON_STATUS_HE_GI_KNOWN; 3126 ppdu_info->rx_status.he_data2 |= 3127 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 3128 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 3129 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 3130 QDF_MON_STATUS_TXOP_KNOWN | 3131 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 3132 3133 /*data3*/ 3134 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3135 HE_SIG_A_MU_DL_INFO, BSS_COLOR_ID); 3136 ppdu_info->rx_status.he_data3 = value; 3137 3138 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3139 HE_SIG_A_MU_DL_INFO, DL_UL_FLAG); 3140 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 3141 ppdu_info->rx_status.he_data3 |= value; 3142 3143 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3144 HE_SIG_A_MU_DL_INFO, 3145 LDPC_EXTRA_SYMBOL); 3146 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 3147 ppdu_info->rx_status.he_data3 |= value; 3148 3149 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3150 HE_SIG_A_MU_DL_INFO, STBC); 3151 he_stbc = value; 3152 value = value << QDF_MON_STATUS_STBC_SHIFT; 3153 ppdu_info->rx_status.he_data3 |= value; 3154 3155 /*data4*/ 3156 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 3157 SPATIAL_REUSE); 3158 ppdu_info->rx_status.he_data4 = value; 3159 3160 /*data5*/ 3161 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3162 HE_SIG_A_MU_DL_INFO, TRANSMIT_BW); 3163 ppdu_info->rx_status.he_data5 = value; 3164 ppdu_info->rx_status.bw = value; 3165 3166 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3167 HE_SIG_A_MU_DL_INFO, CP_LTF_SIZE); 3168 switch (value) { 3169 case 0: 3170 he_gi = HE_GI_0_8; 3171 he_ltf = HE_LTF_4_X; 3172 break; 3173 case 1: 3174 he_gi = HE_GI_0_8; 3175 he_ltf = HE_LTF_2_X; 3176 break; 3177 case 2: 3178 he_gi = HE_GI_1_6; 3179 he_ltf = HE_LTF_2_X; 3180 break; 3181 case 3: 3182 he_gi = HE_GI_3_2; 3183 he_ltf = HE_LTF_4_X; 3184 break; 3185 } 3186 ppdu_info->rx_status.sgi = he_gi; 3187 ppdu_info->rx_status.ltf_size = he_ltf; 3188 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 3189 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 3190 ppdu_info->rx_status.he_data5 |= value; 3191 3192 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 3193 ppdu_info->rx_status.he_data5 |= value; 3194 3195 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3196 HE_SIG_A_MU_DL_INFO, NUM_LTF_SYMBOLS); 3197 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 3198 ppdu_info->rx_status.he_data5 |= value; 3199 3200 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 3201 PACKET_EXTENSION_A_FACTOR); 3202 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 3203 ppdu_info->rx_status.he_data5 |= value; 3204 3205 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 3206 PACKET_EXTENSION_PE_DISAMBIGUITY); 3207 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 3208 ppdu_info->rx_status.he_data5 |= value; 3209 3210 /*data6*/ 3211 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 3212 DOPPLER_INDICATION); 3213 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 3214 ppdu_info->rx_status.he_data6 |= value; 3215 3216 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 3217 TXOP_DURATION); 3218 value = value << QDF_MON_STATUS_TXOP_SHIFT; 3219 ppdu_info->rx_status.he_data6 |= value; 3220 3221 /* HE-MU Flags */ 3222 /* HE-MU-flags1 */ 3223 ppdu_info->rx_status.he_flags1 = 3224 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 3225 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 3226 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 3227 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 3228 QDF_MON_STATUS_RU_0_KNOWN; 3229 3230 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3231 HE_SIG_A_MU_DL_INFO, MCS_OF_SIG_B); 3232 ppdu_info->rx_status.he_flags1 |= value; 3233 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3234 HE_SIG_A_MU_DL_INFO, DCM_OF_SIG_B); 3235 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 3236 ppdu_info->rx_status.he_flags1 |= value; 3237 3238 /* HE-MU-flags2 */ 3239 ppdu_info->rx_status.he_flags2 = 3240 QDF_MON_STATUS_BW_KNOWN; 3241 3242 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3243 HE_SIG_A_MU_DL_INFO, TRANSMIT_BW); 3244 ppdu_info->rx_status.he_flags2 |= value; 3245 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3246 HE_SIG_A_MU_DL_INFO, COMP_MODE_SIG_B); 3247 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 3248 ppdu_info->rx_status.he_flags2 |= value; 3249 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3250 HE_SIG_A_MU_DL_INFO, NUM_SIG_B_SYMBOLS); 3251 value = value - 1; 3252 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 3253 ppdu_info->rx_status.he_flags2 |= value; 3254 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 3255 break; 3256 } 3257 case WIFIPHYRX_HE_SIG_B1_MU_E: 3258 { 3259 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 3260 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 3261 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 3262 3263 ppdu_info->rx_status.he_sig_b_common_known |= 3264 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 3265 /* TODO: Check on the availability of other fields in 3266 * sig_b_common 3267 */ 3268 3269 value = HAL_RX_GET(he_sig_b1_mu_info, 3270 HE_SIG_B1_MU_INFO, RU_ALLOCATION); 3271 ppdu_info->rx_status.he_RU[0] = value; 3272 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 3273 break; 3274 } 3275 case WIFIPHYRX_HE_SIG_B2_MU_E: 3276 { 3277 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 3278 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 3279 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 3280 /* 3281 * Not all "HE" fields can be updated from 3282 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 3283 * to populate rest of the "HE" fields for MU scenarios. 3284 */ 3285 3286 /* HE-data1 */ 3287 ppdu_info->rx_status.he_data1 |= 3288 QDF_MON_STATUS_HE_MCS_KNOWN | 3289 QDF_MON_STATUS_HE_CODING_KNOWN; 3290 3291 /* HE-data2 */ 3292 3293 /* HE-data3 */ 3294 value = HAL_RX_GET(he_sig_b2_mu_info, 3295 HE_SIG_B2_MU_INFO, STA_MCS); 3296 ppdu_info->rx_status.mcs = value; 3297 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 3298 ppdu_info->rx_status.he_data3 |= value; 3299 3300 value = HAL_RX_GET(he_sig_b2_mu_info, 3301 HE_SIG_B2_MU_INFO, STA_CODING); 3302 value = value << QDF_MON_STATUS_CODING_SHIFT; 3303 ppdu_info->rx_status.he_data3 |= value; 3304 3305 /* HE-data4 */ 3306 value = HAL_RX_GET(he_sig_b2_mu_info, 3307 HE_SIG_B2_MU_INFO, STA_ID); 3308 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 3309 ppdu_info->rx_status.he_data4 |= value; 3310 3311 /* HE-data5 */ 3312 3313 /* HE-data6 */ 3314 value = HAL_RX_GET(he_sig_b2_mu_info, 3315 HE_SIG_B2_MU_INFO, NSTS); 3316 /* value n indicates n+1 spatial streams */ 3317 value++; 3318 ppdu_info->rx_status.nss = value; 3319 ppdu_info->rx_status.he_data6 |= value; 3320 3321 break; 3322 } 3323 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 3324 { 3325 uint8_t *he_sig_b2_ofdma_info = 3326 (uint8_t *)rx_tlv + 3327 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 3328 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 3329 3330 /* 3331 * Not all "HE" fields can be updated from 3332 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 3333 * to populate rest of "HE" fields for MU OFDMA scenarios. 3334 */ 3335 3336 /* HE-data1 */ 3337 ppdu_info->rx_status.he_data1 |= 3338 QDF_MON_STATUS_HE_MCS_KNOWN | 3339 QDF_MON_STATUS_HE_DCM_KNOWN | 3340 QDF_MON_STATUS_HE_CODING_KNOWN; 3341 3342 /* HE-data2 */ 3343 ppdu_info->rx_status.he_data2 |= 3344 QDF_MON_STATUS_TXBF_KNOWN; 3345 3346 /* HE-data3 */ 3347 value = HAL_RX_GET(he_sig_b2_ofdma_info, 3348 HE_SIG_B2_OFDMA_INFO, STA_MCS); 3349 ppdu_info->rx_status.mcs = value; 3350 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 3351 ppdu_info->rx_status.he_data3 |= value; 3352 3353 value = HAL_RX_GET(he_sig_b2_ofdma_info, 3354 HE_SIG_B2_OFDMA_INFO, STA_DCM); 3355 he_dcm = value; 3356 value = value << QDF_MON_STATUS_DCM_SHIFT; 3357 ppdu_info->rx_status.he_data3 |= value; 3358 3359 value = HAL_RX_GET(he_sig_b2_ofdma_info, 3360 HE_SIG_B2_OFDMA_INFO, STA_CODING); 3361 value = value << QDF_MON_STATUS_CODING_SHIFT; 3362 ppdu_info->rx_status.he_data3 |= value; 3363 3364 /* HE-data4 */ 3365 value = HAL_RX_GET(he_sig_b2_ofdma_info, 3366 HE_SIG_B2_OFDMA_INFO, STA_ID); 3367 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 3368 ppdu_info->rx_status.he_data4 |= value; 3369 3370 /* HE-data5 */ 3371 value = HAL_RX_GET(he_sig_b2_ofdma_info, 3372 HE_SIG_B2_OFDMA_INFO, TXBF); 3373 value = value << QDF_MON_STATUS_TXBF_SHIFT; 3374 ppdu_info->rx_status.he_data5 |= value; 3375 3376 /* HE-data6 */ 3377 value = HAL_RX_GET(he_sig_b2_ofdma_info, 3378 HE_SIG_B2_OFDMA_INFO, NSTS); 3379 /* value n indicates n+1 spatial streams */ 3380 value++; 3381 ppdu_info->rx_status.nss = value; 3382 ppdu_info->rx_status.he_data6 |= value; 3383 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 3384 break; 3385 } 3386 case WIFIPHYRX_RSSI_LEGACY_E: 3387 { 3388 uint8_t reception_type; 3389 int8_t rssi_value; 3390 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 3391 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, 3392 RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); 3393 3394 ppdu_info->rx_status.rssi_comb = 3395 hal_rx_phy_legacy_get_rssi(hal_soc_hdl, rx_tlv); 3396 3397 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 3398 ppdu_info->rx_status.he_re = 0; 3399 3400 reception_type = HAL_RX_GET_64(rx_tlv, 3401 PHYRX_RSSI_LEGACY, 3402 RECEPTION_TYPE); 3403 switch (reception_type) { 3404 case QDF_RECEPTION_TYPE_ULOFMDA: 3405 ppdu_info->rx_status.ulofdma_flag = 1; 3406 ppdu_info->rx_status.he_data1 = 3407 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 3408 break; 3409 case QDF_RECEPTION_TYPE_ULMIMO: 3410 ppdu_info->rx_status.he_data1 = 3411 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 3412 break; 3413 default: 3414 break; 3415 } 3416 hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); 3417 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3418 RECEIVE_RSSI_INFO, 3419 RSSI_PRI20_CHAIN0); 3420 ppdu_info->rx_status.rssi[0] = rssi_value; 3421 3422 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3423 RECEIVE_RSSI_INFO, 3424 RSSI_PRI20_CHAIN1); 3425 ppdu_info->rx_status.rssi[1] = rssi_value; 3426 3427 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3428 RECEIVE_RSSI_INFO, 3429 RSSI_PRI20_CHAIN2); 3430 ppdu_info->rx_status.rssi[2] = rssi_value; 3431 3432 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3433 RECEIVE_RSSI_INFO, 3434 RSSI_PRI20_CHAIN3); 3435 ppdu_info->rx_status.rssi[3] = rssi_value; 3436 3437 #ifdef DP_BE_NOTYET_WAR 3438 // TODO - this is not preset for kiwi 3439 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3440 RECEIVE_RSSI_INFO, 3441 RSSI_PRI20_CHAIN4); 3442 ppdu_info->rx_status.rssi[4] = rssi_value; 3443 3444 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3445 RECEIVE_RSSI_INFO, 3446 RSSI_PRI20_CHAIN5); 3447 ppdu_info->rx_status.rssi[5] = rssi_value; 3448 3449 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3450 RECEIVE_RSSI_INFO, 3451 RSSI_PRI20_CHAIN6); 3452 ppdu_info->rx_status.rssi[6] = rssi_value; 3453 3454 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3455 RECEIVE_RSSI_INFO, 3456 RSSI_PRI20_CHAIN7); 3457 ppdu_info->rx_status.rssi[7] = rssi_value; 3458 #endif 3459 break; 3460 } 3461 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 3462 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 3463 ppdu_info); 3464 break; 3465 case WIFIPHYRX_GENERIC_U_SIG_E: 3466 hal_rx_parse_u_sig_hdr(hal, rx_tlv, ppdu_info); 3467 break; 3468 case WIFIPHYRX_COMMON_USER_INFO_E: 3469 hal_rx_parse_cmn_usr_info(hal, rx_tlv, ppdu_info); 3470 break; 3471 case WIFIRX_HEADER_E: 3472 { 3473 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 3474 3475 if (ppdu_info->fcs_ok_cnt >= 3476 HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) { 3477 hal_err("Number of MPDUs(%d) per status buff exceeded", 3478 ppdu_info->fcs_ok_cnt); 3479 break; 3480 } 3481 3482 /* Update first_msdu_payload for every mpdu and increment 3483 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV 3484 */ 3485 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload = 3486 rx_tlv; 3487 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len; 3488 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 3489 ppdu_info->msdu_info.payload_len = tlv_len; 3490 ppdu_info->user_id = user_id; 3491 ppdu_info->hdr_len = tlv_len; 3492 ppdu_info->data = rx_tlv; 3493 ppdu_info->data += 4; 3494 3495 /* for every RX_HEADER TLV increment mpdu_cnt */ 3496 com_info->mpdu_cnt++; 3497 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 3498 return HAL_TLV_STATUS_HEADER; 3499 } 3500 case WIFIRX_MPDU_START_E: 3501 { 3502 hal_rx_mon_mpdu_start_t *rx_mpdu_start = rx_tlv; 3503 uint32_t ppdu_id = rx_mpdu_start->rx_mpdu_info_details.phy_ppdu_id; 3504 uint8_t filter_category = 0; 3505 3506 ppdu_info->nac_info.fc_valid = 3507 rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_valid; 3508 3509 ppdu_info->nac_info.to_ds_flag = 3510 rx_mpdu_start->rx_mpdu_info_details.to_ds; 3511 3512 ppdu_info->nac_info.frame_control = 3513 rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_field; 3514 3515 ppdu_info->sw_frame_group_id = 3516 rx_mpdu_start->rx_mpdu_info_details.sw_frame_group_id; 3517 3518 ppdu_info->rx_user_status[user_id].sw_peer_id = 3519 rx_mpdu_start->rx_mpdu_info_details.sw_peer_id; 3520 3521 hal_update_rx_ctrl_frame_stats(ppdu_info, user_id); 3522 3523 if (ppdu_info->sw_frame_group_id == 3524 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 3525 ppdu_info->rx_status.frame_control_info_valid = 3526 ppdu_info->nac_info.fc_valid; 3527 ppdu_info->rx_status.frame_control = 3528 ppdu_info->nac_info.frame_control; 3529 } 3530 3531 hal_get_mac_addr1(rx_mpdu_start, 3532 ppdu_info); 3533 3534 ppdu_info->nac_info.mac_addr2_valid = 3535 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_valid; 3536 3537 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 3538 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_15_0; 3539 3540 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 3541 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_47_16; 3542 3543 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 3544 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 3545 ppdu_info->rx_status.ppdu_len = 3546 rx_mpdu_start->rx_mpdu_info_details.mpdu_length; 3547 } else { 3548 ppdu_info->rx_status.ppdu_len += 3549 rx_mpdu_start->rx_mpdu_info_details.mpdu_length; 3550 } 3551 3552 filter_category = 3553 rx_mpdu_start->rx_mpdu_info_details.rxpcu_mpdu_filter_in_category; 3554 3555 if (filter_category == 0) 3556 ppdu_info->rx_status.rxpcu_filter_pass = 1; 3557 else if (filter_category == 1) 3558 ppdu_info->rx_status.monitor_direct_used = 1; 3559 3560 ppdu_info->rx_user_status[user_id].filter_category = filter_category; 3561 3562 ppdu_info->nac_info.mcast_bcast = 3563 rx_mpdu_start->rx_mpdu_info_details.mcast_bcast; 3564 ppdu_info->mpdu_info[user_id].decap_type = 3565 rx_mpdu_start->rx_mpdu_info_details.decap_type; 3566 3567 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 3568 return HAL_TLV_STATUS_MPDU_START; 3569 } 3570 case WIFIRX_MPDU_END_E: 3571 ppdu_info->user_id = user_id; 3572 ppdu_info->fcs_err = 3573 HAL_RX_GET_64(rx_tlv, RX_MPDU_END, 3574 FCS_ERR); 3575 3576 ppdu_info->mpdu_info[user_id].fcs_err = ppdu_info->fcs_err; 3577 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 3578 return HAL_TLV_STATUS_MPDU_END; 3579 case WIFIRX_MSDU_END_E: { 3580 hal_rx_mon_msdu_end_t *rx_msdu_end = rx_tlv; 3581 3582 if (user_id < HAL_MAX_UL_MU_USERS) { 3583 ppdu_info->rx_msdu_info[user_id].cce_metadata = 3584 rx_msdu_end->cce_metadata; 3585 ppdu_info->rx_msdu_info[user_id].fse_metadata = 3586 rx_msdu_end->fse_metadata; 3587 ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout = 3588 rx_msdu_end->flow_idx_timeout; 3589 ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid = 3590 rx_msdu_end->flow_idx_invalid; 3591 ppdu_info->rx_msdu_info[user_id].flow_idx = 3592 rx_msdu_end->flow_idx; 3593 ppdu_info->msdu[user_id].first_msdu = 3594 rx_msdu_end->first_msdu; 3595 ppdu_info->msdu[user_id].last_msdu = 3596 rx_msdu_end->last_msdu; 3597 ppdu_info->msdu[user_id].msdu_len = 3598 rx_msdu_end->msdu_length; 3599 ppdu_info->msdu[user_id].user_rssi = 3600 rx_msdu_end->user_rssi; 3601 ppdu_info->msdu[user_id].reception_type = 3602 rx_msdu_end->reception_type; 3603 } 3604 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 3605 return HAL_TLV_STATUS_MSDU_END; 3606 } 3607 case WIFIMON_BUFFER_ADDR_E: 3608 hal_rx_status_get_mon_buf_addr(rx_tlv, ppdu_info); 3609 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 3610 return HAL_TLV_STATUS_MON_BUF_ADDR; 3611 case WIFIMON_DROP_E: 3612 hal_rx_update_ppdu_drop_cnt(rx_tlv, ppdu_info); 3613 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 3614 return HAL_TLV_STATUS_MON_DROP; 3615 case 0: 3616 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 3617 return HAL_TLV_STATUS_PPDU_DONE; 3618 case WIFIRX_STATUS_BUFFER_DONE_E: 3619 case WIFIPHYRX_DATA_DONE_E: 3620 case WIFIPHYRX_PKT_END_PART1_E: 3621 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 3622 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3623 3624 default: 3625 hal_debug("unhandled tlv tag %d", tlv_tag); 3626 } 3627 3628 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 3629 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3630 } 3631 3632 static uint32_t 3633 hal_rx_status_process_aggr_tlv(struct hal_soc *hal_soc, 3634 struct hal_rx_ppdu_info *ppdu_info) 3635 { 3636 uint32_t aggr_tlv_tag = ppdu_info->tlv_aggr.tlv_tag; 3637 3638 switch (aggr_tlv_tag) { 3639 case WIFIPHYRX_GENERIC_EHT_SIG_E: 3640 hal_rx_parse_eht_sig_hdr(hal_soc, ppdu_info->tlv_aggr.buf, 3641 ppdu_info); 3642 break; 3643 default: 3644 /* Aggregated TLV cannot be handled */ 3645 qdf_assert(0); 3646 break; 3647 } 3648 3649 ppdu_info->tlv_aggr.in_progress = 0; 3650 ppdu_info->tlv_aggr.cur_len = 0; 3651 3652 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3653 } 3654 3655 static inline bool 3656 hal_rx_status_tlv_should_aggregate(struct hal_soc *hal_soc, uint32_t tlv_tag) 3657 { 3658 switch (tlv_tag) { 3659 case WIFIPHYRX_GENERIC_EHT_SIG_E: 3660 return true; 3661 } 3662 3663 return false; 3664 } 3665 3666 static inline uint32_t 3667 hal_rx_status_aggr_tlv(struct hal_soc *hal_soc, void *rx_tlv_hdr, 3668 struct hal_rx_ppdu_info *ppdu_info, 3669 qdf_nbuf_t nbuf) 3670 { 3671 uint32_t tlv_tag, user_id, tlv_len; 3672 void *rx_tlv; 3673 3674 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 3675 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 3676 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 3677 3678 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV_HDR_SIZE; 3679 3680 if (tlv_len <= HAL_RX_MON_MAX_AGGR_SIZE - ppdu_info->tlv_aggr.cur_len) { 3681 qdf_mem_copy(ppdu_info->tlv_aggr.buf + 3682 ppdu_info->tlv_aggr.cur_len, 3683 rx_tlv, tlv_len); 3684 ppdu_info->tlv_aggr.cur_len += tlv_len; 3685 } else { 3686 dp_err("Length of TLV exceeds max aggregation length"); 3687 qdf_assert(0); 3688 } 3689 3690 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3691 } 3692 3693 static inline uint32_t 3694 hal_rx_status_start_new_aggr_tlv(struct hal_soc *hal_soc, void *rx_tlv_hdr, 3695 struct hal_rx_ppdu_info *ppdu_info, 3696 qdf_nbuf_t nbuf) 3697 { 3698 uint32_t tlv_tag, user_id, tlv_len; 3699 3700 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 3701 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 3702 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 3703 3704 ppdu_info->tlv_aggr.in_progress = 1; 3705 ppdu_info->tlv_aggr.tlv_tag = tlv_tag; 3706 ppdu_info->tlv_aggr.cur_len = 0; 3707 3708 return hal_rx_status_aggr_tlv(hal_soc, rx_tlv_hdr, ppdu_info, nbuf); 3709 } 3710 3711 static inline uint32_t 3712 hal_rx_status_get_tlv_info_wrapper_be(void *rx_tlv_hdr, void *ppduinfo, 3713 hal_soc_handle_t hal_soc_hdl, 3714 qdf_nbuf_t nbuf) 3715 { 3716 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3717 uint32_t tlv_tag, user_id, tlv_len; 3718 struct hal_rx_ppdu_info *ppdu_info = 3719 (struct hal_rx_ppdu_info *)ppduinfo; 3720 3721 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 3722 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 3723 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 3724 3725 /* 3726 * Handle the case where aggregation is in progress 3727 * or the current TLV is one of the TLVs which should be 3728 * aggregated 3729 */ 3730 if (ppdu_info->tlv_aggr.in_progress) { 3731 if (ppdu_info->tlv_aggr.tlv_tag == tlv_tag) { 3732 return hal_rx_status_aggr_tlv(hal, rx_tlv_hdr, 3733 ppdu_info, nbuf); 3734 } else { 3735 /* Finish aggregation of current TLV */ 3736 hal_rx_status_process_aggr_tlv(hal, ppdu_info); 3737 } 3738 } 3739 3740 if (hal_rx_status_tlv_should_aggregate(hal, tlv_tag)) { 3741 return hal_rx_status_start_new_aggr_tlv(hal, rx_tlv_hdr, 3742 ppduinfo, nbuf); 3743 } 3744 3745 return hal_rx_status_get_tlv_info_generic_be(rx_tlv_hdr, ppduinfo, 3746 hal_soc_hdl, nbuf); 3747 } 3748 #endif /* _HAL_BE_API_MON_H_ */ 3749