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Searched refs:write_aux_reg (Results 1 – 11 of 11) sorted by relevance

/linux-6.12.1/arch/arc/mm/
Dtlb.c31 write_aux_reg(ARC_REG_TLBPD1, 0); in __tlb_entry_erase()
34 write_aux_reg(ARC_REG_TLBPD1HI, 0); in __tlb_entry_erase()
36 write_aux_reg(ARC_REG_TLBPD0, 0); in __tlb_entry_erase()
37 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite); in __tlb_entry_erase()
42 write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB); in utlb_invalidate()
51 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid); in tlb_entry_lkup()
53 write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe); in tlb_entry_lkup()
93 write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex); in tlb_entry_insert()
96 write_aux_reg(ARC_REG_TLBPD1, pd1); in tlb_entry_insert()
103 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite); in tlb_entry_insert()
[all …]
Dcache.c220 write_aux_reg(aux_tag, paddr); in __cache_line_loop_v3()
230 write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32); in __cache_line_loop_v3()
234 write_aux_reg(aux_tag, paddr); in __cache_line_loop_v3()
238 write_aux_reg(aux_cmd, vaddr); in __cache_line_loop_v3()
285 write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32); in __cache_line_loop_v4()
287 write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32); in __cache_line_loop_v4()
291 write_aux_reg(aux_cmd, paddr); in __cache_line_loop_v4()
331 write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32); in __cache_line_loop_v4()
333 write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32); in __cache_line_loop_v4()
337 write_aux_reg(e, paddr + sz); /* ENDR is exclusive */ in __cache_line_loop_v4()
[all …]
/linux-6.12.1/arch/arc/kernel/
Dintc-arcv2.c80 write_aux_reg(AUX_IRQ_SELECT, i); in arc_init_IRQ()
81 write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO); in arc_init_IRQ()
89 write_aux_reg(AUX_IRQ_ENABLE, 0); in arc_init_IRQ()
101 write_aux_reg(AUX_IRQ_SELECT, data->hwirq); in arcv2_irq_mask()
102 write_aux_reg(AUX_IRQ_ENABLE, 0); in arcv2_irq_mask()
107 write_aux_reg(AUX_IRQ_SELECT, data->hwirq); in arcv2_irq_unmask()
108 write_aux_reg(AUX_IRQ_ENABLE, 1); in arcv2_irq_unmask()
114 write_aux_reg(AUX_IRQ_SELECT, data->hwirq); in arcv2_irq_enable()
115 write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO); in arcv2_irq_enable()
122 write_aux_reg(AUX_IRQ_ENABLE, 1); in arcv2_irq_enable()
Dperf_event.c271 write_aux_reg(ARC_REG_PCT_INDEX, idx); in arc_pmu_read_counter()
273 write_aux_reg(ARC_REG_PCT_CONTROL, tmp | ARC_REG_PCT_CONTROL_SN); in arc_pmu_read_counter()
394 write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x1); in arc_pmu_enable()
402 write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x0); in arc_pmu_disable()
435 write_aux_reg(ARC_REG_PCT_INDEX, idx); in arc_pmu_event_set_period()
438 write_aux_reg(ARC_REG_PCT_COUNTL, lower_32_bits(value)); in arc_pmu_event_set_period()
439 write_aux_reg(ARC_REG_PCT_COUNTH, upper_32_bits(value)); in arc_pmu_event_set_period()
468 write_aux_reg(ARC_REG_PCT_INT_CTRL, in arc_pmu_start()
472 write_aux_reg(ARC_REG_PCT_INDEX, idx); /* counter # */ in arc_pmu_start()
473 write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config); /* condition */ in arc_pmu_start()
[all …]
Dfpu.c63 write_aux_reg(ARC_REG_FPU_CTRL, 0x100); in fpu_init_task()
66 write_aux_reg(ARC_REG_FPU_STATUS, fwe); in fpu_init_task()
78 write_aux_reg(ARC_REG_FPU_CTRL, restore->ctrl); in fpu_save_restore()
79 write_aux_reg(ARC_REG_FPU_STATUS, (fwe | restore->status)); in fpu_save_restore()
Dintc-compact.c35 write_aux_reg(AUX_IRQ_LEV, level_mask); in arc_init_IRQ()
49 write_aux_reg(AUX_IENABLE, ienb); in arc_init_IRQ()
70 write_aux_reg(AUX_IENABLE, ienb); in arc_irq_mask()
79 write_aux_reg(AUX_IENABLE, ienb); in arc_irq_unmask()
/linux-6.12.1/drivers/clocksource/
Darc_timer.c182 write_aux_reg(AUX_RTC_CTRL, 1); in arc_cs_setup_rtc()
226 write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX); in arc_cs_setup_timer1()
227 write_aux_reg(ARC_REG_TIMER1_CNT, 0); in arc_cs_setup_timer1()
228 write_aux_reg(ARC_REG_TIMER1_CTRL, ARC_TIMER_CTRL_NH); in arc_cs_setup_timer1()
245 write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles); in arc_timer_event_setup()
246 write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */ in arc_timer_event_setup()
248 write_aux_reg(ARC_REG_TIMER0_CTRL, ARC_TIMER_CTRL_IE | ARC_TIMER_CTRL_NH); in arc_timer_event_setup()
297 write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | ARC_TIMER_CTRL_NH); in timer_irq_handler()
/linux-6.12.1/include/soc/arc/
Daux.h14 #define write_aux_reg(r, v) __builtin_arc_sr((unsigned int)(v), r) macro
27 static inline void write_aux_reg(u32 r, u32 v) in write_aux_reg() function
51 write_aux_reg(reg, tmp); \
Dmcip.h119 write_aux_reg(ARC_REG_MCIP_WDATA, data); in __mcip_cmd_data()
/linux-6.12.1/arch/arc/include/asm/
Dirqflags-arcv2.h83 write_aux_reg(AUX_IRQ_ACT, irqact & ~0xffff); in arch_local_irq_enable()
134 write_aux_reg(AUX_IRQ_HINT, irq); in arc_softirq_trigger()
139 write_aux_reg(AUX_IRQ_HINT, 0); in arc_softirq_clear()
Dmmu-arcv2.h84 write_aux_reg(ARC_REG_PID, asid | MMU_ENABLE); in mmu_setup_asid()
91 write_aux_reg(ARC_REG_SCRATCH_DATA0, (unsigned int)pgd); in mmu_setup_pgd()