220 		write_aux_reg(aux_tag, paddr);  in __cache_line_loop_v3()
230 		write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);  in __cache_line_loop_v3()
234 			write_aux_reg(aux_tag, paddr);  in __cache_line_loop_v3()
238 		write_aux_reg(aux_cmd, vaddr);  in __cache_line_loop_v3()
285 			write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);  in __cache_line_loop_v4()
287 			write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);  in __cache_line_loop_v4()
291 		write_aux_reg(aux_cmd, paddr);  in __cache_line_loop_v4()
331 			write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);  in __cache_line_loop_v4()
333 			write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);  in __cache_line_loop_v4()
337 	write_aux_reg(e, paddr + sz);	/* ENDR is exclusive */  in __cache_line_loop_v4()
338 	write_aux_reg(s, paddr);  in __cache_line_loop_v4()
371 		write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH);  in __before_dc_op()
395 	write_aux_reg(ctl, val);  in __before_dc_op()
413 			write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH);  in __after_dc_op()
434 	write_aux_reg(aux, 0x1);  in __dc_entire_op()
444 	write_aux_reg(r, read_aux_reg(r) | DC_CTRL_DIS);  in __dc_disable()
451 	write_aux_reg(r, read_aux_reg(r) & ~DC_CTRL_DIS);  in __dc_enable()
491 	write_aux_reg(ARC_REG_IC_IVIC, 1);  in __ic_entire_inv()
582 	write_aux_reg(ARC_REG_SLC_CTRL, ctrl);  in slc_op_rgn()
591 		write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end));  in slc_op_rgn()
593 	write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end));  in slc_op_rgn()
596 		write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr));  in slc_op_rgn()
598 	write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr));  in slc_op_rgn()
636 	write_aux_reg(ARC_REG_SLC_CTRL, ctrl);  in slc_op_line()
646 		write_aux_reg(cmd, paddr);  in slc_op_line()
672 	write_aux_reg(r, ctrl);  in slc_entire_op()
675 		write_aux_reg(ARC_REG_SLC_INVALIDATE, 0x1);  in slc_entire_op()
677 		write_aux_reg(ARC_REG_SLC_FLUSH, 0x1);  in slc_entire_op()
691 	write_aux_reg(r, read_aux_reg(r) | SLC_CTRL_DIS);  in arc_slc_disable()
698 	write_aux_reg(r, read_aux_reg(r) & ~SLC_CTRL_DIS);  in arc_slc_enable()
972 	write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, order_base_2(mem_sz >> 10) - 2);  in arc_ioc_setup()
980 	write_aux_reg(ARC_REG_IO_COH_AP0_BASE, ioc_base >> 12);  in arc_ioc_setup()
981 	write_aux_reg(ARC_REG_IO_COH_PARTIAL, ARC_IO_COH_PARTIAL_BIT);  in arc_ioc_setup()
982 	write_aux_reg(ARC_REG_IO_COH_ENABLE, ARC_IO_COH_ENABLE_BIT);  in arc_ioc_setup()
1084 			write_aux_reg(ARC_REG_IC_PTAG_HI, 0);  in arc_cache_init()
1087 			write_aux_reg(ARC_REG_DC_PTAG_HI, 0);  in arc_cache_init()
1090 			write_aux_reg(ARC_REG_SLC_RGN_END1, 0);  in arc_cache_init()
1091 			write_aux_reg(ARC_REG_SLC_RGN_START1, 0);  in arc_cache_init()