Lines Matching refs:write_aux_reg
31 write_aux_reg(ARC_REG_TLBPD1, 0); in __tlb_entry_erase()
34 write_aux_reg(ARC_REG_TLBPD1HI, 0); in __tlb_entry_erase()
36 write_aux_reg(ARC_REG_TLBPD0, 0); in __tlb_entry_erase()
37 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite); in __tlb_entry_erase()
42 write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB); in utlb_invalidate()
51 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid); in tlb_entry_lkup()
53 write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe); in tlb_entry_lkup()
93 write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex); in tlb_entry_insert()
96 write_aux_reg(ARC_REG_TLBPD1, pd1); in tlb_entry_insert()
103 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite); in tlb_entry_insert()
110 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid | _PAGE_PRESENT); in tlb_entry_erase()
111 write_aux_reg(ARC_REG_TLBCOMMAND, TLBDeleteEntry); in tlb_entry_erase()
116 write_aux_reg(ARC_REG_TLBPD0, pd0); in tlb_entry_insert()
119 write_aux_reg(ARC_REG_TLBPD1, pd1); in tlb_entry_insert()
121 write_aux_reg(ARC_REG_TLBPD1, pd1 & 0xFFFFFFFF); in tlb_entry_insert()
122 write_aux_reg(ARC_REG_TLBPD1HI, (u64)pd1 >> 32); in tlb_entry_insert()
125 write_aux_reg(ARC_REG_TLBCOMMAND, TLBInsertEntry); in tlb_entry_insert()
144 write_aux_reg(ARC_REG_TLBPD1, 0); in local_flush_tlb_all()
147 write_aux_reg(ARC_REG_TLBPD1HI, 0); in local_flush_tlb_all()
149 write_aux_reg(ARC_REG_TLBPD0, 0); in local_flush_tlb_all()
153 write_aux_reg(ARC_REG_TLBINDEX, entry); in local_flush_tlb_all()
154 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWriteNI); in local_flush_tlb_all()
161 write_aux_reg(ARC_REG_TLBPD0, _PAGE_HW_SZ); in local_flush_tlb_all()
164 write_aux_reg(ARC_REG_TLBINDEX, entry); in local_flush_tlb_all()
165 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWriteNI); in local_flush_tlb_all()
664 write_aux_reg(ARC_REG_TLBPD1HI, 0); in arc_mmu_init()
714 write_aux_reg(ARC_REG_TLBINDEX, in do_tlb_overlap_fault()
716 write_aux_reg(ARC_REG_TLBCOMMAND, TLBRead); in do_tlb_overlap_fault()
747 write_aux_reg(ARC_REG_TLBINDEX, in do_tlb_overlap_fault()