271 	write_aux_reg(ARC_REG_PCT_INDEX, idx);  in arc_pmu_read_counter()
273 	write_aux_reg(ARC_REG_PCT_CONTROL, tmp | ARC_REG_PCT_CONTROL_SN);  in arc_pmu_read_counter()
394 	write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x1);  in arc_pmu_enable()
402 	write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x0);  in arc_pmu_disable()
435 	write_aux_reg(ARC_REG_PCT_INDEX, idx);  in arc_pmu_event_set_period()
438 	write_aux_reg(ARC_REG_PCT_COUNTL, lower_32_bits(value));  in arc_pmu_event_set_period()
439 	write_aux_reg(ARC_REG_PCT_COUNTH, upper_32_bits(value));  in arc_pmu_event_set_period()
468 		write_aux_reg(ARC_REG_PCT_INT_CTRL,  in arc_pmu_start()
472 	write_aux_reg(ARC_REG_PCT_INDEX, idx);		/* counter # */  in arc_pmu_start()
473 	write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config);	/* condition */  in arc_pmu_start()
487 		write_aux_reg(ARC_REG_PCT_INT_ACT, BIT(idx));  in arc_pmu_stop()
488 		write_aux_reg(ARC_REG_PCT_INT_CTRL,  in arc_pmu_stop()
494 		write_aux_reg(ARC_REG_PCT_INDEX, idx);  in arc_pmu_stop()
497 		write_aux_reg(ARC_REG_PCT_CONFIG, 0);  in arc_pmu_stop()
535 	write_aux_reg(ARC_REG_PCT_INDEX, idx);  in arc_pmu_add()
541 		write_aux_reg(ARC_REG_PCT_INT_CNTL,  in arc_pmu_add()
543 		write_aux_reg(ARC_REG_PCT_INT_CNTH,  in arc_pmu_add()
547 	write_aux_reg(ARC_REG_PCT_CONFIG, 0);  in arc_pmu_add()
548 	write_aux_reg(ARC_REG_PCT_COUNTL, 0);  in arc_pmu_add()
549 	write_aux_reg(ARC_REG_PCT_COUNTH, 0);  in arc_pmu_add()
585 		write_aux_reg(ARC_REG_PCT_INT_ACT, BIT(idx));  in arc_pmu_intr()
592 		write_aux_reg(ARC_REG_PCT_INT_CTRL,  in arc_pmu_intr()
631 	write_aux_reg(ARC_REG_PCT_INT_ACT, 0xffffffff);  in arc_cpu_pmu_irq_init()
778 		write_aux_reg(ARC_REG_CC_INDEX, i);  in arc_pmu_device_probe()