Home
last modified time | relevance | path

Searched refs:reg_val (Results 1 – 25 of 409) sorted by relevance

12345678910>>...17

/linux-6.12.1/drivers/net/ethernet/samsung/sxgbe/
Dsxgbe_mtl.c23 u32 reg_val; in sxgbe_mtl_init() local
25 reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
26 reg_val &= ETS_RST; in sxgbe_mtl_init()
31 reg_val &= ETS_WRR; in sxgbe_mtl_init()
34 reg_val |= ETS_WFQ; in sxgbe_mtl_init()
37 reg_val |= ETS_DWRR; in sxgbe_mtl_init()
40 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
44 reg_val &= RAA_SP; in sxgbe_mtl_init()
47 reg_val |= RAA_WSP; in sxgbe_mtl_init()
50 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
[all …]
/linux-6.12.1/drivers/input/keyboard/
Dimx_keypad.c83 unsigned short reg_val; in imx_keypad_scan_matrix() local
94 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
95 reg_val |= 0xff00; in imx_keypad_scan_matrix()
96 writew(reg_val, keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
98 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
99 reg_val &= ~((keypad->cols_en_mask & 0xff) << 8); in imx_keypad_scan_matrix()
100 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
104 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
105 reg_val |= (keypad->cols_en_mask & 0xff) << 8; in imx_keypad_scan_matrix()
106 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
[all …]
/linux-6.12.1/drivers/net/ethernet/marvell/octeon_ep_vf/
Doctep_vf_cnxk.c141 u64 reg_val; in octep_vf_init_config_cnxk_vf() local
143 reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_CONTROL(0)); in octep_vf_init_config_cnxk_vf()
144 conf->ring_cfg.max_io_rings = (reg_val >> CNXK_VF_R_IN_CTL_RPVF_POS) & in octep_vf_init_config_cnxk_vf()
168 u64 reg_val; in octep_vf_setup_iq_regs_cnxk() local
170 reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_CONTROL(iq_no)); in octep_vf_setup_iq_regs_cnxk()
173 if (!(reg_val & CNXK_VF_R_IN_CTL_IDLE)) { in octep_vf_setup_iq_regs_cnxk()
175 reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_CONTROL(iq_no)); in octep_vf_setup_iq_regs_cnxk()
176 } while (!(reg_val & CNXK_VF_R_IN_CTL_IDLE)); in octep_vf_setup_iq_regs_cnxk()
178 reg_val |= CNXK_VF_R_IN_CTL_RDSIZE; in octep_vf_setup_iq_regs_cnxk()
179 reg_val |= CNXK_VF_R_IN_CTL_IS_64B; in octep_vf_setup_iq_regs_cnxk()
[all …]
Doctep_vf_cn9k.c139 u64 reg_val; in octep_vf_init_config_cn93_vf() local
141 reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_IN_CONTROL(0)); in octep_vf_init_config_cn93_vf()
142 conf->ring_cfg.max_io_rings = (reg_val >> CN93_VF_R_IN_CTL_RPVF_POS) & in octep_vf_init_config_cn93_vf()
165 u64 reg_val; in octep_vf_setup_iq_regs_cn93() local
167 reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_IN_CONTROL(iq_no)); in octep_vf_setup_iq_regs_cn93()
170 if (!(reg_val & CN93_VF_R_IN_CTL_IDLE)) { in octep_vf_setup_iq_regs_cn93()
172 reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_IN_CONTROL(iq_no)); in octep_vf_setup_iq_regs_cn93()
173 } while (!(reg_val & CN93_VF_R_IN_CTL_IDLE)); in octep_vf_setup_iq_regs_cn93()
175 reg_val |= CN93_VF_R_IN_CTL_RDSIZE; in octep_vf_setup_iq_regs_cn93()
176 reg_val |= CN93_VF_R_IN_CTL_IS_64B; in octep_vf_setup_iq_regs_cn93()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/
Ddc_helper.c144 uint32_t reg_val) in dmub_reg_value_burst_set_pack() argument
162 cmd_buf->write_values[offload->reg_seq_count] = reg_val; in dmub_reg_value_burst_set_pack()
227 uint32_t reg_val; in generic_reg_update_ex() local
243 reg_val = dm_read_reg(ctx, addr); in generic_reg_update_ex()
244 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; in generic_reg_update_ex()
245 dm_write_reg(ctx, addr, reg_val); in generic_reg_update_ex()
246 return reg_val; in generic_reg_update_ex()
250 uint32_t addr, uint32_t reg_val, int n, in generic_reg_set_ex() argument
265 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; in generic_reg_set_ex()
269 return dmub_reg_value_burst_set_pack(ctx, addr, reg_val); in generic_reg_set_ex()
[all …]
/linux-6.12.1/drivers/media/dvb-frontends/
Daf9033_priv.h19 struct reg_val { struct
87 static const struct reg_val ofsm_init[] = {
202 static const struct reg_val tuner_init_tua9001[] = {
246 static const struct reg_val tuner_init_fc0011[] = {
309 static const struct reg_val tuner_init_fc0012[] = {
354 static const struct reg_val tuner_init_mxl5007t[] = {
391 static const struct reg_val tuner_init_tda18218[] = {
427 static const struct reg_val tuner_init_fc2580[] = {
467 static const struct reg_val ofsm_init_it9135_v1[] = {
582 static const struct reg_val tuner_init_it9135_38[] = {
[all …]
/linux-6.12.1/drivers/net/ethernet/marvell/octeon_ep/
Doctep_cnxk_pf.c287 u64 reg_val; in octep_setup_iq_regs_cnxk_pf() local
290 reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_CONTROL(iq_no)); in octep_setup_iq_regs_cnxk_pf()
293 if (!(reg_val & CNXK_R_IN_CTL_IDLE)) { in octep_setup_iq_regs_cnxk_pf()
295 reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_CONTROL(iq_no)); in octep_setup_iq_regs_cnxk_pf()
296 } while (!(reg_val & CNXK_R_IN_CTL_IDLE)); in octep_setup_iq_regs_cnxk_pf()
299 reg_val |= CNXK_R_IN_CTL_RDSIZE; in octep_setup_iq_regs_cnxk_pf()
300 reg_val |= CNXK_R_IN_CTL_IS_64B; in octep_setup_iq_regs_cnxk_pf()
301 reg_val |= CNXK_R_IN_CTL_ESR; in octep_setup_iq_regs_cnxk_pf()
302 octep_write_csr64(oct, CNXK_SDP_R_IN_CONTROL(iq_no), reg_val); in octep_setup_iq_regs_cnxk_pf()
325 reg_val = CFG_GET_IQ_INTR_THRESHOLD(oct->conf) & 0xffffffff; in octep_setup_iq_regs_cnxk_pf()
[all …]
Doctep_cn9k_pf.c267 u64 reg_val; in octep_setup_iq_regs_cn93_pf() local
270 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no)); in octep_setup_iq_regs_cn93_pf()
273 if (!(reg_val & CN93_R_IN_CTL_IDLE)) { in octep_setup_iq_regs_cn93_pf()
275 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no)); in octep_setup_iq_regs_cn93_pf()
276 } while (!(reg_val & CN93_R_IN_CTL_IDLE)); in octep_setup_iq_regs_cn93_pf()
279 reg_val |= CN93_R_IN_CTL_RDSIZE; in octep_setup_iq_regs_cn93_pf()
280 reg_val |= CN93_R_IN_CTL_IS_64B; in octep_setup_iq_regs_cn93_pf()
281 reg_val |= CN93_R_IN_CTL_ESR; in octep_setup_iq_regs_cn93_pf()
282 octep_write_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no), reg_val); in octep_setup_iq_regs_cn93_pf()
305 reg_val = CFG_GET_IQ_INTR_THRESHOLD(oct->conf) & 0xffffffff; in octep_setup_iq_regs_cn93_pf()
[all …]
/linux-6.12.1/drivers/spi/
Dspi-mt65xx.c272 u32 reg_val; in mtk_spi_reset() local
275 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
276 reg_val |= SPI_CMD_RST; in mtk_spi_reset()
277 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
279 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
280 reg_val &= ~SPI_CMD_RST; in mtk_spi_reset()
281 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
291 u32 reg_val; in mtk_spi_set_hw_cs_timing() local
310 reg_val = readl(mdata->base + SPI_CFG0_REG); in mtk_spi_set_hw_cs_timing()
314 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); in mtk_spi_set_hw_cs_timing()
[all …]
Dspi-slave-mt27xx.c100 u32 reg_val; in mtk_spi_slave_disable_dma() local
102 reg_val = readl(mdata->base + SPIS_DMA_CFG_REG); in mtk_spi_slave_disable_dma()
103 reg_val &= ~RX_DMA_EN; in mtk_spi_slave_disable_dma()
104 reg_val &= ~TX_DMA_EN; in mtk_spi_slave_disable_dma()
105 writel(reg_val, mdata->base + SPIS_DMA_CFG_REG); in mtk_spi_slave_disable_dma()
110 u32 reg_val; in mtk_spi_slave_disable_xfer() local
112 reg_val = readl(mdata->base + SPIS_CFG_REG); in mtk_spi_slave_disable_xfer()
113 reg_val &= ~SPIS_TX_EN; in mtk_spi_slave_disable_xfer()
114 reg_val &= ~SPIS_RX_EN; in mtk_spi_slave_disable_xfer()
115 writel(reg_val, mdata->base + SPIS_CFG_REG); in mtk_spi_slave_disable_xfer()
[all …]
/linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_vbif.c63 u32 reg_val; in dpu_hw_set_mem_type() local
81 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_mem_type()
82 reg_val &= ~(0x7 << bit_off); in dpu_hw_set_mem_type()
83 reg_val |= (value & 0x7) << bit_off; in dpu_hw_set_mem_type()
84 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type()
91 u32 reg_val; in dpu_hw_set_limit_conf() local
102 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_limit_conf()
103 reg_val &= ~(0xFF << bit_off); in dpu_hw_set_limit_conf()
104 reg_val |= (limit) << bit_off; in dpu_hw_set_limit_conf()
105 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_limit_conf()
[all …]
/linux-6.12.1/drivers/net/ethernet/allwinner/
Dsun4i-emac.c105 unsigned int reg_val; in emac_update_speed() local
108 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
109 reg_val &= ~EMAC_MAC_SUPP_100M; in emac_update_speed()
111 reg_val |= EMAC_MAC_SUPP_100M; in emac_update_speed()
112 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
118 unsigned int reg_val; in emac_update_duplex() local
121 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
122 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex()
124 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex()
125 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
[all …]
/linux-6.12.1/sound/drivers/opl3/
Dopl3_synth.c394 unsigned char reg_val; in snd_opl3_play_note() local
414 reg_val = (unsigned char) note->fnum; in snd_opl3_play_note()
416 opl3->command(opl3, opl3_reg, reg_val); in snd_opl3_play_note()
418 reg_val = 0x00; in snd_opl3_play_note()
421 reg_val |= OPL3_KEYON_BIT; in snd_opl3_play_note()
423 reg_val |= (note->octave << 2) & OPL3_BLOCKNUM_MASK; in snd_opl3_play_note()
425 reg_val |= (unsigned char) (note->fnum >> 8) & OPL3_FNUM_HIGH_MASK; in snd_opl3_play_note()
429 opl3->command(opl3, opl3_reg, reg_val); in snd_opl3_play_note()
442 unsigned char reg_val; in snd_opl3_set_voice() local
468 reg_val = 0x00; in snd_opl3_set_voice()
[all …]
/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_mocs.c273 u32 reg_val; in xelp_lncf_dump() local
279 reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i)); in xelp_lncf_dump()
281 reg_val = xe_mmio_read32(gt, XELP_LNCFCMOCS(i)); in xelp_lncf_dump()
285 !!(reg_val & L3_ESC_MASK), in xelp_lncf_dump()
286 REG_FIELD_GET(L3_SCC_MASK, reg_val), in xelp_lncf_dump()
287 REG_FIELD_GET(L3_CACHEABILITY_MASK, reg_val), in xelp_lncf_dump()
288 reg_val); in xelp_lncf_dump()
292 !!(reg_val & L3_UPPER_IDX_ESC_MASK), in xelp_lncf_dump()
293 REG_FIELD_GET(L3_UPPER_IDX_SCC_MASK, reg_val), in xelp_lncf_dump()
294 REG_FIELD_GET(L3_UPPER_IDX_CACHEABILITY_MASK, reg_val), in xelp_lncf_dump()
[all …]
/linux-6.12.1/arch/riscv/kvm/
Dvcpu_onereg.c211 unsigned long reg_val; in kvm_riscv_vcpu_get_reg_config() local
218 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK; in kvm_riscv_vcpu_get_reg_config()
223 reg_val = riscv_cbom_block_size; in kvm_riscv_vcpu_get_reg_config()
228 reg_val = riscv_cboz_block_size; in kvm_riscv_vcpu_get_reg_config()
231 reg_val = vcpu->arch.mvendorid; in kvm_riscv_vcpu_get_reg_config()
234 reg_val = vcpu->arch.marchid; in kvm_riscv_vcpu_get_reg_config()
237 reg_val = vcpu->arch.mimpid; in kvm_riscv_vcpu_get_reg_config()
240 reg_val = satp_mode >> SATP_MODE_SHIFT; in kvm_riscv_vcpu_get_reg_config()
246 if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_config()
260 unsigned long i, isa_ext, reg_val; in kvm_riscv_vcpu_set_reg_config() local
[all …]
/linux-6.12.1/drivers/gpu/drm/msm/hdmi/
Dhdmi_hdcp.c45 u32 reg_val; member
199 u32 reg_val, hdcp_int_status; in msm_hdmi_hdcp_irq() local
203 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_INT_CTRL); in msm_hdmi_hdcp_irq()
204 hdcp_int_status = reg_val & HDCP_INT_STATUS_MASK; in msm_hdmi_hdcp_irq()
210 reg_val |= hdcp_int_status << 1; in msm_hdmi_hdcp_irq()
213 reg_val |= HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK; in msm_hdmi_hdcp_irq()
214 hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, reg_val); in msm_hdmi_hdcp_irq()
228 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); in msm_hdmi_hdcp_irq()
230 __func__, reg_val); in msm_hdmi_hdcp_irq()
284 u32 reg_val, failure, nack0; in msm_reset_hdcp_ddc_failures() local
[all …]
/linux-6.12.1/arch/arm/mach-qcom/
Dplatsmp.c84 u32 reg_val; in cortex_a7_release_secondary() local
103 reg_val = CORE_RST | COREPOR_RST | CLAMP | CORE_MEM_CLAMP; in cortex_a7_release_secondary()
104 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
111 reg_val &= ~CORE_MEM_CLAMP; in cortex_a7_release_secondary()
112 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
113 reg_val |= L2DT_SLP; in cortex_a7_release_secondary()
114 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
117 reg_val = (reg_val | BIT(17)) & ~CLAMP; in cortex_a7_release_secondary()
118 writel(reg_val, reg + APCS_CPU_PWR_CTL); in cortex_a7_release_secondary()
122 reg_val &= ~(CORE_RST | COREPOR_RST); in cortex_a7_release_secondary()
[all …]
/linux-6.12.1/arch/powerpc/platforms/powernv/
Dopal-fadump.h83 __be64 reg_val; member
88 u64 reg_val) in opal_fadump_set_regval_regnum() argument
92 regs->gpr[reg_num] = reg_val; in opal_fadump_set_regval_regnum()
98 regs->ctr = reg_val; in opal_fadump_set_regval_regnum()
101 regs->link = reg_val; in opal_fadump_set_regval_regnum()
104 regs->xer = reg_val; in opal_fadump_set_regval_regnum()
107 regs->dar = reg_val; in opal_fadump_set_regval_regnum()
110 regs->dsisr = reg_val; in opal_fadump_set_regval_regnum()
113 regs->nip = reg_val; in opal_fadump_set_regval_regnum()
116 regs->msr = reg_val; in opal_fadump_set_regval_regnum()
[all …]
/linux-6.12.1/arch/mips/pci/
Dfixup-malta.c70 unsigned char reg_val; in malta_piix_func0_fixup() local
84 pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, &reg_val); in malta_piix_func0_fixup()
85 if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE) in malta_piix_func0_fixup()
88 pci_irq[PCIA+i] = piixirqmap[reg_val & in malta_piix_func0_fixup()
98 pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, &reg_val); in malta_piix_func0_fixup()
99 pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val | in malta_piix_func0_fixup()
109 pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val); in malta_piix_func0_fixup()
110 reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT; in malta_piix_func0_fixup()
111 pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val); in malta_piix_func0_fixup()
124 unsigned char reg_val; in malta_piix_func1_fixup() local
[all …]
/linux-6.12.1/drivers/hwmon/
Dltc2992.c410 int reg_val; in ltc2992_get_voltage() local
412 reg_val = ltc2992_read_reg(st, reg, 2); in ltc2992_get_voltage()
413 if (reg_val < 0) in ltc2992_get_voltage()
414 return reg_val; in ltc2992_get_voltage()
416 reg_val = reg_val >> 4; in ltc2992_get_voltage()
417 *val = DIV_ROUND_CLOSEST(reg_val * scale, 1000); in ltc2992_get_voltage()
432 int reg_val; in ltc2992_read_gpio_alarm() local
440 reg_val = ltc2992_read_reg(st, ltc2992_gpio_addr_map[nr_gpio].alarm, 1); in ltc2992_read_gpio_alarm()
441 if (reg_val < 0) in ltc2992_read_gpio_alarm()
442 return reg_val; in ltc2992_read_gpio_alarm()
[all …]
/linux-6.12.1/drivers/ata/
Dahci_sunxi.c55 u32 reg_val; in sunxi_clrbits() local
57 reg_val = readl(reg); in sunxi_clrbits()
58 reg_val &= ~(clr_val); in sunxi_clrbits()
59 writel(reg_val, reg); in sunxi_clrbits()
64 u32 reg_val; in sunxi_setbits() local
66 reg_val = readl(reg); in sunxi_setbits()
67 reg_val |= set_val; in sunxi_setbits()
68 writel(reg_val, reg); in sunxi_setbits()
73 u32 reg_val; in sunxi_clrsetbits() local
75 reg_val = readl(reg); in sunxi_clrsetbits()
[all …]
/linux-6.12.1/drivers/net/ethernet/cavium/liquidio/
Dcn23xx_vf_device.c68 u64 reg_val = octeon_read_csr64(oct, in cn23xx_vf_reset_io_queues() local
70 while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) && in cn23xx_vf_reset_io_queues()
71 !(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) && in cn23xx_vf_reset_io_queues()
73 WRITE_ONCE(reg_val, octeon_read_csr64( in cn23xx_vf_reset_io_queues()
83 WRITE_ONCE(reg_val, READ_ONCE(reg_val) & in cn23xx_vf_reset_io_queues()
86 READ_ONCE(reg_val)); in cn23xx_vf_reset_io_queues()
88 WRITE_ONCE(reg_val, octeon_read_csr64( in cn23xx_vf_reset_io_queues()
90 if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) { in cn23xx_vf_reset_io_queues()
153 u32 reg_val; in cn23xx_vf_setup_global_output_regs() local
160 reg_val = in cn23xx_vf_setup_global_output_regs()
[all …]
/linux-6.12.1/drivers/staging/media/starfive/camss/
Dstf-isp-hw-ops.c15 u32 reg_val, reg_add; in stf_isp_config_obc() local
19 reg_val = GAIN_D_POINT(0x40) | GAIN_C_POINT(0x40) | in stf_isp_config_obc()
22 stf_isp_reg_write(stfcamss, reg_add, reg_val); in stf_isp_config_obc()
26 reg_val = OFFSET_D_POINT(0) | OFFSET_C_POINT(0) | in stf_isp_config_obc()
29 stf_isp_reg_write(stfcamss, reg_add, reg_val); in stf_isp_config_obc()
120 u32 reg_val, reg_add; in stf_isp_config_awb() local
124 reg_val = AWB_X_SYMBOL_H(symbol_h) | AWB_X_SYMBOL_L(symbol_l); in stf_isp_config_awb()
127 stf_isp_reg_write(stfcamss, reg_add, reg_val); in stf_isp_config_awb()
132 reg_val = AWB_Y_SYMBOL_H(symbol_h) | AWB_Y_SYMBOL_L(symbol_l); in stf_isp_config_awb()
135 stf_isp_reg_write(stfcamss, reg_add, reg_val); in stf_isp_config_awb()
[all …]
/linux-6.12.1/drivers/video/backlight/
Dlm3639_bl.c50 unsigned int reg_val; in lm3639_chip_init() local
60 reg_val = (pdata->pin_pwm & 0x40) | pdata->pin_strobe | pdata->pin_tx; in lm3639_chip_init()
61 ret = regmap_update_bits(pchip->regmap, REG_IO_CTRL, 0x7C, reg_val); in lm3639_chip_init()
76 reg_val = pdata->fled_pins; in lm3639_chip_init()
77 reg_val |= pdata->bled_pins; in lm3639_chip_init()
79 reg_val = pdata->fled_pins; in lm3639_chip_init()
80 reg_val |= pdata->bled_pins | 0x01; in lm3639_chip_init()
83 ret = regmap_update_bits(pchip->regmap, REG_ENABLE, 0x79, reg_val); in lm3639_chip_init()
97 unsigned int reg_val; in lm3639_bled_update_status() local
101 ret = regmap_read(pchip->regmap, REG_FLAG, &reg_val); in lm3639_bled_update_status()
[all …]
/linux-6.12.1/sound/soc/amd/raven/
Dacp3x-i2s.c81 u32 reg_val, frmt_reg; in acp3x_i2s_hwparams() local
116 reg_val = mmACP_BTTDM_ITER; in acp3x_i2s_hwparams()
121 reg_val = mmACP_I2STDM_ITER; in acp3x_i2s_hwparams()
127 reg_val = mmACP_BTTDM_IRER; in acp3x_i2s_hwparams()
132 reg_val = mmACP_I2STDM_IRER; in acp3x_i2s_hwparams()
137 val = rv_readl(rtd->acp3x_base + reg_val); in acp3x_i2s_hwparams()
138 rv_writel(val | 0x2, rtd->acp3x_base + reg_val); in acp3x_i2s_hwparams()
141 val = rv_readl(rtd->acp3x_base + reg_val); in acp3x_i2s_hwparams()
144 rv_writel(val, rtd->acp3x_base + reg_val); in acp3x_i2s_hwparams()
152 u32 ret, val, period_bytes, reg_val, ier_val, water_val; in acp3x_i2s_trigger() local
[all …]

12345678910>>...17