Lines Matching refs:reg_val
272 u32 reg_val; in mtk_spi_reset() local
275 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
276 reg_val |= SPI_CMD_RST; in mtk_spi_reset()
277 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
279 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
280 reg_val &= ~SPI_CMD_RST; in mtk_spi_reset()
281 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
291 u32 reg_val; in mtk_spi_set_hw_cs_timing() local
310 reg_val = readl(mdata->base + SPI_CFG0_REG); in mtk_spi_set_hw_cs_timing()
314 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); in mtk_spi_set_hw_cs_timing()
315 reg_val |= (((hold - 1) & 0xffff) in mtk_spi_set_hw_cs_timing()
320 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); in mtk_spi_set_hw_cs_timing()
321 reg_val |= (((setup - 1) & 0xffff) in mtk_spi_set_hw_cs_timing()
327 reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET); in mtk_spi_set_hw_cs_timing()
328 reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); in mtk_spi_set_hw_cs_timing()
332 reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET); in mtk_spi_set_hw_cs_timing()
333 reg_val |= (((setup - 1) & 0xff) in mtk_spi_set_hw_cs_timing()
337 writel(reg_val, mdata->base + SPI_CFG0_REG); in mtk_spi_set_hw_cs_timing()
342 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_set_hw_cs_timing()
343 reg_val &= ~SPI_CFG1_CS_IDLE_MASK; in mtk_spi_set_hw_cs_timing()
344 reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); in mtk_spi_set_hw_cs_timing()
345 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_set_hw_cs_timing()
355 u32 reg_val; in mtk_spi_hw_init() local
362 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_hw_init()
365 reg_val |= SPI_CMD_IPM_NONIDLE_MODE; in mtk_spi_hw_init()
367 reg_val |= SPI_CMD_IPM_SPIM_LOOP; in mtk_spi_hw_init()
369 reg_val &= ~SPI_CMD_IPM_SPIM_LOOP; in mtk_spi_hw_init()
373 reg_val |= SPI_CMD_CPHA; in mtk_spi_hw_init()
375 reg_val &= ~SPI_CMD_CPHA; in mtk_spi_hw_init()
377 reg_val |= SPI_CMD_CPOL; in mtk_spi_hw_init()
379 reg_val &= ~SPI_CMD_CPOL; in mtk_spi_hw_init()
383 reg_val &= ~SPI_CMD_TXMSBF; in mtk_spi_hw_init()
384 reg_val &= ~SPI_CMD_RXMSBF; in mtk_spi_hw_init()
386 reg_val |= SPI_CMD_TXMSBF; in mtk_spi_hw_init()
387 reg_val |= SPI_CMD_RXMSBF; in mtk_spi_hw_init()
392 reg_val &= ~SPI_CMD_TX_ENDIAN; in mtk_spi_hw_init()
393 reg_val &= ~SPI_CMD_RX_ENDIAN; in mtk_spi_hw_init()
395 reg_val |= SPI_CMD_TX_ENDIAN; in mtk_spi_hw_init()
396 reg_val |= SPI_CMD_RX_ENDIAN; in mtk_spi_hw_init()
402 reg_val |= SPI_CMD_CS_POL; in mtk_spi_hw_init()
404 reg_val &= ~SPI_CMD_CS_POL; in mtk_spi_hw_init()
407 reg_val |= SPI_CMD_SAMPLE_SEL; in mtk_spi_hw_init()
409 reg_val &= ~SPI_CMD_SAMPLE_SEL; in mtk_spi_hw_init()
413 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE; in mtk_spi_hw_init()
416 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA); in mtk_spi_hw_init()
419 reg_val &= ~SPI_CMD_DEASSERT; in mtk_spi_hw_init()
421 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_hw_init()
431 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_hw_init()
432 reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; in mtk_spi_hw_init()
433 reg_val |= ((chip_config->tick_delay & 0x7) in mtk_spi_hw_init()
435 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_hw_init()
437 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_hw_init()
438 reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; in mtk_spi_hw_init()
439 reg_val |= ((chip_config->tick_delay & 0x7) in mtk_spi_hw_init()
441 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_hw_init()
444 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_hw_init()
445 reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1; in mtk_spi_hw_init()
446 reg_val |= ((chip_config->tick_delay & 0x3) in mtk_spi_hw_init()
448 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_hw_init()
464 u32 reg_val; in mtk_spi_set_cs() local
470 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_set_cs()
472 reg_val |= SPI_CMD_PAUSE_EN; in mtk_spi_set_cs()
473 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_set_cs()
475 reg_val &= ~SPI_CMD_PAUSE_EN; in mtk_spi_set_cs()
476 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_set_cs()
485 u32 div, sck_time, reg_val; in mtk_spi_prepare_transfer() local
496 reg_val = readl(mdata->base + SPI_CFG2_REG); in mtk_spi_prepare_transfer()
497 reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET); in mtk_spi_prepare_transfer()
498 reg_val |= (((sck_time - 1) & 0xffff) in mtk_spi_prepare_transfer()
500 reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET); in mtk_spi_prepare_transfer()
501 reg_val |= (((sck_time - 1) & 0xffff) in mtk_spi_prepare_transfer()
503 writel(reg_val, mdata->base + SPI_CFG2_REG); in mtk_spi_prepare_transfer()
505 reg_val = readl(mdata->base + SPI_CFG0_REG); in mtk_spi_prepare_transfer()
506 reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET); in mtk_spi_prepare_transfer()
507 reg_val |= (((sck_time - 1) & 0xff) in mtk_spi_prepare_transfer()
509 reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET); in mtk_spi_prepare_transfer()
510 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); in mtk_spi_prepare_transfer()
511 writel(reg_val, mdata->base + SPI_CFG0_REG); in mtk_spi_prepare_transfer()
517 u32 packet_size, packet_loop, reg_val; in mtk_spi_setup_packet() local
531 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_setup_packet()
533 reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK; in mtk_spi_setup_packet()
535 reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK; in mtk_spi_setup_packet()
536 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; in mtk_spi_setup_packet()
537 reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK; in mtk_spi_setup_packet()
538 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; in mtk_spi_setup_packet()
539 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_setup_packet()
629 u32 reg_val; in mtk_spi_fifo_transfer() local
643 reg_val = 0; in mtk_spi_fifo_transfer()
644 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder); in mtk_spi_fifo_transfer()
645 writel(reg_val, mdata->base + SPI_TX_DATA_REG); in mtk_spi_fifo_transfer()
704 u32 reg_val = 0; in mtk_spi_transfer_one() local
709 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; in mtk_spi_transfer_one()
711 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; in mtk_spi_transfer_one()
713 writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); in mtk_spi_transfer_one()
748 u32 cmd, reg_val, cnt, remainder, len; in mtk_spi_interrupt_thread() local
760 reg_val = readl(mdata->base + SPI_RX_DATA_REG); in mtk_spi_interrupt_thread()
762 ®_val, in mtk_spi_interrupt_thread()
784 reg_val = 0; in mtk_spi_interrupt_thread()
785 memcpy(®_val, in mtk_spi_interrupt_thread()
788 writel(reg_val, mdata->base + SPI_TX_DATA_REG); in mtk_spi_interrupt_thread()
840 u32 reg_val; in mtk_spi_interrupt() local
842 reg_val = readl(mdata->base + SPI_STATUS0_REG); in mtk_spi_interrupt()
843 if (reg_val & MTK_SPI_PAUSE_INT_STATUS) in mtk_spi_interrupt()
955 u32 reg_val, nio, tx_size; in mtk_spi_mem_exec_op() local
966 reg_val = readl(mdata->base + SPI_CFG3_IPM_REG); in mtk_spi_mem_exec_op()
968 reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK; in mtk_spi_mem_exec_op()
969 reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET; in mtk_spi_mem_exec_op()
972 reg_val &= ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK; in mtk_spi_mem_exec_op()
974 reg_val |= (op->addr.nbytes + op->dummy.nbytes) << in mtk_spi_mem_exec_op()
979 reg_val |= SPI_CFG3_IPM_NODATA_FLAG; in mtk_spi_mem_exec_op()
982 reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG; in mtk_spi_mem_exec_op()
989 reg_val |= SPI_CFG3_IPM_XMODE_EN; in mtk_spi_mem_exec_op()
991 reg_val &= ~SPI_CFG3_IPM_XMODE_EN; in mtk_spi_mem_exec_op()
1005 reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK; in mtk_spi_mem_exec_op()
1006 reg_val |= PIN_MODE_CFG(nio); in mtk_spi_mem_exec_op()
1008 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; in mtk_spi_mem_exec_op()
1010 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; in mtk_spi_mem_exec_op()
1012 reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR; in mtk_spi_mem_exec_op()
1013 writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); in mtk_spi_mem_exec_op()
1076 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_mem_exec_op()
1077 reg_val |= SPI_CMD_TX_DMA; in mtk_spi_mem_exec_op()
1079 reg_val |= SPI_CMD_RX_DMA; in mtk_spi_mem_exec_op()
1080 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_mem_exec_op()
1092 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_mem_exec_op()
1093 reg_val &= ~SPI_CMD_TX_DMA; in mtk_spi_mem_exec_op()
1095 reg_val &= ~SPI_CMD_RX_DMA; in mtk_spi_mem_exec_op()
1096 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_mem_exec_op()