| /linux-6.12.1/drivers/gpu/drm/panel/ |
| D | panel-jadard-jd9365da-h3.c | 51 #define jd9365da_switch_page(dsi_ctx, page) \ argument
52 mipi_dsi_dcs_write_seq_multi(dsi_ctx, JD9365DA_DCS_SWITCH_PAGE, (page))
54 static void jadard_enable_standard_cmds(struct mipi_dsi_multi_context *dsi_ctx) in jadard_enable_standard_cmds() argument
56 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe1, 0x93); in jadard_enable_standard_cmds()
57 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe2, 0x65); in jadard_enable_standard_cmds()
58 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe3, 0xf8); in jadard_enable_standard_cmds()
59 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x80, 0x03); in jadard_enable_standard_cmds()
70 struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; in jadard_disable() local
73 mipi_dsi_msleep(&dsi_ctx, jadard->desc->backlight_off_to_display_off_delay_ms); in jadard_disable()
75 mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); in jadard_disable()
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| D | panel-sony-tulip-truly-nt35521.c | 30 #define nt35521_switch_page(dsi_ctx, page) \ argument
31 mipi_dsi_dcs_write_seq_multi(dsi_ctx, NT35521_DCS_SWITCH_PAGE, \
53 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in truly_nt35521_on() local
57 nt35521_switch_page(&dsi_ctx, 0x00); in truly_nt35521_on()
58 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x80); in truly_nt35521_on()
59 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6f, 0x11, 0x00); in truly_nt35521_on()
60 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf7, 0x20, 0x00); in truly_nt35521_on()
61 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6f, 0x01); in truly_nt35521_on()
62 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x21); in truly_nt35521_on()
63 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbd, 0x01, 0xa0, 0x10, 0x08, 0x01); in truly_nt35521_on()
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| D | panel-newvision-nv3051d.c | 50 struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; in panel_nv3051d_init_sequence() local
57 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x30); in panel_nv3051d_init_sequence()
58 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x52); in panel_nv3051d_init_sequence()
59 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x01); in panel_nv3051d_init_sequence()
60 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0x00); in panel_nv3051d_init_sequence()
61 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x40); in panel_nv3051d_init_sequence()
62 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x00); in panel_nv3051d_init_sequence()
63 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x03); in panel_nv3051d_init_sequence()
64 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x12); in panel_nv3051d_init_sequence()
65 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x1E); in panel_nv3051d_init_sequence()
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| D | panel-himax-hx83102.c | 84 static void hx83102_enable_extended_cmds(struct mipi_dsi_multi_context *dsi_ctx, bool enable) in hx83102_enable_extended_cmds() argument
87 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX83102_SETEXTC, 0x83, 0x10, 0x21, 0x55, 0x00); in hx83102_enable_extended_cmds()
89 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX83102_SETEXTC, 0x00, 0x00, 0x00); in hx83102_enable_extended_cmds()
94 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; in starry_himax83102_j02_init() local
96 hx83102_enable_extended_cmds(&dsi_ctx, true); in starry_himax83102_j02_init()
97 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2c, 0xb5, 0xb5, 0x31, 0xf1, in starry_himax83102_j02_init()
101 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x47, 0xb0, 0x80, 0x00, in starry_himax83102_j02_init()
103 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x76, 0x76, 0x76, 0x76, 0x76, in starry_himax83102_j02_init()
105 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd); in starry_himax83102_j02_init()
106 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x84); in starry_himax83102_j02_init()
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| D | panel-raydium-rm692e5.c | 43 static void rm692e5_on(struct mipi_dsi_multi_context *dsi_ctx) in rm692e5_on() argument
45 dsi_ctx->dsi->mode_flags |= MIPI_DSI_MODE_LPM; in rm692e5_on()
47 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfe, 0x41); in rm692e5_on()
48 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xd6, 0x00); in rm692e5_on()
49 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfe, 0x16); in rm692e5_on()
50 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x8a, 0x87); in rm692e5_on()
51 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfe, 0x71); in rm692e5_on()
52 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x82, 0x01); in rm692e5_on()
53 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xc6, 0x00); in rm692e5_on()
54 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xc7, 0x2c); in rm692e5_on()
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| D | panel-sitronix-st7703.c | 72 void (*init_sequence)(struct mipi_dsi_multi_context *dsi_ctx);
80 static void jh057n_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) in jh057n_init_sequence() argument
87 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, in jh057n_init_sequence()
89 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, in jh057n_init_sequence()
92 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, in jh057n_init_sequence()
95 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x4E); in jh057n_init_sequence()
96 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0B); in jh057n_init_sequence()
97 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80); in jh057n_init_sequence()
98 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 0xF0, 0x12, 0x30); in jh057n_init_sequence()
99 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, in jh057n_init_sequence()
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| D | panel-boe-th101mb31ig002-28a.c | 63 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; in boe_th101mb31ig002_enable() local
65 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0xab, 0xba); in boe_th101mb31ig002_enable()
66 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0xba, 0xab); in boe_th101mb31ig002_enable()
67 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb1, 0x10, 0x01, 0x47, 0xff); in boe_th101mb31ig002_enable()
68 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb2, 0x0c, 0x14, 0x04, 0x50, 0x50, 0x14); in boe_th101mb31ig002_enable()
69 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb3, 0x56, 0x53, 0x00); in boe_th101mb31ig002_enable()
70 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb4, 0x33, 0x30, 0x04); in boe_th101mb31ig002_enable()
71 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb6, 0xb0, 0x00, 0x00, 0x10, 0x00, 0x10, in boe_th101mb31ig002_enable()
73 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb8, 0x05, 0x12, 0x29, 0x49, 0x48, 0x00, in boe_th101mb31ig002_enable()
75 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb9, 0x7c, 0x65, 0x55, 0x49, 0x46, 0x36, in boe_th101mb31ig002_enable()
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| D | panel-asus-z00t-tm5p5-n35596.c | 36 static void tm5p5_nt35596_on(struct mipi_dsi_multi_context *dsi_ctx) in tm5p5_nt35596_on() argument
38 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xff, 0x05); in tm5p5_nt35596_on()
39 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfb, 0x01); in tm5p5_nt35596_on()
40 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xc5, 0x31); in tm5p5_nt35596_on()
41 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xff, 0x04); in tm5p5_nt35596_on()
42 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x01, 0x84); in tm5p5_nt35596_on()
43 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x05, 0x25); in tm5p5_nt35596_on()
44 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x06, 0x01); in tm5p5_nt35596_on()
45 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x07, 0x20); in tm5p5_nt35596_on()
46 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x08, 0x06); in tm5p5_nt35596_on()
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| D | panel-visionox-vtdr6130.c | 49 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in visionox_vtdr6130_on() local
53 mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK); in visionox_vtdr6130_on()
55 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, in visionox_vtdr6130_on()
57 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, in visionox_vtdr6130_on()
60 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x09); in visionox_vtdr6130_on()
61 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x01); in visionox_vtdr6130_on()
62 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00); in visionox_vtdr6130_on()
63 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x01); in visionox_vtdr6130_on()
64 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x12, 0x00, 0x00, 0xab, in visionox_vtdr6130_on()
78 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xaa, 0x10); in visionox_vtdr6130_on()
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| D | panel-jdi-fhd-r63452.c | 44 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in jdi_fhd_r63452_on() local
48 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x00); in jdi_fhd_r63452_on()
49 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0x01); in jdi_fhd_r63452_on()
50 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xec, in jdi_fhd_r63452_on()
53 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x03); in jdi_fhd_r63452_on()
55 mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK); in jdi_fhd_r63452_on()
57 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00); in jdi_fhd_r63452_on()
59 mipi_dsi_dcs_set_pixel_format_multi(&dsi_ctx, 0x77); in jdi_fhd_r63452_on()
60 mipi_dsi_dcs_set_column_address_multi(&dsi_ctx, 0x0000, 0x0437); in jdi_fhd_r63452_on()
61 mipi_dsi_dcs_set_page_address_multi(&dsi_ctx, 0x0000, 0x077f); in jdi_fhd_r63452_on()
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| D | panel-boe-tv101wum-ll2.c | 48 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in boe_tv101wum_ll2_on() local
52 mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); in boe_tv101wum_ll2_on()
54 mipi_dsi_msleep(&dsi_ctx, 120); in boe_tv101wum_ll2_on()
56 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x0e); in boe_tv101wum_ll2_on()
57 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0xff, 0x81, 0x68, 0x6c, 0x22, in boe_tv101wum_ll2_on()
59 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x23); in boe_tv101wum_ll2_on()
60 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x90, 0x00, 0x00); in boe_tv101wum_ll2_on()
61 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x94, 0x2c, 0x00); in boe_tv101wum_ll2_on()
62 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x19); in boe_tv101wum_ll2_on()
63 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa2, 0x38); in boe_tv101wum_ll2_on()
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| D | panel-novatek-nt35950.c | 107 static void nt35950_set_cmd2_page(struct mipi_dsi_multi_context *dsi_ctx, in nt35950_set_cmd2_page() argument
113 mipi_dsi_dcs_write_buffer_multi(dsi_ctx, mauc_cmd2_page, in nt35950_set_cmd2_page()
115 if (!dsi_ctx->accum_err) in nt35950_set_cmd2_page()
125 static void nt35950_set_data_compression(struct mipi_dsi_multi_context *dsi_ctx, in nt35950_set_data_compression() argument
135 nt35950_set_cmd2_page(dsi_ctx, nt, 0); in nt35950_set_data_compression()
137 mipi_dsi_dcs_write_buffer_multi(dsi_ctx, cmd_data_compression, in nt35950_set_data_compression()
139 mipi_dsi_dcs_write_buffer_multi(dsi_ctx, cmd_vesa_dsc_on, in nt35950_set_data_compression()
143 nt35950_set_cmd2_page(dsi_ctx, nt, 4); in nt35950_set_data_compression()
146 mipi_dsi_dcs_write_buffer_multi(dsi_ctx, cmd_vesa_dsc_setting, in nt35950_set_data_compression()
150 nt35950_set_cmd2_page(dsi_ctx, nt, last_page); in nt35950_set_data_compression()
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| D | panel-startek-kd070fhfid015.c | 55 struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; in stk_panel_init() local
57 mipi_dsi_dcs_soft_reset_multi(&dsi_ctx); in stk_panel_init()
58 mipi_dsi_msleep(&dsi_ctx, 5); in stk_panel_init()
59 mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); in stk_panel_init()
60 mipi_dsi_msleep(&dsi_ctx, 120); in stk_panel_init()
62 mipi_dsi_generic_write_seq_multi(&dsi_ctx, DSI_REG_MCAP, 0x04); in stk_panel_init()
65 mipi_dsi_generic_write_seq_multi(&dsi_ctx, DSI_REG_IS, 0x14, 0x08, 0x00, 0x22, 0x00); in stk_panel_init()
66 mipi_dsi_generic_write_seq_multi(&dsi_ctx, DSI_REG_IIS, 0x0c, 0x00); in stk_panel_init()
67 mipi_dsi_generic_write_seq_multi(&dsi_ctx, DSI_REG_CTRL, 0x3a, 0xd3); in stk_panel_init()
69 mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x77); in stk_panel_init()
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| D | panel-mantix-mlaf057we51.c | 48 static void mantix_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) in mantix_init_sequence() argument
53 mipi_dsi_generic_write_seq_multi(dsi_ctx, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x5a); in mantix_init_sequence()
55 mipi_dsi_generic_write_seq_multi(dsi_ctx, MANTIX_CMD_INT_CANCEL, 0x03); in mantix_init_sequence()
56 mipi_dsi_generic_write_seq_multi(dsi_ctx, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x5a, 0x03); in mantix_init_sequence()
57 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x80, 0xa9, 0x00); in mantix_init_sequence()
59 mipi_dsi_generic_write_seq_multi(dsi_ctx, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x5a, 0x09); in mantix_init_sequence()
60 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x80, 0x64, 0x00, 0x64, 0x00, 0x00); in mantix_init_sequence()
61 mipi_dsi_msleep(dsi_ctx, 20); in mantix_init_sequence()
63 mipi_dsi_generic_write_seq_multi(dsi_ctx, MANTIX_CMD_SPI_FINISH, 0xa5); in mantix_init_sequence()
64 mipi_dsi_generic_write_seq_multi(dsi_ctx, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x00, 0x2f); in mantix_init_sequence()
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