48 	struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };  in boe_tv101wum_ll2_on()  local
52 	mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);  in boe_tv101wum_ll2_on()
54 	mipi_dsi_msleep(&dsi_ctx, 120);  in boe_tv101wum_ll2_on()
56 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x0e);  in boe_tv101wum_ll2_on()
57 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0xff, 0x81, 0x68, 0x6c, 0x22,  in boe_tv101wum_ll2_on()
59 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x23);  in boe_tv101wum_ll2_on()
60 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x90, 0x00, 0x00);  in boe_tv101wum_ll2_on()
61 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x94, 0x2c, 0x00);  in boe_tv101wum_ll2_on()
62 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x19);  in boe_tv101wum_ll2_on()
63 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa2, 0x38);  in boe_tv101wum_ll2_on()
65 	mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x0c);  in boe_tv101wum_ll2_on()
66 	mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x80, 0xfd);  in boe_tv101wum_ll2_on()
67 	mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x50, 0x00);  in boe_tv101wum_ll2_on()
69 	mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);  in boe_tv101wum_ll2_on()
71 	mipi_dsi_msleep(&dsi_ctx, 20);  in boe_tv101wum_ll2_on()
73 	return dsi_ctx.accum_err;  in boe_tv101wum_ll2_on()
79 	struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };  in boe_tv101wum_ll2_off()  local
83 	mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);  in boe_tv101wum_ll2_off()
85 	mipi_dsi_msleep(&dsi_ctx, 70);  in boe_tv101wum_ll2_off()
87 	mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);  in boe_tv101wum_ll2_off()
89 	mipi_dsi_msleep(&dsi_ctx, 20);  in boe_tv101wum_ll2_off()
91 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x5a);  in boe_tv101wum_ll2_off()
92 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x5a);  in boe_tv101wum_ll2_off()
94 	mipi_dsi_msleep(&dsi_ctx, 150);  in boe_tv101wum_ll2_off()