Home
last modified time | relevance | path

Searched refs:dpll (Results 1 – 25 of 85) sorted by relevance

1234

/linux-6.12.1/drivers/dpll/
Ddpll_netlink.c34 dpll_msg_add_dev_handle(struct sk_buff *msg, struct dpll_device *dpll) in dpll_msg_add_dev_handle() argument
36 if (nla_put_u32(msg, DPLL_A_ID, dpll->id)) in dpll_msg_add_dev_handle()
92 dpll_msg_add_mode(struct sk_buff *msg, struct dpll_device *dpll, in dpll_msg_add_mode() argument
95 const struct dpll_device_ops *ops = dpll_device_ops(dpll); in dpll_msg_add_mode()
99 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); in dpll_msg_add_mode()
109 dpll_msg_add_mode_supported(struct sk_buff *msg, struct dpll_device *dpll, in dpll_msg_add_mode_supported() argument
112 const struct dpll_device_ops *ops = dpll_device_ops(dpll); in dpll_msg_add_mode_supported()
120 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); in dpll_msg_add_mode_supported()
130 dpll_msg_add_lock_status(struct sk_buff *msg, struct dpll_device *dpll, in dpll_msg_add_lock_status() argument
133 const struct dpll_device_ops *ops = dpll_device_ops(dpll); in dpll_msg_add_lock_status()
[all …]
Ddpll_core.c154 dpll_xa_ref_dpll_add(struct xarray *xa_dplls, struct dpll_device *dpll, in dpll_xa_ref_dpll_add() argument
164 if (ref->dpll != dpll) in dpll_xa_ref_dpll_add()
179 ref->dpll = dpll; in dpll_xa_ref_dpll_add()
181 ret = xa_insert(xa_dplls, dpll->id, ref, GFP_KERNEL); in dpll_xa_ref_dpll_add()
192 xa_erase(xa_dplls, dpll->id); in dpll_xa_ref_dpll_add()
208 dpll_xa_ref_dpll_del(struct xarray *xa_dplls, struct dpll_device *dpll, in dpll_xa_ref_dpll_del() argument
216 if (ref->dpll != dpll) in dpll_xa_ref_dpll_del()
245 struct dpll_device *dpll; in dpll_device_alloc() local
248 dpll = kzalloc(sizeof(*dpll), GFP_KERNEL); in dpll_device_alloc()
249 if (!dpll) in dpll_device_alloc()
[all …]
DMakefile6 obj-$(CONFIG_DPLL) += dpll.o
7 dpll-y += dpll_core.o
8 dpll-y += dpll_netlink.o
9 dpll-y += dpll_nl.o
Ddpll_core.h73 struct dpll_device *dpll; member
80 void *dpll_priv(struct dpll_device *dpll);
81 void *dpll_pin_on_dpll_priv(struct dpll_device *dpll, struct dpll_pin *pin);
84 const struct dpll_device_ops *dpll_device_ops(struct dpll_device *dpll);
Ddpll_netlink.h7 int dpll_device_create_ntf(struct dpll_device *dpll);
9 int dpll_device_delete_ntf(struct dpll_device *dpll);
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_dpll.c316 static int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
329 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) in i9xx_dpll_compute_m() argument
331 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
334 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
347 static int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
360 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
378 if ((hw_state->dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) in i9xx_pll_refclk()
407 hw_state->dpll = intel_de_read(dev_priv, DPLL(dev_priv, crtc->pipe)); in i9xx_dpll_get_hw_state()
414 hw_state->dpll &= ~(DPLL_LOCK_VLV | in i9xx_dpll_get_hw_state()
426 u32 dpll = hw_state->dpll; in i9xx_crtc_clock_get() local
[all …]
Dintel_dpll.h11 struct dpll;
24 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
25 u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
32 const struct dpll *dpll);
42 struct dpll *best_clock);
43 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
Dintel_dpll_mgr.c263 mutex_lock(&i915->display.dpll.lock); in intel_enable_shared_dpll()
289 mutex_unlock(&i915->display.dpll.lock); in intel_enable_shared_dpll()
312 mutex_lock(&i915->display.dpll.lock); in intel_disable_shared_dpll()
335 mutex_unlock(&i915->display.dpll.lock); in intel_disable_shared_dpll()
537 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state()
571 intel_de_write(i915, PCH_DPLL(id), hw_state->dpll); in ibx_pch_dpll_enable()
582 intel_de_write(i915, PCH_DPLL(id), hw_state->dpll); in ibx_pch_dpll_enable()
649 hw_state->dpll, in ibx_dump_hw_state()
661 return a->dpll == b->dpll && in ibx_compare_hw_state()
723 if (i915->display.dpll.pch_ssc_use & BIT(id)) in hsw_ddi_wrpll_disable()
[all …]
Dg4x_dp.h21 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915);
31 static inline const struct dpll *vlv_get_dpll(struct drm_i915_private *i915) in vlv_get_dpll()
Dintel_dpll_mgr.h34 for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \
35 ((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++)
185 u32 dpll; member
/linux-6.12.1/include/linux/
Ddpll.h21 int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv,
23 int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv,
27 int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv,
33 const struct dpll_device *dpll, void *dpll_priv,
37 const struct dpll_device *dpll, void *dpll_priv,
40 const struct dpll_device *dpll, void *dpll_priv,
44 const struct dpll_device *dpll, void *dpll_priv,
53 const struct dpll_device *dpll,
62 const struct dpll_device *dpll,
67 const struct dpll_device *dpll, void *dpll_priv,
[all …]
/linux-6.12.1/drivers/gpu/drm/gma500/
Dpsb_intel_display.c107 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
158 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
160 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
161 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
163 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
167 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
168 dpll |= in psb_intel_crtc_mode_set()
173 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
176 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
179 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
[all …]
Doaktrail_crtc.c245 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
247 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
248 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
251 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
253 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
256 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
258 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
317 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
319 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
321 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
[all …]
Dcdv_intel_display.c584 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
665 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
676 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
722 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
723 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
758 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()
767 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set()
768 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
769 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
773 if (!(REG_READ(map->dpll) & DPLL_LOCK)) { in cdv_intel_crtc_mode_set()
[all …]
Dgma_display.c223 temp = REG_READ(map->dpll); in gma_crtc_dpms()
225 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
229 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
230 REG_READ(map->dpll); in gma_crtc_dpms()
233 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
234 REG_READ(map->dpll); in gma_crtc_dpms()
311 temp = REG_READ(map->dpll); in gma_crtc_dpms()
313 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in gma_crtc_dpms()
314 REG_READ(map->dpll); in gma_crtc_dpms()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/ti/
Ddpll.txt16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
20 "ti,omap4-dpll-clock",
21 "ti,omap4-dpll-x2-clock",
22 "ti,omap4-dpll-core-clock",
23 "ti,omap4-dpll-m4xen-clock",
24 "ti,omap4-dpll-j-type-clock",
25 "ti,omap5-mpu-dpll-clock",
[all …]
/linux-6.12.1/Documentation/driver-api/
Ddpll.rst4 The Linux kernel dpll subsystem
22 The main purpose of dpll subsystem is to provide general interface
32 Single dpll device object means single Digital PLL circuit and bunch of
38 Changing the configuration of dpll device is done with `do` request of
52 The number of pins per dpll vary, but usually multiple pins shall be
53 provided for a single dpll device.
68 In general, selected pin (the one which signal is driving the dpll
70 one pin shall be in ``DPLL_PIN_STATE_CONNECTED`` state for any dpll
74 on hardware capabilities and active dpll device work mode
77 for the states the user can request for a dpll device.
[all …]
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/
Ddpll.c11 struct dpll_device *dpll; member
144 mlx5_dpll_device_lock_status_get(const struct dpll_device *dpll, void *priv, in mlx5_dpll_device_lock_status_get() argument
161 static int mlx5_dpll_device_mode_get(const struct dpll_device *dpll, in mlx5_dpll_device_mode_get() argument
176 const struct dpll_device *dpll, in mlx5_dpll_pin_direction_get() argument
187 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_get() argument
205 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_set() argument
219 const struct dpll_device *dpll, void *dpll_priv, in mlx5_dpll_ffo_get() argument
271 dpll_device_change_ntf(mdpll->dpll); in mlx5_dpll_periodic_work()
360 mdpll->dpll = dpll_device_get(clock_id, 0, THIS_MODULE); in mlx5_dpll_probe()
361 if (IS_ERR(mdpll->dpll)) { in mlx5_dpll_probe()
[all …]
/linux-6.12.1/drivers/net/ethernet/intel/ice/
Dice_dpll.c128 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_frequency_set() argument
166 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_input_frequency_set() argument
169 return ice_dpll_frequency_set(pin, pin_priv, dpll, dpll_priv, frequency, in ice_dpll_input_frequency_set()
191 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_output_frequency_set() argument
194 return ice_dpll_frequency_set(pin, pin_priv, dpll, dpll_priv, frequency, in ice_dpll_output_frequency_set()
217 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_frequency_get() argument
250 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_input_frequency_get() argument
253 return ice_dpll_frequency_get(pin, pin_priv, dpll, dpll_priv, frequency, in ice_dpll_input_frequency_get()
275 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_output_frequency_get() argument
278 return ice_dpll_frequency_get(pin, pin_priv, dpll, dpll_priv, frequency, in ice_dpll_output_frequency_get()
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Ddra7xx-clocks.dtsi229 compatible = "ti,omap4-dpll-m4xen-clock";
235 dpll_abe_x2_ck: clock-dpll-abe-x2 {
237 compatible = "ti,omap4-dpll-x2-clock";
242 dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 {
264 dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 {
276 dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 {
307 compatible = "ti,omap4-dpll-core-clock";
313 dpll_core_x2_ck: clock-dpll-core-x2 {
315 compatible = "ti,omap4-dpll-x2-clock";
320 dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c {
[all …]
Dam43xx-clocks.dtsi231 compatible = "ti,am3-dpll-core-clock";
237 dpll_core_x2_ck: clock-dpll-core-x2 {
239 compatible = "ti,am3-dpll-x2-clock";
244 dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 {
256 dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c {
268 dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 {
282 compatible = "ti,am3-dpll-clock";
288 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 {
311 compatible = "ti,am3-dpll-clock";
317 dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 {
[all …]
Dam33xx-clocks.dtsi191 compatible = "ti,am3-dpll-core-clock";
197 dpll_core_x2_ck: clock-dpll-core-x2 {
199 compatible = "ti,am3-dpll-x2-clock";
204 dpll_core_m4_ck: clock-dpll-core-m4@480 {
214 dpll_core_m5_ck: clock-dpll-core-m5@484 {
224 dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
236 compatible = "ti,am3-dpll-clock";
242 dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
254 compatible = "ti,am3-dpll-no-gate-clock";
260 dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
[all …]
/linux-6.12.1/arch/arm/mach-omap1/
Dsram.S36 strh r0, [r2] @ set dpll into bypass mode
41 strh r0, [r2] @ write new dpll value
49 lock: ldrh r4, [r2], #0 @ read back dpll value
52 tst r4, #1 << 0 @ dpll rate locked?
/linux-6.12.1/drivers/ata/
Dpata_hpt3x2n.c312 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
319 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
328 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
330 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
332 flags |= dpll; in hpt3x2n_qc_issue()
335 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
/linux-6.12.1/drivers/gpu/drm/renesas/rcar-du/
Drcar_du_crtc.c83 struct dpll_info *dpll, in rcar_du_dpll_divider() argument
147 dpll->n = n; in rcar_du_dpll_divider()
148 dpll->m = m; in rcar_du_dpll_divider()
149 dpll->fdpll = fdpll; in rcar_du_dpll_divider()
150 dpll->output = output; in rcar_du_dpll_divider()
162 dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff); in rcar_du_dpll_divider()
217 struct dpll_info dpll = { 0 }; in rcar_du_crtc_set_display_timing() local
227 rcar_du_dpll_divider(rcrtc, &dpll, extclk, target); in rcar_du_crtc_set_display_timing()
230 | DPLLCR_FDPLL(dpll.fdpll) in rcar_du_crtc_set_display_timing()
231 | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m) in rcar_du_crtc_set_display_timing()

1234