Lines Matching refs:dpll
316 static int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
329 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) in i9xx_dpll_compute_m() argument
331 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
334 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
347 static int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
360 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
378 if ((hw_state->dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) in i9xx_pll_refclk()
407 hw_state->dpll = intel_de_read(dev_priv, DPLL(dev_priv, crtc->pipe)); in i9xx_dpll_get_hw_state()
414 hw_state->dpll &= ~(DPLL_LOCK_VLV | in i9xx_dpll_get_hw_state()
426 u32 dpll = hw_state->dpll; in i9xx_crtc_clock_get() local
428 struct dpll clock; in i9xx_crtc_clock_get()
432 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) in i9xx_crtc_clock_get()
448 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> in i9xx_crtc_clock_get()
451 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> in i9xx_crtc_clock_get()
454 switch (dpll & DPLL_MODE_MASK) { in i9xx_crtc_clock_get()
456 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? in i9xx_crtc_clock_get()
460 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? in i9xx_crtc_clock_get()
466 "mode\n", (int)(dpll & DPLL_MODE_MASK)); in i9xx_crtc_clock_get()
482 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in i9xx_crtc_clock_get()
490 if (dpll & PLL_P1_DIVIDE_BY_TWO) in i9xx_crtc_clock_get()
493 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> in i9xx_crtc_clock_get()
496 if (dpll & PLL_P2_DIVIDE_BY_4) in i9xx_crtc_clock_get()
521 struct dpll clock; in vlv_crtc_clock_get()
525 if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
548 struct dpll clock; in chv_crtc_clock_get()
553 if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
581 const struct dpll *clock) in intel_pll_is_valid()
652 const struct dpll *match_clock, in i9xx_find_best_dpll()
653 struct dpll *best_clock) in i9xx_find_best_dpll()
656 struct dpll clock; in i9xx_find_best_dpll()
710 const struct dpll *match_clock, in pnv_find_best_dpll()
711 struct dpll *best_clock) in pnv_find_best_dpll()
714 struct dpll clock; in pnv_find_best_dpll()
766 const struct dpll *match_clock, in g4x_find_best_dpll()
767 struct dpll *best_clock) in g4x_find_best_dpll()
770 struct dpll clock; in g4x_find_best_dpll()
817 const struct dpll *calculated_clock, in vlv_PLL_is_optimal()
818 const struct dpll *best_clock, in vlv_PLL_is_optimal()
860 const struct dpll *match_clock, in vlv_find_best_dpll()
861 struct dpll *best_clock) in vlv_find_best_dpll()
865 struct dpll clock; in vlv_find_best_dpll()
918 const struct dpll *match_clock, in chv_find_best_dpll()
919 struct dpll *best_clock) in chv_find_best_dpll()
924 struct dpll clock; in chv_find_best_dpll()
974 struct dpll *best_clock) in bxt_find_best_dpll()
984 u32 i9xx_dpll_compute_fp(const struct dpll *dpll) in i9xx_dpll_compute_fp() argument
986 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
989 static u32 pnv_dpll_compute_fp(const struct dpll *dpll) in pnv_dpll_compute_fp() argument
991 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
1000 const struct dpll *clock, in i9xx_dpll()
1001 const struct dpll *reduced_clock) in i9xx_dpll()
1005 u32 dpll; in i9xx_dpll() local
1007 dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS; in i9xx_dpll()
1010 dpll |= DPLLB_MODE_LVDS; in i9xx_dpll()
1012 dpll |= DPLLB_MODE_DAC_SERIAL; in i9xx_dpll()
1016 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_dpll()
1022 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_dpll()
1025 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_dpll()
1029 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_dpll()
1030 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_dpll()
1032 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_dpll()
1035 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_dpll()
1041 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in i9xx_dpll()
1044 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in i9xx_dpll()
1047 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in i9xx_dpll()
1050 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in i9xx_dpll()
1056 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); in i9xx_dpll()
1059 dpll |= PLL_REF_INPUT_TVCLKINBC; in i9xx_dpll()
1062 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i9xx_dpll()
1064 dpll |= PLL_REF_INPUT_DREFCLK; in i9xx_dpll()
1066 return dpll; in i9xx_dpll()
1070 const struct dpll *clock, in i9xx_compute_dpll()
1071 const struct dpll *reduced_clock) in i9xx_compute_dpll()
1085 hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock); in i9xx_compute_dpll()
1092 const struct dpll *clock, in i8xx_dpll()
1093 const struct dpll *reduced_clock) in i8xx_dpll()
1097 u32 dpll; in i8xx_dpll() local
1099 dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS; in i8xx_dpll()
1102 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_dpll()
1105 dpll |= PLL_P1_DIVIDE_BY_TWO; in i8xx_dpll()
1107 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_dpll()
1109 dpll |= PLL_P2_DIVIDE_BY_4; in i8xx_dpll()
1128 dpll |= DPLL_DVO_2X_MODE; in i8xx_dpll()
1132 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i8xx_dpll()
1134 dpll |= PLL_REF_INPUT_DREFCLK; in i8xx_dpll()
1136 return dpll; in i8xx_dpll()
1140 const struct dpll *clock, in i8xx_compute_dpll()
1141 const struct dpll *reduced_clock) in i8xx_compute_dpll()
1148 hw_state->dpll = i8xx_dpll(crtc_state, clock, reduced_clock); in i8xx_compute_dpll()
1251 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor) in ilk_needs_fb_cb_tune() argument
1253 return dpll->m < factor * dpll->n; in ilk_needs_fb_cb_tune()
1256 static u32 ilk_dpll_compute_fp(const struct dpll *clock, int factor) in ilk_dpll_compute_fp()
1268 const struct dpll *clock, in ilk_dpll()
1269 const struct dpll *reduced_clock) in ilk_dpll()
1273 u32 dpll; in ilk_dpll() local
1275 dpll = DPLL_VCO_ENABLE; in ilk_dpll()
1278 dpll |= DPLLB_MODE_LVDS; in ilk_dpll()
1280 dpll |= DPLLB_MODE_DAC_SERIAL; in ilk_dpll()
1282 dpll |= (crtc_state->pixel_multiplier - 1) in ilk_dpll()
1287 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_dpll()
1290 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_dpll()
1308 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_dpll()
1311 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_dpll()
1313 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ilk_dpll()
1317 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in ilk_dpll()
1320 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in ilk_dpll()
1323 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in ilk_dpll()
1326 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in ilk_dpll()
1333 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in ilk_dpll()
1335 dpll |= PLL_REF_INPUT_DREFCLK; in ilk_dpll()
1337 return dpll; in ilk_dpll()
1341 const struct dpll *clock, in ilk_compute_dpll()
1342 const struct dpll *reduced_clock) in ilk_compute_dpll()
1350 hw_state->dpll = ilk_dpll(crtc_state, clock, reduced_clock); in ilk_compute_dpll()
1392 refclk, NULL, &crtc_state->dpll)) in ilk_crtc_compute_clock()
1395 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in ilk_crtc_compute_clock()
1397 ilk_compute_dpll(crtc_state, &crtc_state->dpll, in ilk_crtc_compute_clock()
1398 &crtc_state->dpll); in ilk_crtc_compute_clock()
1404 crtc_state->port_clock = crtc_state->dpll.dot; in ilk_crtc_compute_clock()
1426 u32 dpll; in vlv_dpll() local
1428 dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_dpll()
1432 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_dpll()
1436 dpll |= DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV; in vlv_dpll()
1438 return dpll; in vlv_dpll()
1445 hw_state->dpll = vlv_dpll(crtc_state); in vlv_compute_dpll()
1452 u32 dpll; in chv_dpll() local
1454 dpll = DPLL_SSC_REF_CLK_CHV | in chv_dpll()
1458 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_dpll()
1462 dpll |= DPLL_VCO_ENABLE; in chv_dpll()
1464 return dpll; in chv_dpll()
1471 hw_state->dpll = chv_dpll(crtc_state); in chv_compute_dpll()
1485 refclk, NULL, &crtc_state->dpll)) in chv_crtc_compute_clock()
1488 chv_calc_dpll_params(refclk, &crtc_state->dpll); in chv_crtc_compute_clock()
1496 crtc_state->port_clock = crtc_state->dpll.dot; in chv_crtc_compute_clock()
1512 refclk, NULL, &crtc_state->dpll)) in vlv_crtc_compute_clock()
1515 vlv_calc_dpll_params(refclk, &crtc_state->dpll); in vlv_crtc_compute_clock()
1523 crtc_state->port_clock = crtc_state->dpll.dot; in vlv_crtc_compute_clock()
1562 refclk, NULL, &crtc_state->dpll)) in g4x_crtc_compute_clock()
1565 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in g4x_crtc_compute_clock()
1567 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in g4x_crtc_compute_clock()
1568 &crtc_state->dpll); in g4x_crtc_compute_clock()
1570 crtc_state->port_clock = crtc_state->dpll.dot; in g4x_crtc_compute_clock()
1602 refclk, NULL, &crtc_state->dpll)) in pnv_crtc_compute_clock()
1605 pnv_calc_dpll_params(refclk, &crtc_state->dpll); in pnv_crtc_compute_clock()
1607 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in pnv_crtc_compute_clock()
1608 &crtc_state->dpll); in pnv_crtc_compute_clock()
1610 crtc_state->port_clock = crtc_state->dpll.dot; in pnv_crtc_compute_clock()
1640 refclk, NULL, &crtc_state->dpll)) in i9xx_crtc_compute_clock()
1643 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in i9xx_crtc_compute_clock()
1645 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in i9xx_crtc_compute_clock()
1646 &crtc_state->dpll); in i9xx_crtc_compute_clock()
1648 crtc_state->port_clock = crtc_state->dpll.dot; in i9xx_crtc_compute_clock()
1682 refclk, NULL, &crtc_state->dpll)) in i8xx_crtc_compute_clock()
1685 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in i8xx_crtc_compute_clock()
1687 i8xx_compute_dpll(crtc_state, &crtc_state->dpll, in i8xx_crtc_compute_clock()
1688 &crtc_state->dpll); in i8xx_crtc_compute_clock()
1690 crtc_state->port_clock = crtc_state->dpll.dot; in i8xx_crtc_compute_clock()
1754 ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc); in intel_dpll_crtc_compute_clock()
1778 if (!i915->display.funcs.dpll->crtc_get_shared_dpll) in intel_dpll_crtc_get_shared_dpll()
1781 ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc); in intel_dpll_crtc_get_shared_dpll()
1795 dev_priv->display.funcs.dpll = &mtl_dpll_funcs; in intel_dpll_init_clock_hook()
1797 dev_priv->display.funcs.dpll = &dg2_dpll_funcs; in intel_dpll_init_clock_hook()
1799 dev_priv->display.funcs.dpll = &hsw_dpll_funcs; in intel_dpll_init_clock_hook()
1801 dev_priv->display.funcs.dpll = &ilk_dpll_funcs; in intel_dpll_init_clock_hook()
1803 dev_priv->display.funcs.dpll = &chv_dpll_funcs; in intel_dpll_init_clock_hook()
1805 dev_priv->display.funcs.dpll = &vlv_dpll_funcs; in intel_dpll_init_clock_hook()
1807 dev_priv->display.funcs.dpll = &g4x_dpll_funcs; in intel_dpll_init_clock_hook()
1809 dev_priv->display.funcs.dpll = &pnv_dpll_funcs; in intel_dpll_init_clock_hook()
1811 dev_priv->display.funcs.dpll = &i9xx_dpll_funcs; in intel_dpll_init_clock_hook()
1813 dev_priv->display.funcs.dpll = &i8xx_dpll_funcs; in intel_dpll_init_clock_hook()
1848 hw_state->dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
1849 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in i9xx_enable_pll()
1864 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in i9xx_enable_pll()
1869 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in i9xx_enable_pll()
1908 const struct dpll *clock = &crtc_state->dpll; in vlv_prepare_pll()
1998 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in _vlv_enable_pll()
2021 hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); in vlv_enable_pll()
2023 if (hw_state->dpll & DPLL_VCO_ENABLE) { in vlv_enable_pll()
2036 const struct dpll *clock = &crtc_state->dpll; in chv_prepare_pll()
2146 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in _chv_enable_pll()
2168 hw_state->dpll & ~DPLL_VCO_ENABLE); in chv_enable_pll()
2170 if (hw_state->dpll & DPLL_VCO_ENABLE) { in chv_enable_pll()
2213 const struct dpll *dpll) in vlv_force_pll_on() argument
2224 crtc_state->dpll = *dpll; in vlv_force_pll_on()