Lines Matching refs:dpll
584 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
665 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
676 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
722 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
723 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
758 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()
767 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set()
768 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
769 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
773 if (!(REG_READ(map->dpll) & DPLL_LOCK)) { in cdv_intel_crtc_mode_set()
842 u32 dpll; in cdv_intel_crtc_clock_get() local
849 dpll = REG_READ(map->dpll); in cdv_intel_crtc_clock_get()
850 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) in cdv_intel_crtc_clock_get()
857 dpll = p->dpll; in cdv_intel_crtc_clock_get()
858 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) in cdv_intel_crtc_clock_get()
873 ffs((dpll & in cdv_intel_crtc_clock_get()
878 dev_err(dev->dev, "PLL %d\n", dpll); in cdv_intel_crtc_clock_get()
882 if ((dpll & PLL_REF_INPUT_MASK) == in cdv_intel_crtc_clock_get()
889 if (dpll & PLL_P1_DIVIDE_BY_TWO) in cdv_intel_crtc_clock_get()
893 ((dpll & in cdv_intel_crtc_clock_get()
897 if (dpll & PLL_P2_DIVIDE_BY_4) in cdv_intel_crtc_clock_get()