| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn201/ |
| D | irq_service_dcn201.c | 152 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
168 IRQ_REG_ENTRY(HPD, reg_num,\
177 IRQ_REG_ENTRY(HPD, reg_num,\
185 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
193 IRQ_REG_ENTRY(OTG, reg_num,\
204 IRQ_REG_ENTRY(OTG, reg_num,\
211 IRQ_REG_ENTRY(OTG, reg_num,\
219 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn303/ |
| D | irq_service_dcn303.c | 138 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
153 IRQ_REG_ENTRY(HPD, reg_num,\
162 IRQ_REG_ENTRY(HPD, reg_num,\
170 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
181 IRQ_REG_ENTRY(OTG, reg_num,\
189 IRQ_REG_ENTRY(OTG, reg_num,\
197 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn20/ |
| D | irq_service_dcn20.c | 203 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
221 IRQ_REG_ENTRY(HPD, reg_num,\
230 IRQ_REG_ENTRY(HPD, reg_num,\
238 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
249 IRQ_REG_ENTRY(OTG, reg_num,\
257 IRQ_REG_ENTRY(OTG, reg_num,\
265 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn10/ |
| D | irq_service_dcn10.c | 200 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
216 IRQ_REG_ENTRY(HPD, reg_num,\
225 IRQ_REG_ENTRY(HPD, reg_num,\
233 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
244 IRQ_REG_ENTRY(OTG, reg_num,\
252 IRQ_REG_ENTRY(OTG, reg_num,\
260 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dce120/ |
| D | irq_service_dce120.c | 103 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
119 IRQ_REG_ENTRY(HPD, reg_num,\
128 IRQ_REG_ENTRY(HPD, reg_num,\
136 IRQ_REG_ENTRY(DCP, reg_num, \
145 IRQ_REG_ENTRY(CRTC, reg_num,\
153 IRQ_REG_ENTRY(CRTC, reg_num,\
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn32/ |
| D | irq_service_dcn32.c | 209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
239 IRQ_REG_ENTRY(HPD, reg_num,\
248 IRQ_REG_ENTRY(HPD, reg_num,\
256 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
267 IRQ_REG_ENTRY(OTG, reg_num,\
275 IRQ_REG_ENTRY(OTG, reg_num,\
283 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn315/ |
| D | irq_service_dcn315.c | 215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
245 IRQ_REG_ENTRY(HPD, reg_num,\
254 IRQ_REG_ENTRY(HPD, reg_num,\
262 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
273 IRQ_REG_ENTRY(OTG, reg_num,\
281 IRQ_REG_ENTRY(OTG, reg_num,\
289 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn302/ |
| D | irq_service_dcn302.c | 195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
229 IRQ_REG_ENTRY(HPD, reg_num,\
238 IRQ_REG_ENTRY(HPD, reg_num,\
246 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
257 IRQ_REG_ENTRY(OTG, reg_num,\
265 IRQ_REG_ENTRY(OTG, reg_num,\
273 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn401/ |
| D | irq_service_dcn401.c | 189 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
219 IRQ_REG_ENTRY(HPD, reg_num,\
228 IRQ_REG_ENTRY(HPD, reg_num,\
236 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
247 IRQ_REG_ENTRY(OTG, reg_num,\
255 IRQ_REG_ENTRY(OTG, reg_num,\
262 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn314/ |
| D | irq_service_dcn314.c | 210 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
240 IRQ_REG_ENTRY(HPD, reg_num,\
249 IRQ_REG_ENTRY(HPD, reg_num,\
257 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
268 IRQ_REG_ENTRY(OTG, reg_num,\
276 IRQ_REG_ENTRY(OTG, reg_num,\
284 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn30/ |
| D | irq_service_dcn30.c | 220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
250 IRQ_REG_ENTRY(HPD, reg_num,\
259 IRQ_REG_ENTRY(HPD, reg_num,\
267 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
278 IRQ_REG_ENTRY(OTG, reg_num,\
286 IRQ_REG_ENTRY(OTG, reg_num,\
301 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn31/ |
| D | irq_service_dcn31.c | 208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
238 IRQ_REG_ENTRY(HPD, reg_num,\
247 IRQ_REG_ENTRY(HPD, reg_num,\
255 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
266 IRQ_REG_ENTRY(OTG, reg_num,\
274 IRQ_REG_ENTRY(OTG, reg_num,\
282 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn21/ |
| D | irq_service_dcn21.c | 213 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ macro
243 IRQ_REG_ENTRY(HPD, reg_num,\
252 IRQ_REG_ENTRY(HPD, reg_num,\
260 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
271 IRQ_REG_ENTRY(OTG, reg_num,\
279 IRQ_REG_ENTRY(OTG, reg_num,\
287 IRQ_REG_ENTRY(OTG, reg_num,\
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn35/ |
| D | irq_service_dcn35.c | 207 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ macro
236 IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1, HPD, reg_num,\
243 IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1RX, HPD, reg_num,\
250 IRQ_REG_ENTRY(DC_IRQ_SOURCE_PFLIP1, HUBPREQ, reg_num,\
259 IRQ_REG_ENTRY(DC_IRQ_SOURCE_VUPDATE1, OTG, reg_num,\
265 IRQ_REG_ENTRY(DC_IRQ_SOURCE_VBLANK1, OTG, reg_num,\
271 IRQ_REG_ENTRY(DC_IRQ_SOURCE_DC1_VLINE0, OTG, reg_num,\
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn351/ |
| D | irq_service_dcn351.c | 186 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ macro
215 IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1, HPD, reg_num,\
222 IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1RX, HPD, reg_num,\
229 IRQ_REG_ENTRY(DC_IRQ_SOURCE_PFLIP1, HUBPREQ, reg_num,\
238 IRQ_REG_ENTRY(DC_IRQ_SOURCE_VUPDATE1, OTG, reg_num,\
244 IRQ_REG_ENTRY(DC_IRQ_SOURCE_VBLANK1, OTG, reg_num,\
250 IRQ_REG_ENTRY(DC_IRQ_SOURCE_DC1_VLINE0, OTG, reg_num,\
|