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/linux-6.12.1/arch/powerpc/lib/
Dxor_vmx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
44 #define XOR(V1, V2) \ macro
46 V1##_0 = vec_xor(V1##_0, V2##_0); \
47 V1##_1 = vec_xor(V1##_1, V2##_1); \
48 V1##_2 = vec_xor(V1##_2, V2##_2); \
49 V1##_3 = vec_xor(V1##_3, V2##_3); \
57 DEFINE(v2); in __xor_altivec_2()
62 LOAD(v2); in __xor_altivec_2()
63 XOR(v1, v2); in __xor_altivec_2()
67 v2 += 4; in __xor_altivec_2()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/dma/
Dmarvell,xor-v2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/marvell,xor-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell XOR v2 engines
10 - Andrew Lunn <andrew@lunn.ch>
15 - const: marvell,xor-v2
16 - items:
17 - enum:
18 - marvell,armada-7k-xor
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/linux-6.12.1/arch/arm64/boot/dts/marvell/
Darmada-ap810-ap0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
14 compatible = "marvell,armada-ap810";
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
28 ap810-ap0 {
29 #address-cells = <2>;
30 #size-cells = <2>;
[all …]
Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
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Darmada-cp11x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
42 cooling-maps { };
[all …]
/linux-6.12.1/arch/powerpc/crypto/
Dcrc32-vpmsum_core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 * 32 bits of 0s to the end - this matches what a CRC does. We just
28 #include <asm/ppc-opcode.h>
66 std r31,-8(r1)
67 std r30,-16(r1)
68 std r29,-24(r1)
69 std r28,-32(r1)
70 std r27,-40(r1)
71 std r26,-48(r1)
72 std r25,-56(r1)
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Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
19 # row1 = (row1 + row2), row4 = row1 xor row4, row4 rotate each word by 16
20 # row3 = (row3 + row4), row2 = row3 xor row2, row2 rotate each word by 12
21 # row1 = (row1 + row2), row4 = row1 xor row4, row4 rotate each word by 8
22 # row3 = (row3 + row4), row2 = row3 xor row2, row2 rotate each word by 7
38 # Column round (v0, v4, v8, v12, v1, v5, v9, v13, v2, v6, v10, v14, v3, v7, v11, v15)
39 # Diagnal round (v0, v5, v10, v15, v1, v6, v11, v12, v2, v7, v8, v13, v3, v4, v9, v14)
43 #include <asm/asm-offsets.h>
44 #include <asm/asm-compat.h>
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/linux-6.12.1/arch/arm64/crypto/
Daes-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aes-ce-ccm-core.S - AES-CCM transform for ARMv8 with Crypto Extensions
5 * Copyright (C) 2013 - 2017 Linaro Ltd.
15 .arch armv8-a+crypto
20 ld1 {v10.4s-v13.4s}, [\rk]
21 ld1 {v14.4s-v17.4s}, [\tmp], #64
22 ld1 {v18.4s-v21.4s}, [\tmp], #64
23 ld1 {v3.4s-v5.4s}, [\tmp]
65 ld1 {v2.16b}, [x1], #16 /* load next input block */
67 eor v2.16b, v2.16b, v5.16b /* final round enc+mac */
[all …]
Daes-modes.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm64/crypto/aes-modes.S - chaining mode wrappers for AES
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
8 /* included by aes-ce.S and aes-neon.S */
26 encrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
31 decrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
37 encrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
42 decrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
62 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
66 st1 {v0.16b-v3.16b}, [x0], #64
[all …]
Dcrct10dif-ce-core.S2 // Accelerated CRC-T10DIF using arm64 NEON and Crypto Extensions instructions
14 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
62 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
69 .arch armv8-a+crypto
277 CPU_LE( rev64 v2.16b, v2.16b )
285 CPU_LE( ext v2.16b, v2.16b, v2.16b, #8 )
292 // XOR the first 16 data *bits* with the initial CRC value.
305 // While >= 128 data bytes remain (not counting v0-v7), fold the 128
306 // bytes v0-v7 into them, storing the result back into v0-v7.
309 fold_32_bytes \p, v2, v3
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/linux-6.12.1/arch/s390/crypto/
Dcrc32le-vx.c1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Hardware-accelerated CRC-32 variants for Linux on z Systems
6 * computing of bitreflected CRC-32 checksums for IEEE 802.3 Ethernet
9 * This CRC-32 implementation algorithm is bitreflected and processes
10 * the least-significant bit first (Little-Endian).
18 #include "crc32-vx.h"
20 /* Vector register range containing CRC-32 constants */
29 * The CRC-32 constant block contains reduction constants to fold and
32 * For the CRC-32 variants, the constants are precomputed according to
36 * R2 = [(x4*128-32 mod P'(x) << 32)]' << 1
[all …]
Dcrc32be-vx.c1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Hardware-accelerated CRC-32 variants for Linux on z Systems
6 * computing of CRC-32 checksums.
8 * This CRC-32 implementation algorithm processes the most-significant
17 #include "crc32-vx.h"
19 /* Vector register range containing CRC-32 constants */
28 * The CRC-32 constant block contains reduction constants to fold and
31 * For the CRC-32 variants, the constants are precomputed according to
49 * can be multiplied by 1 to perform an XOR without the need for a separate
52 * CRC-32 (IEEE 802.3 Ethernet, ...) polynomials:
[all …]
/linux-6.12.1/arch/x86/crypto/
Daes-xts-avx-x86_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * AES-XTS for modern x86_64 CPUs
11 * This file implements AES-XTS for modern x86_64 CPUs. To handle the
16 * AES-NI + AVX
17 * - 128-bit vectors (1 AES block per vector)
18 * - VEX-coded instructions
19 * - xmm0-xmm15
20 * - This is for older CPUs that lack VAES but do have AVX.
23 * - 256-bit vectors (2 AES blocks per vector)
24 * - VEX-coded instructions
[all …]
Daes-gcm-avx10-x86_64.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // VAES and VPCLMULQDQ optimized AES-GCM for x86_64
9 //------------------------------------------------------------------------------
11 // This file is dual-licensed, meaning that you can use it under your choice of
17 // http://www.apache.org/licenses/LICENSE-2.0
49 //------------------------------------------------------------------------------
51 // This file implements AES-GCM (Galois/Counter Mode) for x86_64 CPUs that
54 // decryption update functions which are the most performance-critical, are
55 // provided in two variants generated from a macro: one using 256-bit vectors
56 // (suffix: vaes_avx10_256) and one using 512-bit vectors (vaes_avx10_512). The
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/linux-6.12.1/arch/arm64/lib/
Dxor-neon.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm64/lib/xor-neon.c
9 #include <linux/raid/xor.h>
11 #include <asm/neon-intrinsics.h>
19 register uint64x2_t v0, v1, v2, v3; in xor_arm64_neon_2() local
26 v2 = veorq_u64(vld1q_u64(dp1 + 4), vld1q_u64(dp2 + 4)); in xor_arm64_neon_2()
32 vst1q_u64(dp1 + 4, v2); in xor_arm64_neon_2()
37 } while (--lines > 0); in xor_arm64_neon_2()
48 register uint64x2_t v0, v1, v2, v3; in xor_arm64_neon_3() local
55 v2 = veorq_u64(vld1q_u64(dp1 + 4), vld1q_u64(dp2 + 4)); in xor_arm64_neon_3()
[all …]
/linux-6.12.1/kernel/
Dkcmp.c1 // SPDX-License-Identifier: GPL-2.0
23 * We don't expose the real in-memory order of objects for security reasons.
27 * The obfuscation is done in two steps. First we xor the kernel pointer with
29 * Secondly we multiply the xor production with a large odd random number to
45 * 0 - equal, i.e. v1 = v2
46 * 1 - less than, i.e. v1 < v2
47 * 2 - greater than, i.e. v1 > v2
48 * 3 - not equal but ordering unavailable (reserved for future)
50 static int kcmp_ptr(void *v1, void *v2, enum kcmp_type type) in kcmp_ptr() argument
55 t2 = kptr_obfuscate((long)v2, type); in kcmp_ptr()
[all …]
/linux-6.12.1/arch/loongarch/lib/
Dxor_template.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Template for XOR operations, instantiated in xor_simd.c.
9 * - LINE_WIDTH
10 * - XOR_FUNC_NAME(nr)
11 * - LD_INOUT_LINE(buf)
12 * - LD_AND_XOR_LINE(buf)
13 * - ST_LINE(buf)
18 const unsigned long * __restrict v2)
25 LD_AND_XOR_LINE(v2)
27 : : [v1] "r"(v1), [v2] "r"(v2) : "memory"
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/linux-6.12.1/arch/riscv/crypto/
Dsm4-riscv64-zvksed-zvkb.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
40 // The generated code of this file depends on the following RISC-V extensions:
41 // - RV64I
42 // - RISC-V Vector ('V') with VLEN >= 128
43 // - RISC-V Vector SM4 Block Cipher extension ('Zvksed')
44 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
60 // XOR the user key with the family key.
62 vle32.v v2, (t0)
63 vxor.vv v1, v1, v2
[all …]
/linux-6.12.1/lib/
Datomic64_test.c1 // SPDX-License-Identifier: GPL-2.0-or-later
101 i, (i) - one, (i) - one); \
115 TEST(, add, +=, -one); in test_atomic()
116 TEST(, sub, -=, onestwos); in test_atomic()
117 TEST(, sub, -=, -one); in test_atomic()
120 TEST(, xor, ^=, v1); in test_atomic()
124 RETURN_FAMILY_TEST(, add_return, +=, -one); in test_atomic()
125 RETURN_FAMILY_TEST(, sub_return, -=, onestwos); in test_atomic()
126 RETURN_FAMILY_TEST(, sub_return, -=, -one); in test_atomic()
129 FETCH_FAMILY_TEST(, fetch_add, +=, -one); in test_atomic()
[all …]
Dcrc32.c3 * cleaned up code to current version of sparse and added the slicing-by-8
4 * algorithm to the closely similar existing slicing-by-4 algorithm.
9 * subsequently included in the kernel, thus was re-licensed under the
10 * GNU GPL v2.
16 * Some xor at the end with ~0. The generic crc32() function takes
17 * seed as an argument, and doesn't xor at the end. Then individual
19 * drivers/net/smc9194.c uses seed ~0, doesn't xor with ~0.
20 * fs/jffs2 uses seed 0, doesn't xor with ~0.
21 * fs/partitions/efi.c uses seed ~0, xor's with ~0.
56 /* implements slicing-by-4 or slicing-by-8 algorithm */
[all …]
/linux-6.12.1/drivers/dma/ioat/
Ddma.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
23 #define to_dev(ioat_chan) (&(ioat_chan)->ioat_dma->pdev->dev)
24 #define to_pdev(ioat_chan) ((ioat_chan)->ioat_dma->pdev)
26 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->ioat_dma->reg_base) / 0x80)
30 #define src_cnt_to_hw(x) ((x) - 2)
32 #define ndest_to_hw(x) ((x) - 1)
34 #define src16_cnt_to_hw(x) ((x) - 9)
50 * struct ioatdma_device - internal representation of a IOAT device
51 * @pdev: PCI-Express device
[all …]
/linux-6.12.1/drivers/dma/
Dmv_xor_v2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015-2016 Marvell International Ltd.
8 #include <linux/dma-mapping.h>
53 /* XOR Global registers */
95 * struct mv_xor_v2_descriptor - DMA HW descriptor
101 * @fill_pattern_src_addr: Fill-Pattern or Source-Address and
102 * AW-Attributes
117 #define DESC_OP_MODE_MEMCPY 1 /* Pure-DMA operation */
118 #define DESC_OP_MODE_MEMSET 2 /* Mem-Fill operation */
119 #define DESC_OP_MODE_MEMINIT 3 /* Mem-Init operation */
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Dfsl_raid.c13 * Copyright (c) 2010-2014 Freescale Semiconductor, Inc.
45 * RAID Engine (RE) block is capable of offloading XOR, memcpy and P/Q
67 #include <linux/dma-mapping.h>
86 /* Add descriptors into per chan software queue - submit_q */
95 re_chan = container_of(tx->chan, struct fsl_re_chan, chan); in fsl_re_tx_submit()
97 spin_lock_irqsave(&re_chan->desc_lock, flags); in fsl_re_tx_submit()
99 list_add_tail(&desc->node, &re_chan->submit_q); in fsl_re_tx_submit()
100 spin_unlock_irqrestore(&re_chan->desc_lock, flags); in fsl_re_tx_submit()
115 spin_lock_irqsave(&re_chan->desc_lock, flags); in fsl_re_issue_pending()
117 in_be32(&re_chan->jrregs->inbring_slot_avail)); in fsl_re_issue_pending()
[all …]
/linux-6.12.1/drivers/input/keyboard/
Djornada680_kbd.c1 // SPDX-License-Identifier: GPL-2.0-only
43 /* PTD1 */ KEY_CAPSLOCK, KEY_MACRO, KEY_LEFTCTRL, 0, KEY_ESC, KEY_KP5, 0, 0, /* 1 -> 8 */
44 KEY_F1, KEY_F2, KEY_F3, KEY_F8, KEY_F7, KEY_F6, KEY_F4, KEY_F5, /* 9 -> 16 */
45 /* PTD5 */ KEY_SLASH, KEY_APOSTROPHE, KEY_ENTER, 0, KEY_Z, 0, 0, 0, /* 17 -> 24 */
46 KEY_X, KEY_C, KEY_V, KEY_DOT, KEY_COMMA, KEY_M, KEY_B, KEY_N, /* 25 -> 32 */
47 /* PTD7 */ KEY_KP2, KEY_KP6, KEY_KP3, 0, 0, 0, 0, 0, /* 33 -> 40 */
48 …KEY_F10, KEY_RO, KEY_F9, KEY_KP4, KEY_NUMLOCK, KEY_SCROLLLOCK, KEY_LEFTALT, KEY_HANJA, /* 41 -> 4…
49 /* PTE0 */ KEY_KATAKANA, KEY_KP0, KEY_GRAVE, 0, KEY_FINANCE, 0, 0, 0, /* 49 -> 56 */
50 KEY_KPMINUS, KEY_HIRAGANA, KEY_SPACE, KEY_KPDOT, KEY_VOLUMEUP, 249, 0, 0, /* 57 -> 64 */
51 /* PTE1 */ KEY_SEMICOLON, KEY_RIGHTBRACE, KEY_BACKSLASH, 0, KEY_A, 0, 0, 0, /* 65 -> 72 */
[all …]
/linux-6.12.1/arch/loongarch/crypto/
Dcrc32-loongarch.c1 // SPDX-License-Identifier: GPL-2.0
3 * crc32.c - CRC32 and CRC32C using LoongArch crc* instructions
5 * Module based on mips/crypto/crc32-mips.c
9 * Copyright (C) 2020-2023 Loongson Technology Corporation Limited
15 #include <asm/cpu-features.h>
39 len -= sizeof(u64); in crc32_loongarch_hw()
74 len -= sizeof(u64); in crc32c_loongarch_hw()
113 struct chksum_ctx *mctx = crypto_shash_ctx(desc->tfm); in chksum_init()
116 ctx->crc = mctx->key; in chksum_init()
122 * Setting the seed allows arbitrary accumulators and flexible XOR policy
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