Lines Matching +full:xor +full:- +full:v2
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015-2016 Marvell International Ltd.
8 #include <linux/dma-mapping.h>
53 /* XOR Global registers */
95 * struct mv_xor_v2_descriptor - DMA HW descriptor
101 * @fill_pattern_src_addr: Fill-Pattern or Source-Address and
102 * AW-Attributes
117 #define DESC_OP_MODE_MEMCPY 1 /* Pure-DMA operation */
118 #define DESC_OP_MODE_MEMSET 2 /* Mem-Fill operation */
119 #define DESC_OP_MODE_MEMINIT 3 /* Mem-Init operation */
120 #define DESC_OP_MODE_MEM_COMPARE 4 /* Mem-Compare operation */
122 #define DESC_OP_MODE_XOR 6 /* RAID5 (XOR) operation */
123 #define DESC_OP_MODE_RAID6 7 /* RAID6 P&Q-generation */
136 * struct mv_xor_v2_device - implements a xor device
142 * @irq_tasklet: tasklet used for IRQ handling call-backs
175 * struct mv_xor_v2_sw_desc - implements a xor SW descriptor
203 * First word: Buffer-DX-Address-Low[31:0] in mv_xor_v2_set_data_buffers()
204 * Second word: Buffer-DX+1-Address-Low[31:0] in mv_xor_v2_set_data_buffers()
205 * Third word: DX+1-Buffer-Address-High[47:32] [31:16] in mv_xor_v2_set_data_buffers()
206 * DX-Buffer-Address-High[47:32] [15:0] in mv_xor_v2_set_data_buffers()
209 desc->data_buff_addr[arr_index] = lower_32_bits(src); in mv_xor_v2_set_data_buffers()
211 desc->data_buff_addr[arr_index + 2] &= ~0xFFFF; in mv_xor_v2_set_data_buffers()
212 desc->data_buff_addr[arr_index + 2] |= in mv_xor_v2_set_data_buffers()
215 desc->data_buff_addr[arr_index + 1] = in mv_xor_v2_set_data_buffers()
218 desc->data_buff_addr[arr_index + 2] &= ~0xFFFF0000; in mv_xor_v2_set_data_buffers()
219 desc->data_buff_addr[arr_index + 2] |= in mv_xor_v2_set_data_buffers()
231 writel(num_of_desc, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_ADD_OFF); in mv_xor_v2_add_desc_to_desq()
241 writel(num_of_desc, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_DEALLOC_OFF); in mv_xor_v2_free_desc_from_desq()
251 xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_CTRL_OFF); in mv_xor_v2_set_desc_size()
265 reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_THRD_OFF); in mv_xor_v2_enable_imsg_thrd()
269 writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_THRD_OFF); in mv_xor_v2_enable_imsg_thrd()
272 reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_TMOT); in mv_xor_v2_enable_imsg_thrd()
275 writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_TMOT); in mv_xor_v2_enable_imsg_thrd()
284 reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_DONE_OFF); in mv_xor_v2_interrupt_handler()
294 tasklet_schedule(&xor_dev->irq_tasklet); in mv_xor_v2_interrupt_handler()
310 container_of(tx->chan, struct mv_xor_v2_device, dmachan); in mv_xor_v2_tx_submit()
312 dev_dbg(xor_dev->dmadev.dev, in mv_xor_v2_tx_submit()
314 __func__, sw_desc, &sw_desc->async_tx); in mv_xor_v2_tx_submit()
317 spin_lock_bh(&xor_dev->lock); in mv_xor_v2_tx_submit()
321 dest_hw_desc = xor_dev->hw_desq_virt + xor_dev->hw_queue_idx; in mv_xor_v2_tx_submit()
323 memcpy(dest_hw_desc, &sw_desc->hw_desc, xor_dev->desc_size); in mv_xor_v2_tx_submit()
325 xor_dev->npendings++; in mv_xor_v2_tx_submit()
326 xor_dev->hw_queue_idx++; in mv_xor_v2_tx_submit()
327 if (xor_dev->hw_queue_idx >= MV_XOR_V2_DESC_NUM) in mv_xor_v2_tx_submit()
328 xor_dev->hw_queue_idx = 0; in mv_xor_v2_tx_submit()
330 spin_unlock_bh(&xor_dev->lock); in mv_xor_v2_tx_submit()
345 spin_lock_bh(&xor_dev->lock); in mv_xor_v2_prep_sw_desc()
347 if (list_empty(&xor_dev->free_sw_desc)) { in mv_xor_v2_prep_sw_desc()
348 spin_unlock_bh(&xor_dev->lock); in mv_xor_v2_prep_sw_desc()
350 tasklet_schedule(&xor_dev->irq_tasklet); in mv_xor_v2_prep_sw_desc()
354 list_for_each_entry(sw_desc, &xor_dev->free_sw_desc, free_list) { in mv_xor_v2_prep_sw_desc()
355 if (async_tx_test_ack(&sw_desc->async_tx)) { in mv_xor_v2_prep_sw_desc()
362 spin_unlock_bh(&xor_dev->lock); in mv_xor_v2_prep_sw_desc()
366 list_del(&sw_desc->free_list); in mv_xor_v2_prep_sw_desc()
369 spin_unlock_bh(&xor_dev->lock); in mv_xor_v2_prep_sw_desc()
387 dev_dbg(xor_dev->dmadev.dev, in mv_xor_v2_prep_dma_memcpy()
395 sw_desc->async_tx.flags = flags; in mv_xor_v2_prep_dma_memcpy()
398 hw_descriptor = &sw_desc->hw_desc; in mv_xor_v2_prep_dma_memcpy()
401 hw_descriptor->desc_id = sw_desc->idx; in mv_xor_v2_prep_dma_memcpy()
404 hw_descriptor->desc_ctrl = in mv_xor_v2_prep_dma_memcpy()
408 hw_descriptor->desc_ctrl |= DESC_IOD; in mv_xor_v2_prep_dma_memcpy()
411 hw_descriptor->fill_pattern_src_addr[0] = lower_32_bits(src); in mv_xor_v2_prep_dma_memcpy()
412 hw_descriptor->fill_pattern_src_addr[1] = in mv_xor_v2_prep_dma_memcpy()
416 hw_descriptor->fill_pattern_src_addr[2] = lower_32_bits(dest); in mv_xor_v2_prep_dma_memcpy()
417 hw_descriptor->fill_pattern_src_addr[3] = in mv_xor_v2_prep_dma_memcpy()
421 hw_descriptor->buff_size = len; in mv_xor_v2_prep_dma_memcpy()
424 return &sw_desc->async_tx; in mv_xor_v2_prep_dma_memcpy()
428 * Prepare a HW descriptor for a XOR operation
443 dev_dbg(xor_dev->dmadev.dev, in mv_xor_v2_prep_dma_xor()
451 sw_desc->async_tx.flags = flags; in mv_xor_v2_prep_dma_xor()
454 hw_descriptor = &sw_desc->hw_desc; in mv_xor_v2_prep_dma_xor()
457 hw_descriptor->desc_id = sw_desc->idx; in mv_xor_v2_prep_dma_xor()
459 /* Set the XOR control word */ in mv_xor_v2_prep_dma_xor()
460 hw_descriptor->desc_ctrl = in mv_xor_v2_prep_dma_xor()
462 hw_descriptor->desc_ctrl |= DESC_P_BUFFER_ENABLE; in mv_xor_v2_prep_dma_xor()
465 hw_descriptor->desc_ctrl |= DESC_IOD; in mv_xor_v2_prep_dma_xor()
471 hw_descriptor->desc_ctrl |= in mv_xor_v2_prep_dma_xor()
475 hw_descriptor->fill_pattern_src_addr[2] = lower_32_bits(dest); in mv_xor_v2_prep_dma_xor()
476 hw_descriptor->fill_pattern_src_addr[3] = in mv_xor_v2_prep_dma_xor()
480 hw_descriptor->buff_size = len; in mv_xor_v2_prep_dma_xor()
483 return &sw_desc->async_tx; in mv_xor_v2_prep_dma_xor()
502 hw_descriptor = &sw_desc->hw_desc; in mv_xor_v2_prep_dma_interrupt()
505 hw_descriptor->desc_id = sw_desc->idx; in mv_xor_v2_prep_dma_interrupt()
508 hw_descriptor->desc_ctrl = in mv_xor_v2_prep_dma_interrupt()
510 hw_descriptor->desc_ctrl |= DESC_IOD; in mv_xor_v2_prep_dma_interrupt()
513 return &sw_desc->async_tx; in mv_xor_v2_prep_dma_interrupt()
524 spin_lock_bh(&xor_dev->lock); in mv_xor_v2_issue_pending()
530 mv_xor_v2_add_desc_to_desq(xor_dev, xor_dev->npendings); in mv_xor_v2_issue_pending()
531 xor_dev->npendings = 0; in mv_xor_v2_issue_pending()
533 spin_unlock_bh(&xor_dev->lock); in mv_xor_v2_issue_pending()
542 reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_DONE_OFF); in mv_xor_v2_get_pending_params()
563 dev_dbg(xor_dev->dmadev.dev, "%s %d\n", __func__, __LINE__); in mv_xor_v2_tasklet()
571 xor_dev->hw_desq_virt + pending_ptr; in mv_xor_v2_tasklet()
575 &xor_dev->sw_desq[next_pending_hw_desc->desc_id]; in mv_xor_v2_tasklet()
578 if (next_pending_sw_desc->async_tx.cookie > 0) { in mv_xor_v2_tasklet()
580 * update the channel's completed cookie - no in mv_xor_v2_tasklet()
584 dma_cookie_complete(&next_pending_sw_desc->async_tx); in mv_xor_v2_tasklet()
586 dma_descriptor_unmap(&next_pending_sw_desc->async_tx); in mv_xor_v2_tasklet()
588 &next_pending_sw_desc->async_tx, NULL); in mv_xor_v2_tasklet()
591 dma_run_dependencies(&next_pending_sw_desc->async_tx); in mv_xor_v2_tasklet()
594 spin_lock(&xor_dev->lock); in mv_xor_v2_tasklet()
597 list_add(&next_pending_sw_desc->free_list, in mv_xor_v2_tasklet()
598 &xor_dev->free_sw_desc); in mv_xor_v2_tasklet()
601 spin_unlock(&xor_dev->lock); in mv_xor_v2_tasklet()
616 * Set DMA Interrupt-message (IMSG) parameters
620 struct mv_xor_v2_device *xor_dev = dev_get_drvdata(desc->dev); in mv_xor_v2_set_msi_msg()
622 writel(msg->address_lo, in mv_xor_v2_set_msi_msg()
623 xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_BALR_OFF); in mv_xor_v2_set_msi_msg()
624 writel(msg->address_hi & 0xFFFF, in mv_xor_v2_set_msi_msg()
625 xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_BAHR_OFF); in mv_xor_v2_set_msi_msg()
626 writel(msg->data, in mv_xor_v2_set_msi_msg()
627 xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_CDAT_OFF); in mv_xor_v2_set_msi_msg()
636 xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_SIZE_OFF); in mv_xor_v2_descq_init()
639 writel(lower_32_bits(xor_dev->hw_desq), in mv_xor_v2_descq_init()
640 xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_BALR_OFF); in mv_xor_v2_descq_init()
641 writel(upper_32_bits(xor_dev->hw_desq), in mv_xor_v2_descq_init()
642 xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_BAHR_OFF); in mv_xor_v2_descq_init()
649 * - OuterShareable - Snoops will be performed on CPU caches in mv_xor_v2_descq_init()
650 * - Enable cacheable - Bufferable, Modifiable, Other Allocate in mv_xor_v2_descq_init()
653 reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_ARATTR_OFF); in mv_xor_v2_descq_init()
657 writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_ARATTR_OFF); in mv_xor_v2_descq_init()
659 reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_AWATTR_OFF); in mv_xor_v2_descq_init()
663 writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_AWATTR_OFF); in mv_xor_v2_descq_init()
665 /* BW CTRL - set values to optimize the XOR performance: in mv_xor_v2_descq_init()
667 * - Set WrBurstLen & RdBurstLen - the unit will issue in mv_xor_v2_descq_init()
669 * - Limit the number of outstanding write & read data in mv_xor_v2_descq_init()
680 writel(reg, xor_dev->glob_base + MV_XOR_V2_GLOB_BW_CTRL); in mv_xor_v2_descq_init()
683 reg = readl(xor_dev->glob_base + MV_XOR_V2_GLOB_PAUSE); in mv_xor_v2_descq_init()
685 writel(reg, xor_dev->glob_base + MV_XOR_V2_GLOB_PAUSE); in mv_xor_v2_descq_init()
688 writel(0, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_STOP_OFF); in mv_xor_v2_descq_init()
697 /* Set this bit to disable to stop the XOR unit. */ in mv_xor_v2_suspend()
698 writel(0x1, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_STOP_OFF); in mv_xor_v2_suspend()
724 xor_dev = devm_kzalloc(&pdev->dev, sizeof(*xor_dev), GFP_KERNEL); in mv_xor_v2_probe()
726 return -ENOMEM; in mv_xor_v2_probe()
728 xor_dev->dma_base = devm_platform_ioremap_resource(pdev, 0); in mv_xor_v2_probe()
729 if (IS_ERR(xor_dev->dma_base)) in mv_xor_v2_probe()
730 return PTR_ERR(xor_dev->dma_base); in mv_xor_v2_probe()
732 xor_dev->glob_base = devm_platform_ioremap_resource(pdev, 1); in mv_xor_v2_probe()
733 if (IS_ERR(xor_dev->glob_base)) in mv_xor_v2_probe()
734 return PTR_ERR(xor_dev->glob_base); in mv_xor_v2_probe()
738 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); in mv_xor_v2_probe()
742 xor_dev->reg_clk = devm_clk_get_optional_enabled(&pdev->dev, "reg"); in mv_xor_v2_probe()
743 if (IS_ERR(xor_dev->reg_clk)) in mv_xor_v2_probe()
744 return PTR_ERR(xor_dev->reg_clk); in mv_xor_v2_probe()
746 xor_dev->clk = devm_clk_get_enabled(&pdev->dev, NULL); in mv_xor_v2_probe()
747 if (IS_ERR(xor_dev->clk)) in mv_xor_v2_probe()
748 return PTR_ERR(xor_dev->clk); in mv_xor_v2_probe()
750 ret = platform_device_msi_init_and_alloc_irqs(&pdev->dev, 1, in mv_xor_v2_probe()
755 xor_dev->irq = msi_get_virq(&pdev->dev, 0); in mv_xor_v2_probe()
757 ret = devm_request_irq(&pdev->dev, xor_dev->irq, in mv_xor_v2_probe()
759 dev_name(&pdev->dev), xor_dev); in mv_xor_v2_probe()
763 tasklet_setup(&xor_dev->irq_tasklet, mv_xor_v2_tasklet); in mv_xor_v2_probe()
765 xor_dev->desc_size = mv_xor_v2_set_desc_size(xor_dev); in mv_xor_v2_probe()
767 dma_cookie_init(&xor_dev->dmachan); in mv_xor_v2_probe()
774 xor_dev->hw_desq_virt = in mv_xor_v2_probe()
775 dma_alloc_coherent(&pdev->dev, in mv_xor_v2_probe()
776 xor_dev->desc_size * MV_XOR_V2_DESC_NUM, in mv_xor_v2_probe()
777 &xor_dev->hw_desq, GFP_KERNEL); in mv_xor_v2_probe()
778 if (!xor_dev->hw_desq_virt) { in mv_xor_v2_probe()
779 ret = -ENOMEM; in mv_xor_v2_probe()
784 xor_dev->sw_desq = devm_kcalloc(&pdev->dev, in mv_xor_v2_probe()
787 if (!xor_dev->sw_desq) { in mv_xor_v2_probe()
788 ret = -ENOMEM; in mv_xor_v2_probe()
792 spin_lock_init(&xor_dev->lock); in mv_xor_v2_probe()
795 INIT_LIST_HEAD(&xor_dev->free_sw_desc); in mv_xor_v2_probe()
800 xor_dev->sw_desq + i; in mv_xor_v2_probe()
801 sw_desc->idx = i; in mv_xor_v2_probe()
802 dma_async_tx_descriptor_init(&sw_desc->async_tx, in mv_xor_v2_probe()
803 &xor_dev->dmachan); in mv_xor_v2_probe()
804 sw_desc->async_tx.tx_submit = mv_xor_v2_tx_submit; in mv_xor_v2_probe()
805 async_tx_ack(&sw_desc->async_tx); in mv_xor_v2_probe()
807 list_add(&sw_desc->free_list, in mv_xor_v2_probe()
808 &xor_dev->free_sw_desc); in mv_xor_v2_probe()
811 dma_dev = &xor_dev->dmadev; in mv_xor_v2_probe()
814 dma_cap_zero(dma_dev->cap_mask); in mv_xor_v2_probe()
815 dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask); in mv_xor_v2_probe()
816 dma_cap_set(DMA_XOR, dma_dev->cap_mask); in mv_xor_v2_probe()
817 dma_cap_set(DMA_INTERRUPT, dma_dev->cap_mask); in mv_xor_v2_probe()
820 INIT_LIST_HEAD(&dma_dev->channels); in mv_xor_v2_probe()
823 dma_dev->device_tx_status = dma_cookie_status; in mv_xor_v2_probe()
824 dma_dev->device_issue_pending = mv_xor_v2_issue_pending; in mv_xor_v2_probe()
825 dma_dev->dev = &pdev->dev; in mv_xor_v2_probe()
827 dma_dev->device_prep_dma_memcpy = mv_xor_v2_prep_dma_memcpy; in mv_xor_v2_probe()
828 dma_dev->device_prep_dma_interrupt = mv_xor_v2_prep_dma_interrupt; in mv_xor_v2_probe()
829 dma_dev->max_xor = 8; in mv_xor_v2_probe()
830 dma_dev->device_prep_dma_xor = mv_xor_v2_prep_dma_xor; in mv_xor_v2_probe()
832 xor_dev->dmachan.device = dma_dev; in mv_xor_v2_probe()
834 list_add_tail(&xor_dev->dmachan.device_node, in mv_xor_v2_probe()
835 &dma_dev->channels); in mv_xor_v2_probe()
845 dev_notice(&pdev->dev, "Marvell Version 2 XOR driver\n"); in mv_xor_v2_probe()
850 dma_free_coherent(&pdev->dev, in mv_xor_v2_probe()
851 xor_dev->desc_size * MV_XOR_V2_DESC_NUM, in mv_xor_v2_probe()
852 xor_dev->hw_desq_virt, xor_dev->hw_desq); in mv_xor_v2_probe()
854 platform_device_msi_free_irqs_all(&pdev->dev); in mv_xor_v2_probe()
862 dma_async_device_unregister(&xor_dev->dmadev); in mv_xor_v2_remove()
864 dma_free_coherent(&pdev->dev, in mv_xor_v2_remove()
865 xor_dev->desc_size * MV_XOR_V2_DESC_NUM, in mv_xor_v2_remove()
866 xor_dev->hw_desq_virt, xor_dev->hw_desq); in mv_xor_v2_remove()
868 devm_free_irq(&pdev->dev, xor_dev->irq, xor_dev); in mv_xor_v2_remove()
870 platform_device_msi_free_irqs_all(&pdev->dev); in mv_xor_v2_remove()
872 tasklet_kill(&xor_dev->irq_tasklet); in mv_xor_v2_remove()
877 { .compatible = "marvell,xor-v2", },
896 MODULE_DESCRIPTION("DMA engine driver for Marvell's Version 2 of XOR engine");