Lines Matching +full:xor +full:- +full:v2
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Hardware-accelerated CRC-32 variants for Linux on z Systems
6 * computing of bitreflected CRC-32 checksums for IEEE 802.3 Ethernet
9 * This CRC-32 implementation algorithm is bitreflected and processes
10 * the least-significant bit first (Little-Endian).
18 #include "crc32-vx.h"
20 /* Vector register range containing CRC-32 constants */
29 * The CRC-32 constant block contains reduction constants to fold and
32 * For the CRC-32 variants, the constants are precomputed according to
36 * R2 = [(x4*128-32 mod P'(x) << 32)]' << 1
38 * R4 = [(x128-32 mod P'(x) << 32)]' << 1
48 * CRC-32 (IEEE 802.3 Ethernet, ...) polynomials:
53 * CRC-32C (Castagnoli) polynomials:
60 0x0f0e0d0c0b0a0908, 0x0706050403020100, /* BE->LE mask */
69 0x0f0e0d0c0b0a0908, 0x0706050403020100, /* BE->LE mask */
78 * crc32_le_vgfm_generic - Compute CRC-32 (LE variant) with vector registers
83 * @constants: CRC-32 constant pool base pointer.
89 * V9: Constant for BE->LE conversion and shift operations
90 * V10..V14: CRC-32 constants.
94 /* Load CRC-32 constants */ in crc32_le_vgfm_generic()
107 /* Load a 64-byte data chunk and XOR with CRC */ in crc32_le_vgfm_generic()
116 size -= 64; in crc32_le_vgfm_generic()
129 * contents in V2, V3, and V4 respectively. in crc32_le_vgfm_generic()
136 size -= 64; in crc32_le_vgfm_generic()
140 * Fold V1 to V4 into a single 128-bit value in V1. Multiply V1 with R3 in crc32_le_vgfm_generic()
141 * and R4 and accumulating the next 128-bit chunk until a single 128-bit in crc32_le_vgfm_generic()
153 size -= 16; in crc32_le_vgfm_generic()
158 * be loaded in bits 1-4 in byte element 7 of a vector register. in crc32_le_vgfm_generic()
181 * Now do the final 32-bit fold by multiplying the rightmost word in crc32_le_vgfm_generic()
182 * in V1 with R5 and XOR the result with the remaining bits in V1. in crc32_le_vgfm_generic()
185 * and store the result in V2 which is then accumulated. Use the in crc32_le_vgfm_generic()
194 fpu_vsrlb(2, 1, 9); /* Store remaining bits in V2 */ in crc32_le_vgfm_generic()
196 fpu_vgfmag(1, CONST_R5, 1, 2); /* V1 = (V1 * R5) XOR V2 */ in crc32_le_vgfm_generic()
199 * Apply a Barret reduction to compute the final 32-bit CRC value. in crc32_le_vgfm_generic()
201 * The input values to the Barret reduction are the degree-63 polynomial in crc32_le_vgfm_generic()
202 * in V1 (R(x)), degree-32 generator polynomial, and the reduction in crc32_le_vgfm_generic()
210 * 3. C(x) = R(x) XOR T2(x) mod x^32 in crc32_le_vgfm_generic()
223 * V2 and XOR the intermediate result, T2(x), with the value in V1. in crc32_le_vgfm_generic()
224 * The final result is stored in word element 2 of V2. in crc32_le_vgfm_generic()