| /linux-6.12.1/drivers/net/ethernet/microchip/sparx5/ |
| D | sparx5_vcap_impl.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver VCAP implementation
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
66 .vtype = VCAP_TYPE_IS0, /* CLM-0 */
72 .last_cid = SPARX5_VCAP_CID_IS0_L2 - 1,
73 .blockno = 8, /* Maps block 8-9 */
78 .vtype = VCAP_TYPE_IS0, /* CLM-1 */
84 .last_cid = SPARX5_VCAP_CID_IS0_L4 - 1,
85 .blockno = 6, /* Maps block 6-7 */
[all …]
|
| D | sparx5_switchdev.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
19 struct sparx5 *sparx5; member
27 return -EINVAL; in sparx5_port_attr_pre_bridge_flags()
34 bool should_flood = flood_flag || port->is_mrouter; in sparx5_port_update_mcast_ip_flood()
58 struct sparx5 *sparx5 = port->sparx5; in sparx5_attr_stp_state_set() local
60 if (!test_bit(port->portno, sparx5->bridge_mask)) { in sparx5_attr_stp_state_set()
61 netdev_err(port->ndev, in sparx5_attr_stp_state_set()
62 "Controlling non-bridged port %d?\n", port->portno); in sparx5_attr_stp_state_set()
66 switch (state) { in sparx5_attr_stp_state_set()
[all …]
|
| D | sparx5_vcap_debugfs.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver VCAP debugFS implementation
18 switch (value) { in sparx5_vcap_is0_etype_str()
42 switch (value) { in sparx5_vcap_is0_mpls_str()
66 switch (value) { in sparx5_vcap_is0_mlbs_str()
76 static void sparx5_vcap_is0_port_keys(struct sparx5 *sparx5, in sparx5_vcap_is0_port_keys() argument
84 out->prf(out->dst, " port[%02d] (%s): ", port->portno, in sparx5_vcap_is0_port_keys()
85 netdev_name(port->ndev)); in sparx5_vcap_is0_port_keys()
86 for (lookup = 0; lookup < admin->lookups; ++lookup) { in sparx5_vcap_is0_port_keys()
87 out->prf(out->dst, "\n Lookup %d: ", lookup); in sparx5_vcap_is0_port_keys()
[all …]
|
| D | sparx5_main.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
33 ((SPX5_BUFFER_MEMORY / SPX5_BUFFER_CELL_SZ - 100) * (fraction) / 100)
217 static int sparx5_create_targets(struct sparx5 *sparx5) in sparx5_create_targets() argument
228 if (idx == iomap->range) { in sparx5_create_targets()
234 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM, in sparx5_create_targets()
237 dev_err(sparx5->dev, "Invalid resource\n"); in sparx5_create_targets()
238 return -EINVAL; in sparx5_create_targets()
[all …]
|
| D | sparx5_port.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
31 status->an_complete = true; in decode_sgmii_word()
33 status->link = false; in decode_sgmii_word()
37 switch (lp_abil & LPA_SGMII_SPD_MASK) { in decode_sgmii_word()
39 status->speed = SPEED_10; in decode_sgmii_word()
42 status->speed = SPEED_100; in decode_sgmii_word()
45 status->speed = SPEED_1000; in decode_sgmii_word()
48 status->link = false; in decode_sgmii_word()
52 status->duplex = DUPLEX_FULL; in decode_sgmii_word()
[all …]
|
| D | sparx5_ptp.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
27 static u64 sparx5_ptp_get_1ppm(struct sparx5 *sparx5) in sparx5_ptp_get_1ppm() argument
32 * (1/1000000)/((2^-59)/X) in sparx5_ptp_get_1ppm()
37 switch (sparx5->coreclock) { in sparx5_ptp_get_1ppm()
55 static u64 sparx5_ptp_get_nominal_value(struct sparx5 *sparx5) in sparx5_ptp_get_nominal_value() argument
59 switch (sparx5->coreclock) { in sparx5_ptp_get_nominal_value()
81 struct sparx5 *sparx5 = port->sparx5; in sparx5_ptp_hwtstamp_set() local
[all …]
|
| D | sparx5_police.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
10 static int sparx5_policer_service_conf_set(struct sparx5 *sparx5, in sparx5_policer_service_conf_set() argument
17 g = &sdlb_groups[pol->group]; in sparx5_policer_service_conf_set()
18 idx = pol->idx; in sparx5_policer_service_conf_set()
20 rate = pol->rate * 1000; in sparx5_policer_service_conf_set()
21 burst = pol->burst; in sparx5_policer_service_conf_set()
23 pup_tokens = sparx5_sdlb_pup_token_get(sparx5, g->pup_interval, rate); in sparx5_policer_service_conf_set()
25 sparx5_sdlb_pup_token_get(sparx5, g->pup_interval, g->max_rate); in sparx5_policer_service_conf_set()
27 thres = DIV_ROUND_UP(burst, g->min_burst); in sparx5_policer_service_conf_set()
[all …]
|
| D | sparx5_calendar.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
53 static u32 sparx5_target_bandwidth(struct sparx5 *sparx5) in sparx5_target_bandwidth() argument
55 switch (sparx5->target_ct) { in sparx5_target_bandwidth()
90 switch (cclock) { in sparx5_clk_to_bandwidth()
101 switch (speed) { in sparx5_cal_speed_to_value()
115 switch (bw) { in sparx5_bandwidth_to_calendar()
129 static enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, in sparx5_get_port_cal_speed() argument
152 /* Front ports - may be used */ in sparx5_get_port_cal_speed()
153 port = sparx5->ports[portno]; in sparx5_get_port_cal_speed()
[all …]
|
| D | sparx5_tc_matchall.c | 1 // SPDX-License-Identifier: GPL-2.0+
20 if (entry->cookie == cookie) in sparx5_tc_matchall_entry_find()
33 entry->port = port; in sparx5_tc_matchall_parse_action()
34 entry->type = action->id; in sparx5_tc_matchall_parse_action()
35 entry->ingress = ingress; in sparx5_tc_matchall_parse_action()
36 entry->cookie = cookie; in sparx5_tc_matchall_parse_action()
43 entry->mirror.port = netdev_priv(action->dev); in sparx5_tc_matchall_parse_mirror_action()
53 struct sparx5 *sparx5; in sparx5_tc_matchall_replace() local
56 if (!flow_offload_has_one_action(&tmo->rule->action)) { in sparx5_tc_matchall_replace()
57 NL_SET_ERR_MSG_MOD(tmo->common.extack, in sparx5_tc_matchall_replace()
[all …]
|
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Makefile for the Microchip Sparx5 network device drivers.
6 obj-$(CONFIG_SPARX5_SWITCH) += sparx5-switch.o
8 sparx5-switch-y := sparx5_main.o sparx5_packet.o \
16 sparx5-switch-$(CONFIG_SPARX5_DCB) += sparx5_dcb.o
17 sparx5-switch-$(CONFIG_DEBUG_FS) += sparx5_vcap_debugfs.o
20 ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/vcap
21 ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma
|
| D | sparx5_main.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Microchip Sparx5 Switch driver
29 SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */
30 SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */
31 SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */
32 SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */
33 SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */
34 SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */
35 SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */
36 SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */
[all …]
|
| D | sparx5_packet.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
19 #define XTR_VALID_BYTES(x) (4 - ((x) & 3))
23 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp) in sparx5_xtr_flush() argument
26 spx5_wr(QS_XTR_FLUSH_FLUSH_SET(BIT(grp)), sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
32 spx5_wr(0, sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
39 /* FWD is bit 45-72 (28 bits), but we only read the 27 LSB for now */ in sparx5_ifh_parse()
46 info->src_port = FIELD_GET(GENMASK(7, 1), fwd); in sparx5_ifh_parse()
49 * Bit 270-271 are occasionally unexpectedly set by the hardware, in sparx5_ifh_parse()
52 info->timestamp = in sparx5_ifh_parse()
[all …]
|
| D | sparx5_mirror.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
25 static u64 sparx5_mirror_port_get(struct sparx5 *sparx5, u32 idx) in sparx5_mirror_port_get() argument
27 return (u64)spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG1(idx)) << 32 | in sparx5_mirror_port_get()
28 spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG(idx)); in sparx5_mirror_port_get()
32 static void sparx5_mirror_port_add(struct sparx5 *sparx5, u32 idx, u32 portno) in sparx5_mirror_port_add() argument
40 return spx5_rmw(val, val, sparx5, ANA_AC_PROBE_PORT_CFG(idx)); in sparx5_mirror_port_add()
42 return spx5_rmw(val, val, sparx5, ANA_AC_PROBE_PORT_CFG1(idx)); in sparx5_mirror_port_add()
46 static void sparx5_mirror_port_del(struct sparx5 *sparx5, u32 idx, u32 portno) in sparx5_mirror_port_del() argument
54 return spx5_rmw(0, val, sparx5, ANA_AC_PROBE_PORT_CFG(idx)); in sparx5_mirror_port_del()
[all …]
|
| D | sparx5_vlan.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
10 static int sparx5_vlant_set_mask(struct sparx5 *sparx5, u16 vid) in sparx5_vlant_set_mask() argument
15 bitmap_to_arr32(mask, sparx5->vlan_mask[vid], SPX5_PORTS); in sparx5_vlant_set_mask()
18 spx5_wr(mask[0], sparx5, ANA_L3_VLAN_MASK_CFG(vid)); in sparx5_vlant_set_mask()
19 spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid)); in sparx5_vlant_set_mask()
20 spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid)); in sparx5_vlant_set_mask()
25 void sparx5_vlan_init(struct sparx5 *sparx5) in sparx5_vlan_init() argument
31 sparx5, in sparx5_vlan_init()
38 sparx5, in sparx5_vlan_init()
[all …]
|
| D | sparx5_sdlb.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
23 int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5) in sparx5_sdlb_clk_hz_get() argument
28 clk_per_100ps = HSCH_SYS_CLK_PER_100PS_GET(spx5_rd(sparx5, in sparx5_sdlb_clk_hz_get()
37 static int sparx5_sdlb_pup_interval_get(struct sparx5 *sparx5, u32 max_token, in sparx5_sdlb_pup_interval_get() argument
42 clk_hz = sparx5_sdlb_clk_hz_get(sparx5); in sparx5_sdlb_pup_interval_get()
47 int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval, u64 rate) in sparx5_sdlb_pup_token_get() argument
54 clk_hz = sparx5_sdlb_clk_hz_get(sparx5); in sparx5_sdlb_pup_token_get()
59 static void sparx5_sdlb_group_disable(struct sparx5 *sparx5, u32 group) in sparx5_sdlb_group_disable() argument
62 ANA_AC_SDLB_PUP_CTRL_PUP_ENA, sparx5, in sparx5_sdlb_group_disable()
[all …]
|
| D | sparx5_psfp.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
55 u32 sparx5_psfp_isdx_get_sf(struct sparx5 *sparx5, u32 isdx) in sparx5_psfp_isdx_get_sf() argument
57 return ANA_L2_TSN_CFG_TSN_SFID_GET(spx5_rd(sparx5, in sparx5_psfp_isdx_get_sf()
61 u32 sparx5_psfp_isdx_get_fm(struct sparx5 *sparx5, u32 isdx) in sparx5_psfp_isdx_get_fm() argument
63 return ANA_L2_DLB_CFG_DLB_IDX_GET(spx5_rd(sparx5, in sparx5_psfp_isdx_get_fm()
67 u32 sparx5_psfp_sf_get_sg(struct sparx5 *sparx5, u32 sfid) in sparx5_psfp_sf_get_sg() argument
69 return ANA_AC_TSN_SF_CFG_TSN_SGID_GET(spx5_rd(sparx5, in sparx5_psfp_sf_get_sg()
73 void sparx5_isdx_conf_set(struct sparx5 *sparx5, u32 isdx, u32 sfid, u32 fmid) in sparx5_isdx_conf_set() argument
76 sparx5, ANA_L2_TSN_CFG(isdx)); in sparx5_isdx_conf_set()
[all …]
|
| D | sparx5_port.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Microchip Sparx5 Switch driver
69 port - 12 : port - 44; in sparx5_port_dev_index()
70 return (port - 56); in sparx5_port_dev_index()
73 int sparx5_port_init(struct sparx5 *sparx5,
77 int sparx5_port_config(struct sparx5 *sparx5,
81 int sparx5_port_pcs_set(struct sparx5 *sparx5,
85 int sparx5_serdes_set(struct sparx5 *sparx5,
98 int sparx5_get_port_status(struct sparx5 *sparx5,
103 int sparx5_port_fwd_urg(struct sparx5 *sparx5, u32 speed);
|
| D | sparx5_tc_flower.c | 1 // SPDX-License-Identifier: GPL-2.0+
39 /* SparX-5 VCAP fragment types:
41 * 2 = suspicious fragment, 3 = valid follow-up fragment
57 /* 0/0 0/1 1/0 1/1 <-- first_frag */
65 switch (st->tpid) { in sparx5_tc_flower_es0_tpid()
67 err = vcap_rule_add_key_u32(st->vrule, in sparx5_tc_flower_es0_tpid()
72 err = vcap_rule_add_key_u32(st->vrule, in sparx5_tc_flower_es0_tpid()
77 NL_SET_ERR_MSG_MOD(st->fco->common.extack, in sparx5_tc_flower_es0_tpid()
79 err = -EINVAL; in sparx5_tc_flower_es0_tpid()
91 flow_rule_match_basic(st->frule, &mt); in sparx5_tc_flower_handler_basic_usage()
[all …]
|
| D | sparx5_netdev.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
21 /* Max width is 5 bytes - 40 bits. In worst case this will
22 * spread over 6 bytes - 48 bits
33 u32 byte = (35 - (pos / 8)); in __ifh_encode_bitfield()
36 u64 encode = GENMASK_ULL(bit + width - 1, bit) & (value << bit); in __ifh_encode_bitfield()
38 /* The b0-b7 goes into the start IFH byte */ in __ifh_encode_bitfield()
41 /* The b8-b15 goes into the next IFH byte */ in __ifh_encode_bitfield()
43 ifh_hdr[byte - 1] |= (u8)((encode & 0xFF00) >> 8); in __ifh_encode_bitfield()
44 /* The b16-b23 goes into the next IFH byte */ in __ifh_encode_bitfield()
[all …]
|
| D | sparx5_mactable.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
44 static int sparx5_mact_get_status(struct sparx5 *sparx5) in sparx5_mact_get_status() argument
46 return spx5_rd(sparx5, LRN_COMMON_ACCESS_CTRL); in sparx5_mact_get_status()
49 static int sparx5_mact_wait_for_completion(struct sparx5 *sparx5) in sparx5_mact_wait_for_completion() argument
54 sparx5, val, in sparx5_mact_wait_for_completion()
59 static void sparx5_mact_select(struct sparx5 *sparx5, in sparx5_mact_select() argument
76 spx5_wr(mach, sparx5, LRN_MAC_ACCESS_CFG_0); in sparx5_mact_select()
77 spx5_wr(macl, sparx5, LRN_MAC_ACCESS_CFG_1); in sparx5_mact_select()
80 int sparx5_mact_learn(struct sparx5 *sparx5, int pgid, in sparx5_mact_learn() argument
[all …]
|
| D | sparx5_fdma.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
15 #include <linux/dma-mapping.h>
30 *dataptr = fdma->dma + (sizeof(struct fdma_dcb) * fdma->n_dcbs) + in sparx5_fdma_tx_dataptr_cb()
31 ((dcb * fdma->n_dbs + db) * fdma->db_size); in sparx5_fdma_tx_dataptr_cb()
39 struct sparx5 *sparx5 = fdma->priv; in sparx5_fdma_rx_dataptr_cb() local
40 struct sparx5_rx *rx = &sparx5->rx; in sparx5_fdma_rx_dataptr_cb()
43 skb = __netdev_alloc_skb(rx->ndev, fdma->db_size, GFP_ATOMIC); in sparx5_fdma_rx_dataptr_cb()
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/arm/ |
| D | microchip,sparx5.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Sparx5 Boards
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
[all …]
|
| /linux-6.12.1/arch/arm64/boot/dts/microchip/ |
| D | sparx5.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
11 compatible = "microchip,sparx5";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <1>;
23 stdout-path = "serial0:115200n8";
27 #address-cells = <1>;
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/reset/ |
| D | microchip,rst.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Sparx5 Switch Reset Controller
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
14 The Microchip Sparx5 Switch provides reset control and implements the following
16 - One Time Switch Core Reset (Soft Reset)
20 pattern: "^reset-controller@[0-9a-f]+$"
24 - microchip,sparx5-switch-reset
[all …]
|
| /linux-6.12.1/drivers/reset/ |
| D | reset-microchip-sparx5.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch Reset driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
15 #include <linux/reset-controller.h>
42 regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg, in sparx5_switch_reset()
43 ctx->props->protect_bit, ctx->props->protect_bit); in sparx5_switch_reset()
46 regmap_write(ctx->gcb_ctrl, ctx->props->reset_reg, in sparx5_switch_reset()
47 ctx->props->reset_bit); in sparx5_switch_reset()
50 return regmap_read_poll_timeout(ctx->gcb_ctrl, ctx->props->reset_reg, val, in sparx5_switch_reset()
[all …]
|