Lines Matching +full:sparx5 +full:- +full:switch
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
33 ((SPX5_BUFFER_MEMORY / SPX5_BUFFER_CELL_SZ - 100) * (fraction) / 100)
217 static int sparx5_create_targets(struct sparx5 *sparx5) in sparx5_create_targets() argument
228 if (idx == iomap->range) { in sparx5_create_targets()
234 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM, in sparx5_create_targets()
237 dev_err(sparx5->dev, "Invalid resource\n"); in sparx5_create_targets()
238 return -EINVAL; in sparx5_create_targets()
240 iomem[idx] = devm_ioremap(sparx5->dev, in sparx5_create_targets()
241 iores[idx]->start, in sparx5_create_targets()
244 dev_err(sparx5->dev, "Unable to get switch registers: %s\n", in sparx5_create_targets()
245 iores[idx]->name); in sparx5_create_targets()
246 return -ENOMEM; in sparx5_create_targets()
248 begin[idx] = iomem[idx] - sparx5_main_iomap[range_id[idx]].offset; in sparx5_create_targets()
253 sparx5->regs[iomap->id] = begin[iomap->range] + iomap->offset; in sparx5_create_targets()
258 static int sparx5_create_port(struct sparx5 *sparx5, in sparx5_create_port() argument
266 ndev = sparx5_create_netdev(sparx5, config->portno); in sparx5_create_port()
268 dev_err(sparx5->dev, "Could not create net device: %02u\n", in sparx5_create_port()
269 config->portno); in sparx5_create_port()
273 spx5_port->of_node = config->node; in sparx5_create_port()
274 spx5_port->serdes = config->serdes; in sparx5_create_port()
275 spx5_port->pvid = NULL_VID; in sparx5_create_port()
276 spx5_port->signd_internal = true; in sparx5_create_port()
277 spx5_port->signd_active_high = true; in sparx5_create_port()
278 spx5_port->signd_enable = true; in sparx5_create_port()
279 spx5_port->max_vlan_tags = SPX5_PORT_MAX_TAGS_NONE; in sparx5_create_port()
280 spx5_port->vlan_type = SPX5_VLAN_PORT_TYPE_UNAWARE; in sparx5_create_port()
281 spx5_port->custom_etype = 0x8880; /* Vitesse */ in sparx5_create_port()
282 spx5_port->phylink_pcs.poll = true; in sparx5_create_port()
283 spx5_port->phylink_pcs.ops = &sparx5_phylink_pcs_ops; in sparx5_create_port()
284 spx5_port->phylink_pcs.neg_mode = true; in sparx5_create_port()
285 spx5_port->is_mrouter = false; in sparx5_create_port()
286 INIT_LIST_HEAD(&spx5_port->tc_templates); in sparx5_create_port()
287 sparx5->ports[config->portno] = spx5_port; in sparx5_create_port()
289 err = sparx5_port_init(sparx5, spx5_port, &config->conf); in sparx5_create_port()
291 dev_err(sparx5->dev, "port init failed\n"); in sparx5_create_port()
294 spx5_port->conf = config->conf; in sparx5_create_port()
297 sparx5_vlan_port_setup(sparx5, spx5_port->portno); in sparx5_create_port()
300 spx5_port->phylink_config.dev = &spx5_port->ndev->dev; in sparx5_create_port()
301 spx5_port->phylink_config.type = PHYLINK_NETDEV; in sparx5_create_port()
302 spx5_port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | in sparx5_create_port()
307 spx5_port->phylink_config.supported_interfaces); in sparx5_create_port()
309 spx5_port->phylink_config.supported_interfaces); in sparx5_create_port()
311 spx5_port->phylink_config.supported_interfaces); in sparx5_create_port()
313 spx5_port->phylink_config.supported_interfaces); in sparx5_create_port()
315 if (spx5_port->conf.bandwidth == SPEED_5000 || in sparx5_create_port()
316 spx5_port->conf.bandwidth == SPEED_10000 || in sparx5_create_port()
317 spx5_port->conf.bandwidth == SPEED_25000) in sparx5_create_port()
319 spx5_port->phylink_config.supported_interfaces); in sparx5_create_port()
321 if (spx5_port->conf.bandwidth == SPEED_10000 || in sparx5_create_port()
322 spx5_port->conf.bandwidth == SPEED_25000) in sparx5_create_port()
324 spx5_port->phylink_config.supported_interfaces); in sparx5_create_port()
326 if (spx5_port->conf.bandwidth == SPEED_25000) in sparx5_create_port()
328 spx5_port->phylink_config.supported_interfaces); in sparx5_create_port()
330 phylink = phylink_create(&spx5_port->phylink_config, in sparx5_create_port()
331 of_fwnode_handle(config->node), in sparx5_create_port()
332 config->conf.phy_mode, in sparx5_create_port()
337 spx5_port->phylink = phylink; in sparx5_create_port()
342 static int sparx5_init_ram(struct sparx5 *s5) in sparx5_init_ram()
364 writel(cfg->init_val, cfg->init_reg); in sparx5_init_ram()
366 value = readl(cfg->init_reg); in sparx5_init_ram()
367 if ((value & cfg->init_val) != cfg->init_val) in sparx5_init_ram()
368 pending--; in sparx5_init_ram()
380 dev_err(s5->dev, "Memory initialization error\n"); in sparx5_init_ram()
381 return -EINVAL; in sparx5_init_ram()
386 static int sparx5_init_switchcore(struct sparx5 *sparx5) in sparx5_init_switchcore() argument
393 sparx5, in sparx5_init_switchcore()
398 sparx5, in sparx5_init_switchcore()
402 value = spx5_rd(sparx5, HSCH_RESET_CFG); in sparx5_init_switchcore()
404 err = sparx5_init_ram(sparx5); in sparx5_init_switchcore()
410 spx5_wr(ANA_AC_STAT_RESET_RESET_SET(1), sparx5, ANA_AC_STAT_RESET); in sparx5_init_switchcore()
411 spx5_wr(ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(1), sparx5, ASM_STAT_CFG); in sparx5_init_switchcore()
413 /* Enable switch-core and queue system */ in sparx5_init_switchcore()
414 spx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1), sparx5, HSCH_RESET_CFG); in sparx5_init_switchcore()
419 static int sparx5_init_coreclock(struct sparx5 *sparx5) in sparx5_init_coreclock() argument
421 enum sparx5_core_clockfreq freq = sparx5->coreclock; in sparx5_init_coreclock()
428 switch (sparx5->target_ct) { in sparx5_init_coreclock()
430 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
432 else if (sparx5->coreclock != SPX5_CORE_CLOCK_250MHZ) in sparx5_init_coreclock()
438 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
440 else if (sparx5->coreclock != SPX5_CORE_CLOCK_500MHZ) in sparx5_init_coreclock()
445 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
447 else if (sparx5->coreclock != SPX5_CORE_CLOCK_625MHZ) in sparx5_init_coreclock()
451 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
457 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
459 else if (sparx5->coreclock == SPX5_CORE_CLOCK_250MHZ) in sparx5_init_coreclock()
463 dev_err(sparx5->dev, "Target (%#04x) not supported\n", in sparx5_init_coreclock()
464 sparx5->target_ct); in sparx5_init_coreclock()
465 return -ENODEV; in sparx5_init_coreclock()
468 switch (freq) { in sparx5_init_coreclock()
482 dev_err(sparx5->dev, "%d coreclock not supported on (%#04x)\n", in sparx5_init_coreclock()
483 sparx5->coreclock, sparx5->target_ct); in sparx5_init_coreclock()
484 return -EINVAL; in sparx5_init_coreclock()
488 sparx5->coreclock = freq; in sparx5_init_coreclock()
503 sparx5, in sparx5_init_coreclock()
510 sparx5, in sparx5_init_coreclock()
515 sparx5, in sparx5_init_coreclock()
520 sparx5, in sparx5_init_coreclock()
525 sparx5, in sparx5_init_coreclock()
531 sparx5, in sparx5_init_coreclock()
537 sparx5, in sparx5_init_coreclock()
542 sparx5, in sparx5_init_coreclock()
548 static int sparx5_qlim_set(struct sparx5 *sparx5) in sparx5_qlim_set() argument
554 spx5_wr(0xFFF, sparx5, in sparx5_qlim_set()
558 spx5_wr(0xFFF, sparx5, in sparx5_qlim_set()
563 spx5_wr(QLIM_WM(80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); in sparx5_qlim_set()
564 spx5_wr(QLIM_WM(90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); in sparx5_qlim_set()
565 spx5_wr(QLIM_WM(95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); in sparx5_qlim_set()
566 spx5_wr(QLIM_WM(100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); in sparx5_qlim_set()
574 static void sparx5_board_init(struct sparx5 *sparx5) in sparx5_board_init() argument
578 if (!sparx5->sd_sgpio_remapping) in sparx5_board_init()
584 sparx5, in sparx5_board_init()
589 if (sparx5->ports[idx]) in sparx5_board_init()
590 if (sparx5->ports[idx]->conf.sd_sgpio != ~0) in sparx5_board_init()
591 spx5_wr(sparx5->ports[idx]->conf.sd_sgpio, in sparx5_board_init()
592 sparx5, in sparx5_board_init()
596 static int sparx5_start(struct sparx5 *sparx5) in sparx5_start() argument
605 spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx)); in sparx5_start()
606 spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx)); in sparx5_start()
607 spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx)); in sparx5_start()
608 spx5_wr(idx, sparx5, REW_OWN_UPSID(idx)); in sparx5_start()
615 sparx5, in sparx5_start()
619 sparx5_update_fwd(sparx5); in sparx5_start()
623 sparx5, ANA_AC_PGID_MISC_CFG(PGID_CPU)); in sparx5_start()
625 sparx5, ANA_AC_PGID_MISC_CFG(PGID_BCAST)); in sparx5_start()
631 sparx5, ANA_CL_FILTER_CTRL(idx)); in sparx5_start()
634 sparx5_mact_init(sparx5); in sparx5_start()
637 sparx5_pgid_init(sparx5); in sparx5_start()
640 sparx5_vlan_init(sparx5); in sparx5_start()
643 sparx5_mact_learn(sparx5, PGID_CPU, broadcast, NULL_VID); in sparx5_start()
646 sparx5_qlim_set(sparx5); in sparx5_start()
648 err = sparx5_config_auto_calendar(sparx5); in sparx5_start()
652 err = sparx5_config_dsm_calendar(sparx5); in sparx5_start()
657 err = sparx_stats_init(sparx5); in sparx5_start()
662 mutex_init(&sparx5->mact_lock); in sparx5_start()
663 INIT_LIST_HEAD(&sparx5->mact_entries); in sparx5_start()
664 snprintf(queue_name, sizeof(queue_name), "%s-mact", in sparx5_start()
665 dev_name(sparx5->dev)); in sparx5_start()
666 sparx5->mact_queue = create_singlethread_workqueue(queue_name); in sparx5_start()
667 if (!sparx5->mact_queue) in sparx5_start()
668 return -ENOMEM; in sparx5_start()
670 INIT_DELAYED_WORK(&sparx5->mact_work, sparx5_mact_pull_work); in sparx5_start()
671 queue_delayed_work(sparx5->mact_queue, &sparx5->mact_work, in sparx5_start()
674 mutex_init(&sparx5->mdb_lock); in sparx5_start()
675 INIT_LIST_HEAD(&sparx5->mdb_entries); in sparx5_start()
677 err = sparx5_register_netdevs(sparx5); in sparx5_start()
681 sparx5_board_init(sparx5); in sparx5_start()
682 err = sparx5_register_notifier_blocks(sparx5); in sparx5_start()
686 err = sparx5_vcap_init(sparx5); in sparx5_start()
688 sparx5_unregister_notifier_blocks(sparx5); in sparx5_start()
693 err = -ENXIO; in sparx5_start()
694 if (sparx5->fdma_irq >= 0) { in sparx5_start()
695 if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0) in sparx5_start()
696 err = devm_request_threaded_irq(sparx5->dev, in sparx5_start()
697 sparx5->fdma_irq, in sparx5_start()
701 "sparx5-fdma", sparx5); in sparx5_start()
703 err = sparx5_fdma_start(sparx5); in sparx5_start()
705 sparx5->fdma_irq = -ENXIO; in sparx5_start()
707 sparx5->fdma_irq = -ENXIO; in sparx5_start()
709 if (err && sparx5->xtr_irq >= 0) { in sparx5_start()
710 err = devm_request_irq(sparx5->dev, sparx5->xtr_irq, in sparx5_start()
712 "sparx5-xtr", sparx5); in sparx5_start()
714 err = sparx5_manual_injection_mode(sparx5); in sparx5_start()
716 sparx5->xtr_irq = -ENXIO; in sparx5_start()
718 sparx5->xtr_irq = -ENXIO; in sparx5_start()
721 if (sparx5->ptp_irq >= 0) { in sparx5_start()
722 err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq, in sparx5_start()
724 IRQF_ONESHOT, "sparx5-ptp", in sparx5_start()
725 sparx5); in sparx5_start()
727 sparx5->ptp_irq = -ENXIO; in sparx5_start()
729 sparx5->ptp = 1; in sparx5_start()
735 static void sparx5_cleanup_ports(struct sparx5 *sparx5) in sparx5_cleanup_ports() argument
737 sparx5_unregister_netdevs(sparx5); in sparx5_cleanup_ports()
738 sparx5_destroy_netdevs(sparx5); in sparx5_cleanup_ports()
744 struct device_node *np = pdev->dev.of_node; in mchp_sparx5_probe()
747 struct sparx5 *sparx5; in mchp_sparx5_probe() local
750 if (!np && !pdev->dev.platform_data) in mchp_sparx5_probe()
751 return -ENODEV; in mchp_sparx5_probe()
753 sparx5 = devm_kzalloc(&pdev->dev, sizeof(*sparx5), GFP_KERNEL); in mchp_sparx5_probe()
754 if (!sparx5) in mchp_sparx5_probe()
755 return -ENOMEM; in mchp_sparx5_probe()
757 platform_set_drvdata(pdev, sparx5); in mchp_sparx5_probe()
758 sparx5->pdev = pdev; in mchp_sparx5_probe()
759 sparx5->dev = &pdev->dev; in mchp_sparx5_probe()
760 spin_lock_init(&sparx5->tx_lock); in mchp_sparx5_probe()
762 /* Do switch core reset if available */ in mchp_sparx5_probe()
763 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); in mchp_sparx5_probe()
765 return dev_err_probe(&pdev->dev, PTR_ERR(reset), in mchp_sparx5_probe()
766 "Failed to get switch reset controller.\n"); in mchp_sparx5_probe()
770 sparx5->coreclock = SPX5_CORE_CLOCK_DEFAULT; in mchp_sparx5_probe()
772 sparx5->debugfs_root = debugfs_create_dir("sparx5", NULL); in mchp_sparx5_probe()
774 ports = of_get_child_by_name(np, "ethernet-ports"); in mchp_sparx5_probe()
776 dev_err(sparx5->dev, "no ethernet-ports child node found\n"); in mchp_sparx5_probe()
777 return -ENODEV; in mchp_sparx5_probe()
779 sparx5->port_count = of_get_child_count(ports); in mchp_sparx5_probe()
781 configs = kcalloc(sparx5->port_count, in mchp_sparx5_probe()
784 err = -ENOMEM; in mchp_sparx5_probe()
795 dev_err(sparx5->dev, "port reg property error\n"); in mchp_sparx5_probe()
799 conf = &config->conf; in mchp_sparx5_probe()
800 conf->speed = SPEED_UNKNOWN; in mchp_sparx5_probe()
801 conf->bandwidth = SPEED_UNKNOWN; in mchp_sparx5_probe()
802 err = of_get_phy_mode(portnp, &conf->phy_mode); in mchp_sparx5_probe()
804 dev_err(sparx5->dev, "port %u: missing phy-mode\n", in mchp_sparx5_probe()
809 &conf->bandwidth); in mchp_sparx5_probe()
811 dev_err(sparx5->dev, "port %u: missing bandwidth\n", in mchp_sparx5_probe()
815 err = of_property_read_u32(portnp, "microchip,sd-sgpio", &conf->sd_sgpio); in mchp_sparx5_probe()
817 conf->sd_sgpio = ~0; in mchp_sparx5_probe()
819 sparx5->sd_sgpio_remapping = true; in mchp_sparx5_probe()
820 serdes = devm_of_phy_get(sparx5->dev, portnp, NULL); in mchp_sparx5_probe()
822 err = dev_err_probe(sparx5->dev, PTR_ERR(serdes), in mchp_sparx5_probe()
828 config->portno = portno; in mchp_sparx5_probe()
829 config->node = portnp; in mchp_sparx5_probe()
830 config->serdes = serdes; in mchp_sparx5_probe()
832 conf->media = PHY_MEDIA_DAC; in mchp_sparx5_probe()
833 conf->serdes_reset = true; in mchp_sparx5_probe()
834 conf->portmode = conf->phy_mode; in mchp_sparx5_probe()
835 conf->power_down = true; in mchp_sparx5_probe()
839 err = sparx5_create_targets(sparx5); in mchp_sparx5_probe()
843 if (of_get_mac_address(np, sparx5->base_mac)) { in mchp_sparx5_probe()
844 dev_info(sparx5->dev, "MAC addr was not set, use random MAC\n"); in mchp_sparx5_probe()
845 eth_random_addr(sparx5->base_mac); in mchp_sparx5_probe()
846 sparx5->base_mac[5] = 0; in mchp_sparx5_probe()
849 sparx5->fdma_irq = platform_get_irq_byname(sparx5->pdev, "fdma"); in mchp_sparx5_probe()
850 sparx5->xtr_irq = platform_get_irq_byname(sparx5->pdev, "xtr"); in mchp_sparx5_probe()
851 sparx5->ptp_irq = platform_get_irq_byname(sparx5->pdev, "ptp"); in mchp_sparx5_probe()
854 sparx5->chip_id = spx5_rd(sparx5, GCB_CHIP_ID); in mchp_sparx5_probe()
856 sparx5->target_ct = (enum spx5_target_chiptype) in mchp_sparx5_probe()
857 GCB_CHIP_ID_PART_ID_GET(sparx5->chip_id); in mchp_sparx5_probe()
860 err = sparx5_init_switchcore(sparx5); in mchp_sparx5_probe()
862 dev_err(sparx5->dev, "Switchcore initialization error\n"); in mchp_sparx5_probe()
866 /* Initialize the LC-PLL (core clock) and set affected registers */ in mchp_sparx5_probe()
867 err = sparx5_init_coreclock(sparx5); in mchp_sparx5_probe()
869 dev_err(sparx5->dev, "LC-PLL initialization error\n"); in mchp_sparx5_probe()
873 for (idx = 0; idx < sparx5->port_count; ++idx) { in mchp_sparx5_probe()
875 if (!config->node) in mchp_sparx5_probe()
878 err = sparx5_create_port(sparx5, config); in mchp_sparx5_probe()
880 dev_err(sparx5->dev, "port create error\n"); in mchp_sparx5_probe()
885 err = sparx5_start(sparx5); in mchp_sparx5_probe()
887 dev_err(sparx5->dev, "Start failed\n"); in mchp_sparx5_probe()
891 err = sparx5_qos_init(sparx5); in mchp_sparx5_probe()
893 dev_err(sparx5->dev, "Failed to initialize QoS\n"); in mchp_sparx5_probe()
897 err = sparx5_ptp_init(sparx5); in mchp_sparx5_probe()
899 dev_err(sparx5->dev, "PTP failed\n"); in mchp_sparx5_probe()
903 INIT_LIST_HEAD(&sparx5->mall_entries); in mchp_sparx5_probe()
908 sparx5_cleanup_ports(sparx5); in mchp_sparx5_probe()
909 if (sparx5->mact_queue) in mchp_sparx5_probe()
910 destroy_workqueue(sparx5->mact_queue); in mchp_sparx5_probe()
920 struct sparx5 *sparx5 = platform_get_drvdata(pdev); in mchp_sparx5_remove() local
922 debugfs_remove_recursive(sparx5->debugfs_root); in mchp_sparx5_remove()
923 if (sparx5->xtr_irq) { in mchp_sparx5_remove()
924 disable_irq(sparx5->xtr_irq); in mchp_sparx5_remove()
925 sparx5->xtr_irq = -ENXIO; in mchp_sparx5_remove()
927 if (sparx5->fdma_irq) { in mchp_sparx5_remove()
928 disable_irq(sparx5->fdma_irq); in mchp_sparx5_remove()
929 sparx5->fdma_irq = -ENXIO; in mchp_sparx5_remove()
931 sparx5_ptp_deinit(sparx5); in mchp_sparx5_remove()
932 sparx5_fdma_stop(sparx5); in mchp_sparx5_remove()
933 sparx5_cleanup_ports(sparx5); in mchp_sparx5_remove()
934 sparx5_vcap_destroy(sparx5); in mchp_sparx5_remove()
936 sparx5_unregister_notifier_blocks(sparx5); in mchp_sparx5_remove()
937 destroy_workqueue(sparx5->mact_queue); in mchp_sparx5_remove()
941 { .compatible = "microchip,sparx5-switch" },
950 .name = "sparx5-switch",
957 MODULE_DESCRIPTION("Microchip Sparx5 switch driver");