Lines Matching +full:sparx5 +full:- +full:switch
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
15 #include <linux/dma-mapping.h>
30 *dataptr = fdma->dma + (sizeof(struct fdma_dcb) * fdma->n_dcbs) + in sparx5_fdma_tx_dataptr_cb()
31 ((dcb * fdma->n_dbs + db) * fdma->db_size); in sparx5_fdma_tx_dataptr_cb()
39 struct sparx5 *sparx5 = fdma->priv; in sparx5_fdma_rx_dataptr_cb() local
40 struct sparx5_rx *rx = &sparx5->rx; in sparx5_fdma_rx_dataptr_cb()
43 skb = __netdev_alloc_skb(rx->ndev, fdma->db_size, GFP_ATOMIC); in sparx5_fdma_rx_dataptr_cb()
45 return -ENOMEM; in sparx5_fdma_rx_dataptr_cb()
47 *dataptr = virt_to_phys(skb->data); in sparx5_fdma_rx_dataptr_cb()
49 rx->skb[dcb][db] = skb; in sparx5_fdma_rx_dataptr_cb()
54 static void sparx5_fdma_rx_activate(struct sparx5 *sparx5, struct sparx5_rx *rx) in sparx5_fdma_rx_activate() argument
56 struct fdma *fdma = &rx->fdma; in sparx5_fdma_rx_activate()
59 spx5_wr(((u64)fdma->dma) & GENMASK(31, 0), sparx5, in sparx5_fdma_rx_activate()
60 FDMA_DCB_LLP(fdma->channel_id)); in sparx5_fdma_rx_activate()
61 spx5_wr(((u64)fdma->dma) >> 32, sparx5, in sparx5_fdma_rx_activate()
62 FDMA_DCB_LLP1(fdma->channel_id)); in sparx5_fdma_rx_activate()
64 /* Set the number of RX DBs to be used, and DB end-of-frame interrupt */ in sparx5_fdma_rx_activate()
65 spx5_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | in sparx5_fdma_rx_activate()
68 sparx5, FDMA_CH_CFG(fdma->channel_id)); in sparx5_fdma_rx_activate()
72 sparx5, in sparx5_fdma_rx_activate()
77 sparx5, FDMA_PORT_CTRL(0)); in sparx5_fdma_rx_activate()
80 spx5_rmw(BIT(fdma->channel_id), in sparx5_fdma_rx_activate()
81 BIT(fdma->channel_id) & FDMA_INTR_DB_ENA_INTR_DB_ENA, in sparx5_fdma_rx_activate()
82 sparx5, FDMA_INTR_DB_ENA); in sparx5_fdma_rx_activate()
85 spx5_wr(BIT(fdma->channel_id), sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_rx_activate()
88 static void sparx5_fdma_rx_deactivate(struct sparx5 *sparx5, struct sparx5_rx *rx) in sparx5_fdma_rx_deactivate() argument
90 struct fdma *fdma = &rx->fdma; in sparx5_fdma_rx_deactivate()
93 spx5_rmw(0, BIT(fdma->channel_id) & FDMA_CH_ACTIVATE_CH_ACTIVATE, in sparx5_fdma_rx_deactivate()
94 sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_rx_deactivate()
97 spx5_rmw(0, BIT(fdma->channel_id) & FDMA_INTR_DB_ENA_INTR_DB_ENA, in sparx5_fdma_rx_deactivate()
98 sparx5, FDMA_INTR_DB_ENA); in sparx5_fdma_rx_deactivate()
102 sparx5, FDMA_PORT_CTRL(0)); in sparx5_fdma_rx_deactivate()
105 static void sparx5_fdma_tx_activate(struct sparx5 *sparx5, struct sparx5_tx *tx) in sparx5_fdma_tx_activate() argument
107 struct fdma *fdma = &tx->fdma; in sparx5_fdma_tx_activate()
110 spx5_wr(((u64)fdma->dma) & GENMASK(31, 0), sparx5, in sparx5_fdma_tx_activate()
111 FDMA_DCB_LLP(fdma->channel_id)); in sparx5_fdma_tx_activate()
112 spx5_wr(((u64)fdma->dma) >> 32, sparx5, in sparx5_fdma_tx_activate()
113 FDMA_DCB_LLP1(fdma->channel_id)); in sparx5_fdma_tx_activate()
115 /* Set the number of TX DBs to be used, and DB end-of-frame interrupt */ in sparx5_fdma_tx_activate()
116 spx5_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | in sparx5_fdma_tx_activate()
119 sparx5, FDMA_CH_CFG(fdma->channel_id)); in sparx5_fdma_tx_activate()
123 sparx5, FDMA_PORT_CTRL(0)); in sparx5_fdma_tx_activate()
126 spx5_wr(BIT(fdma->channel_id), sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_tx_activate()
129 static void sparx5_fdma_tx_deactivate(struct sparx5 *sparx5, struct sparx5_tx *tx) in sparx5_fdma_tx_deactivate() argument
132 spx5_rmw(0, BIT(tx->fdma.channel_id) & FDMA_CH_ACTIVATE_CH_ACTIVATE, in sparx5_fdma_tx_deactivate()
133 sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_tx_deactivate()
136 static void sparx5_fdma_reload(struct sparx5 *sparx5, struct fdma *fdma) in sparx5_fdma_reload() argument
139 spx5_wr(BIT(fdma->channel_id), sparx5, FDMA_CH_RELOAD); in sparx5_fdma_reload()
142 static bool sparx5_fdma_rx_get_frame(struct sparx5 *sparx5, struct sparx5_rx *rx) in sparx5_fdma_rx_get_frame() argument
144 struct fdma *fdma = &rx->fdma; in sparx5_fdma_rx_get_frame()
154 skb = rx->skb[fdma->dcb_index][fdma->db_index]; in sparx5_fdma_rx_get_frame()
157 sparx5_ifh_parse((u32 *)skb->data, &fi); in sparx5_fdma_rx_get_frame()
159 port = fi.src_port < SPX5_PORTS ? sparx5->ports[fi.src_port] : NULL; in sparx5_fdma_rx_get_frame()
160 if (!port || !port->ndev) { in sparx5_fdma_rx_get_frame()
161 dev_err(sparx5->dev, "Data on inactive port %d\n", fi.src_port); in sparx5_fdma_rx_get_frame()
162 sparx5_xtr_flush(sparx5, XTR_QUEUE); in sparx5_fdma_rx_get_frame()
165 skb->dev = port->ndev; in sparx5_fdma_rx_get_frame()
167 if (likely(!(skb->dev->features & NETIF_F_RXFCS))) in sparx5_fdma_rx_get_frame()
168 skb_trim(skb, skb->len - ETH_FCS_LEN); in sparx5_fdma_rx_get_frame()
170 sparx5_ptp_rxtstamp(sparx5, skb, fi.timestamp); in sparx5_fdma_rx_get_frame()
171 skb->protocol = eth_type_trans(skb, skb->dev); in sparx5_fdma_rx_get_frame()
175 if (test_bit(port->portno, sparx5->bridge_mask)) in sparx5_fdma_rx_get_frame()
176 skb->offload_fwd_mark = 1; in sparx5_fdma_rx_get_frame()
177 skb->dev->stats.rx_bytes += skb->len; in sparx5_fdma_rx_get_frame()
178 skb->dev->stats.rx_packets++; in sparx5_fdma_rx_get_frame()
179 rx->packets++; in sparx5_fdma_rx_get_frame()
187 struct sparx5 *sparx5 = container_of(rx, struct sparx5, rx); in sparx5_fdma_napi_callback() local
188 struct fdma *fdma = &rx->fdma; in sparx5_fdma_napi_callback()
191 while (counter < weight && sparx5_fdma_rx_get_frame(sparx5, rx)) { in sparx5_fdma_napi_callback()
197 fdma_dcb_add(fdma, fdma->dcb_index, in sparx5_fdma_napi_callback()
198 FDMA_DCB_INFO_DATAL(fdma->db_size), in sparx5_fdma_napi_callback()
204 napi_complete_done(&rx->napi, counter); in sparx5_fdma_napi_callback()
205 spx5_rmw(BIT(fdma->channel_id), in sparx5_fdma_napi_callback()
206 BIT(fdma->channel_id) & FDMA_INTR_DB_ENA_INTR_DB_ENA, in sparx5_fdma_napi_callback()
207 sparx5, FDMA_INTR_DB_ENA); in sparx5_fdma_napi_callback()
210 sparx5_fdma_reload(sparx5, fdma); in sparx5_fdma_napi_callback()
214 int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb) in sparx5_fdma_xmit() argument
216 struct sparx5_tx *tx = &sparx5->tx; in sparx5_fdma_xmit()
217 struct fdma *fdma = &tx->fdma; in sparx5_fdma_xmit()
222 if (!fdma_db_is_done(fdma_db_get(fdma, fdma->dcb_index, 0))) in sparx5_fdma_xmit()
223 return -EINVAL; in sparx5_fdma_xmit()
226 virt_addr = ((u8 *)fdma->dcbs + in sparx5_fdma_xmit()
227 (sizeof(struct fdma_dcb) * fdma->n_dcbs) + in sparx5_fdma_xmit()
228 ((fdma->dcb_index * fdma->n_dbs) * fdma->db_size)); in sparx5_fdma_xmit()
231 memcpy(virt_addr + IFH_LEN * 4, skb->data, skb->len); in sparx5_fdma_xmit()
233 fdma_dcb_add(fdma, fdma->dcb_index, 0, in sparx5_fdma_xmit()
237 FDMA_DCB_STATUS_BLOCKL(skb->len + IFH_LEN * 4 + 4)); in sparx5_fdma_xmit()
240 sparx5_fdma_tx_activate(sparx5, tx); in sparx5_fdma_xmit()
243 sparx5_fdma_reload(sparx5, fdma); in sparx5_fdma_xmit()
248 static int sparx5_fdma_rx_alloc(struct sparx5 *sparx5) in sparx5_fdma_rx_alloc() argument
250 struct sparx5_rx *rx = &sparx5->rx; in sparx5_fdma_rx_alloc()
251 struct fdma *fdma = &rx->fdma; in sparx5_fdma_rx_alloc()
258 fdma_dcbs_init(fdma, FDMA_DCB_INFO_DATAL(fdma->db_size), in sparx5_fdma_rx_alloc()
261 netif_napi_add_weight(rx->ndev, &rx->napi, sparx5_fdma_napi_callback, in sparx5_fdma_rx_alloc()
263 napi_enable(&rx->napi); in sparx5_fdma_rx_alloc()
264 sparx5_fdma_rx_activate(sparx5, rx); in sparx5_fdma_rx_alloc()
268 static int sparx5_fdma_tx_alloc(struct sparx5 *sparx5) in sparx5_fdma_tx_alloc() argument
270 struct sparx5_tx *tx = &sparx5->tx; in sparx5_fdma_tx_alloc()
271 struct fdma *fdma = &tx->fdma; in sparx5_fdma_tx_alloc()
278 fdma_dcbs_init(fdma, FDMA_DCB_INFO_DATAL(fdma->db_size), in sparx5_fdma_tx_alloc()
284 static void sparx5_fdma_rx_init(struct sparx5 *sparx5, in sparx5_fdma_rx_init() argument
287 struct fdma *fdma = &rx->fdma; in sparx5_fdma_rx_init()
290 fdma->channel_id = channel; in sparx5_fdma_rx_init()
291 fdma->n_dcbs = FDMA_DCB_MAX; in sparx5_fdma_rx_init()
292 fdma->n_dbs = FDMA_RX_DCB_MAX_DBS; in sparx5_fdma_rx_init()
293 fdma->priv = sparx5; in sparx5_fdma_rx_init()
294 fdma->db_size = ALIGN(FDMA_XTR_BUFFER_SIZE, PAGE_SIZE); in sparx5_fdma_rx_init()
295 fdma->size = fdma_get_size(&sparx5->rx.fdma); in sparx5_fdma_rx_init()
296 fdma->ops.dataptr_cb = &sparx5_fdma_rx_dataptr_cb; in sparx5_fdma_rx_init()
297 fdma->ops.nextptr_cb = &fdma_nextptr_cb; in sparx5_fdma_rx_init()
300 struct sparx5_port *port = sparx5->ports[idx]; in sparx5_fdma_rx_init()
302 if (port && port->ndev) { in sparx5_fdma_rx_init()
303 rx->ndev = port->ndev; in sparx5_fdma_rx_init()
309 static void sparx5_fdma_tx_init(struct sparx5 *sparx5, in sparx5_fdma_tx_init() argument
312 struct fdma *fdma = &tx->fdma; in sparx5_fdma_tx_init()
314 fdma->channel_id = channel; in sparx5_fdma_tx_init()
315 fdma->n_dcbs = FDMA_DCB_MAX; in sparx5_fdma_tx_init()
316 fdma->n_dbs = FDMA_TX_DCB_MAX_DBS; in sparx5_fdma_tx_init()
317 fdma->priv = sparx5; in sparx5_fdma_tx_init()
318 fdma->db_size = ALIGN(FDMA_XTR_BUFFER_SIZE, PAGE_SIZE); in sparx5_fdma_tx_init()
319 fdma->size = fdma_get_size_contiguous(&sparx5->tx.fdma); in sparx5_fdma_tx_init()
320 fdma->ops.dataptr_cb = &sparx5_fdma_tx_dataptr_cb; in sparx5_fdma_tx_init()
321 fdma->ops.nextptr_cb = &fdma_nextptr_cb; in sparx5_fdma_tx_init()
326 struct sparx5 *sparx5 = args; in sparx5_fdma_handler() local
329 db = spx5_rd(sparx5, FDMA_INTR_DB); in sparx5_fdma_handler()
330 err = spx5_rd(sparx5, FDMA_INTR_ERR); in sparx5_fdma_handler()
333 spx5_wr(0, sparx5, FDMA_INTR_DB_ENA); in sparx5_fdma_handler()
334 spx5_wr(db, sparx5, FDMA_INTR_DB); in sparx5_fdma_handler()
335 napi_schedule(&sparx5->rx.napi); in sparx5_fdma_handler()
338 u32 err_type = spx5_rd(sparx5, FDMA_ERRORS); in sparx5_fdma_handler()
340 dev_err_ratelimited(sparx5->dev, in sparx5_fdma_handler()
343 spx5_wr(err, sparx5, FDMA_INTR_ERR); in sparx5_fdma_handler()
344 spx5_wr(err_type, sparx5, FDMA_ERRORS); in sparx5_fdma_handler()
349 static void sparx5_fdma_injection_mode(struct sparx5 *sparx5) in sparx5_fdma_injection_mode() argument
359 sparx5, QS_XTR_GRP_CFG(XTR_QUEUE)); in sparx5_fdma_injection_mode()
362 sparx5, QS_INJ_GRP_CFG(INJ_QUEUE)); in sparx5_fdma_injection_mode()
370 sparx5, ASM_PORT_CFG(portno)); in sparx5_fdma_injection_mode()
375 sparx5, in sparx5_fdma_injection_mode()
381 sparx5, in sparx5_fdma_injection_mode()
385 urgency = sparx5_port_fwd_urg(sparx5, SPEED_2500); in sparx5_fdma_injection_mode()
390 sparx5, in sparx5_fdma_injection_mode()
398 sparx5, in sparx5_fdma_injection_mode()
404 sparx5, in sparx5_fdma_injection_mode()
409 int sparx5_fdma_start(struct sparx5 *sparx5) in sparx5_fdma_start() argument
414 spx5_wr(FDMA_CTRL_NRESET_SET(0), sparx5, FDMA_CTRL); in sparx5_fdma_start()
415 spx5_wr(FDMA_CTRL_NRESET_SET(1), sparx5, FDMA_CTRL); in sparx5_fdma_start()
424 sparx5, CPU_PROC_CTRL); in sparx5_fdma_start()
426 sparx5_fdma_injection_mode(sparx5); in sparx5_fdma_start()
427 sparx5_fdma_rx_init(sparx5, &sparx5->rx, FDMA_XTR_CHANNEL); in sparx5_fdma_start()
428 sparx5_fdma_tx_init(sparx5, &sparx5->tx, FDMA_INJ_CHANNEL); in sparx5_fdma_start()
429 err = sparx5_fdma_rx_alloc(sparx5); in sparx5_fdma_start()
431 dev_err(sparx5->dev, "Could not allocate RX buffers: %d\n", err); in sparx5_fdma_start()
434 err = sparx5_fdma_tx_alloc(sparx5); in sparx5_fdma_start()
436 dev_err(sparx5->dev, "Could not allocate TX buffers: %d\n", err); in sparx5_fdma_start()
442 static u32 sparx5_fdma_port_ctrl(struct sparx5 *sparx5) in sparx5_fdma_port_ctrl() argument
444 return spx5_rd(sparx5, FDMA_PORT_CTRL(0)); in sparx5_fdma_port_ctrl()
447 int sparx5_fdma_stop(struct sparx5 *sparx5) in sparx5_fdma_stop() argument
451 napi_disable(&sparx5->rx.napi); in sparx5_fdma_stop()
453 sparx5_fdma_rx_deactivate(sparx5, &sparx5->rx); in sparx5_fdma_stop()
454 sparx5_fdma_tx_deactivate(sparx5, &sparx5->tx); in sparx5_fdma_stop()
458 500, 10000, 0, sparx5); in sparx5_fdma_stop()
459 fdma_free_phys(&sparx5->rx.fdma); in sparx5_fdma_stop()
460 fdma_free_phys(&sparx5->tx.fdma); in sparx5_fdma_stop()