Lines Matching +full:sparx5 +full:- +full:switch
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
31 status->an_complete = true; in decode_sgmii_word()
33 status->link = false; in decode_sgmii_word()
37 switch (lp_abil & LPA_SGMII_SPD_MASK) { in decode_sgmii_word()
39 status->speed = SPEED_10; in decode_sgmii_word()
42 status->speed = SPEED_100; in decode_sgmii_word()
45 status->speed = SPEED_1000; in decode_sgmii_word()
48 status->link = false; in decode_sgmii_word()
52 status->duplex = DUPLEX_FULL; in decode_sgmii_word()
54 status->duplex = DUPLEX_HALF; in decode_sgmii_word()
59 status->link = !(lp_abil & ADVERTISE_RFAULT) && status->link; in decode_cl37_word()
60 status->an_complete = true; in decode_cl37_word()
61 status->duplex = (ADVERTISE_1000XFULL & lp_abil) ? in decode_cl37_word()
66 status->pause = MLO_PAUSE_RX | MLO_PAUSE_TX; in decode_cl37_word()
69 status->pause |= (lp_abil & ADVERTISE_1000XPAUSE) ? in decode_cl37_word()
71 status->pause |= (ld_abil & ADVERTISE_1000XPAUSE) ? in decode_cl37_word()
74 status->pause = MLO_PAUSE_NONE; in decode_cl37_word()
78 static int sparx5_get_dev2g5_status(struct sparx5 *sparx5, in sparx5_get_dev2g5_status() argument
82 u32 portno = port->portno; in sparx5_get_dev2g5_status()
87 value = spx5_rd(sparx5, DEV2G5_PCS1G_STICKY(portno)); in sparx5_get_dev2g5_status()
88 status->link_down = DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(value); in sparx5_get_dev2g5_status()
89 if (status->link_down) /* Clear the sticky */ in sparx5_get_dev2g5_status()
90 spx5_wr(value, sparx5, DEV2G5_PCS1G_STICKY(portno)); in sparx5_get_dev2g5_status()
93 value = spx5_rd(sparx5, DEV2G5_PCS1G_LINK_STATUS(portno)); in sparx5_get_dev2g5_status()
94 status->link = DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(value) && in sparx5_get_dev2g5_status()
97 if (port->conf.portmode == PHY_INTERFACE_MODE_1000BASEX) in sparx5_get_dev2g5_status()
98 status->speed = SPEED_1000; in sparx5_get_dev2g5_status()
99 else if (port->conf.portmode == PHY_INTERFACE_MODE_2500BASEX) in sparx5_get_dev2g5_status()
100 status->speed = SPEED_2500; in sparx5_get_dev2g5_status()
102 status->duplex = DUPLEX_FULL; in sparx5_get_dev2g5_status()
105 value = spx5_rd(sparx5, DEV2G5_PCS1G_ANEG_STATUS(portno)); in sparx5_get_dev2g5_status()
110 if (port->conf.portmode == PHY_INTERFACE_MODE_SGMII) { in sparx5_get_dev2g5_status()
113 value = spx5_rd(sparx5, DEV2G5_PCS1G_ANEG_CFG(portno)); in sparx5_get_dev2g5_status()
121 static int sparx5_get_sfi_status(struct sparx5 *sparx5, in sparx5_get_sfi_status() argument
125 bool high_speed_dev = sparx5_is_baser(port->conf.portmode); in sparx5_get_sfi_status()
126 u32 portno = port->portno; in sparx5_get_sfi_status()
131 netdev_err(port->ndev, "error: low speed and SFI mode\n"); in sparx5_get_sfi_status()
132 return -EINVAL; in sparx5_get_sfi_status()
137 inst = spx5_inst_get(sparx5, dev, tinst); in sparx5_get_sfi_status()
142 status->link_down = 1; in sparx5_get_sfi_status()
146 status->link = (value == DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY); in sparx5_get_sfi_status()
147 status->duplex = DUPLEX_FULL; in sparx5_get_sfi_status()
148 if (port->conf.portmode == PHY_INTERFACE_MODE_5GBASER) in sparx5_get_sfi_status()
149 status->speed = SPEED_5000; in sparx5_get_sfi_status()
150 else if (port->conf.portmode == PHY_INTERFACE_MODE_10GBASER) in sparx5_get_sfi_status()
151 status->speed = SPEED_10000; in sparx5_get_sfi_status()
153 status->speed = SPEED_25000; in sparx5_get_sfi_status()
158 /* Get link status of 1000Base-X/in-band and SFI ports.
160 int sparx5_get_port_status(struct sparx5 *sparx5, in sparx5_get_port_status() argument
165 status->speed = port->conf.speed; in sparx5_get_port_status()
166 if (port->conf.power_down) { in sparx5_get_port_status()
167 status->link = false; in sparx5_get_port_status()
170 switch (port->conf.portmode) { in sparx5_get_port_status()
175 return sparx5_get_dev2g5_status(sparx5, port, status); in sparx5_get_port_status()
179 return sparx5_get_sfi_status(sparx5, port, status); in sparx5_get_port_status()
183 netdev_err(port->ndev, "Status not supported"); in sparx5_get_port_status()
184 return -ENODEV; in sparx5_get_port_status()
193 switch (errtype) { in sparx5_port_error()
195 netdev_err(port->ndev, in sparx5_port_error()
197 conf->speed, phy_modes(conf->portmode)); in sparx5_port_error()
200 netdev_err(port->ndev, in sparx5_port_error()
201 "Switch port does not support interface type: %s\n", in sparx5_port_error()
202 phy_modes(conf->portmode)); in sparx5_port_error()
205 netdev_err(port->ndev, in sparx5_port_error()
209 return -EINVAL; in sparx5_port_error()
212 static int sparx5_port_verify_speed(struct sparx5 *sparx5, in sparx5_port_verify_speed() argument
216 if ((sparx5_port_is_2g5(port->portno) && in sparx5_port_verify_speed()
217 conf->speed > SPEED_2500) || in sparx5_port_verify_speed()
218 (sparx5_port_is_5g(port->portno) && in sparx5_port_verify_speed()
219 conf->speed > SPEED_5000) || in sparx5_port_verify_speed()
220 (sparx5_port_is_10g(port->portno) && in sparx5_port_verify_speed()
221 conf->speed > SPEED_10000)) in sparx5_port_verify_speed()
224 switch (conf->portmode) { in sparx5_port_verify_speed()
226 return -EINVAL; in sparx5_port_verify_speed()
228 if (conf->speed != SPEED_1000 || in sparx5_port_verify_speed()
229 sparx5_port_is_2g5(port->portno)) in sparx5_port_verify_speed()
231 if (sparx5_port_is_2g5(port->portno)) in sparx5_port_verify_speed()
235 if (conf->speed != SPEED_2500 || in sparx5_port_verify_speed()
236 sparx5_port_is_2g5(port->portno)) in sparx5_port_verify_speed()
240 if (port->portno > 47) in sparx5_port_verify_speed()
244 if (conf->speed != SPEED_1000 && in sparx5_port_verify_speed()
245 conf->speed != SPEED_100 && in sparx5_port_verify_speed()
246 conf->speed != SPEED_10 && in sparx5_port_verify_speed()
247 conf->speed != SPEED_2500) in sparx5_port_verify_speed()
253 if ((conf->speed != SPEED_5000 && in sparx5_port_verify_speed()
254 conf->speed != SPEED_10000 && in sparx5_port_verify_speed()
255 conf->speed != SPEED_25000)) in sparx5_port_verify_speed()
264 static bool sparx5_dev_change(struct sparx5 *sparx5, in sparx5_dev_change() argument
268 return sparx5_is_baser(port->conf.portmode) ^ in sparx5_dev_change()
269 sparx5_is_baser(conf->portmode); in sparx5_dev_change()
272 static int sparx5_port_flush_poll(struct sparx5 *sparx5, u32 portno) in sparx5_port_flush_poll() argument
278 /* Resource == 0: Memory tracked per source (SRC-MEM) in sparx5_port_flush_poll()
279 * Resource == 1: Frame references tracked per source (SRC-REF) in sparx5_port_flush_poll()
280 * Resource == 2: Memory tracked per destination (DST-MEM) in sparx5_port_flush_poll()
281 * Resource == 3: Frame references tracked per destination. (DST-REF) in sparx5_port_flush_poll()
291 value = spx5_rd(sparx5, in sparx5_port_flush_poll()
295 "DST-MEM" : "SRC-MEM"; in sparx5_port_flush_poll()
305 dev_err(sparx5->dev, in sparx5_port_flush_poll()
308 return -EINVAL; in sparx5_port_flush_poll()
316 static int sparx5_port_disable(struct sparx5 *sparx5, struct sparx5_port *port, bool high_spd_dev) in sparx5_port_disable() argument
319 sparx5_port_dev_index(port->portno) : port->portno; in sparx5_port_disable()
321 sparx5_to_high_dev(port->portno) : TARGET_DEV2G5; in sparx5_port_disable()
322 void __iomem *devinst = spx5_inst_get(sparx5, dev, tinst); in sparx5_port_disable()
323 u32 spd = port->conf.speed; in sparx5_port_disable()
351 /* 3: Disable traffic being sent to or from switch port->portno */ in sparx5_port_disable()
354 sparx5, in sparx5_port_disable()
355 QFWD_SWITCH_PORT_MODE(port->portno)); in sparx5_port_disable()
360 sparx5, in sparx5_port_disable()
361 HSCH_PORT_MODE(port->portno)); in sparx5_port_disable()
364 spx5_rmw(QSYS_PAUSE_CFG_PAUSE_STOP_SET(0xFFF - 1), in sparx5_port_disable()
366 sparx5, in sparx5_port_disable()
367 QSYS_PAUSE_CFG(port->portno)); in sparx5_port_disable()
373 /* 7: Flush the queues associated with the port->portno */ in sparx5_port_disable()
374 spx5_rmw(HSCH_FLUSH_CTRL_FLUSH_PORT_SET(port->portno) | in sparx5_port_disable()
382 sparx5, in sparx5_port_disable()
388 sparx5, in sparx5_port_disable()
389 HSCH_PORT_MODE(port->portno)); in sparx5_port_disable()
392 err = sparx5_port_flush_poll(sparx5, port->portno); in sparx5_port_disable()
422 spx5_rmw(HSCH_FLUSH_CTRL_FLUSH_PORT_SET(port->portno) | in sparx5_port_disable()
426 sparx5, in sparx5_port_disable()
430 u32 pcs = sparx5_to_pcs_dev(port->portno); in sparx5_port_disable()
431 void __iomem *pcsinst = spx5_inst_get(sparx5, pcs, tinst); in sparx5_port_disable()
439 if (sparx5_port_is_25g(port->portno)) in sparx5_port_disable()
443 sparx5, in sparx5_port_disable()
449 sparx5, in sparx5_port_disable()
450 DEV2G5_PCS1G_CFG(port->portno)); in sparx5_port_disable()
457 static int sparx5_port_fifo_sz(struct sparx5 *sparx5, in sparx5_port_fifo_sz() argument
460 u32 sys_clk = sparx5_clk_period(sparx5->coreclock); in sparx5_port_fifo_sz()
476 switch (speed) { in sparx5_port_fifo_sz()
516 static int sparx5_port_mux_set(struct sparx5 *sparx5, in sparx5_port_mux_set() argument
520 u32 portno = port->portno; in sparx5_port_mux_set()
523 if (port->conf.portmode == conf->portmode) in sparx5_port_mux_set()
526 switch (conf->portmode) { in sparx5_port_mux_set()
528 inst = (portno - portno % 4) / 4; in sparx5_port_mux_set()
531 sparx5, in sparx5_port_mux_set()
535 /* Affects d0-d3,d8-d11..d40-d43 */ in sparx5_port_mux_set()
542 sparx5, in sparx5_port_mux_set()
552 static int sparx5_port_max_tags_set(struct sparx5 *sparx5, in sparx5_port_max_tags_set() argument
555 enum sparx5_port_max_tags max_tags = port->max_vlan_tags; in sparx5_port_max_tags_set()
559 enum sparx5_vlan_port_type vlan_type = port->vlan_type; in sparx5_port_max_tags_set()
561 u32 dev = sparx5_to_high_dev(port->portno); in sparx5_port_max_tags_set()
562 u32 tinst = sparx5_port_dev_index(port->portno); in sparx5_port_max_tags_set()
563 void __iomem *inst = spx5_inst_get(sparx5, dev, tinst); in sparx5_port_max_tags_set()
567 port->custom_etype : in sparx5_port_max_tags_set()
575 sparx5, in sparx5_port_max_tags_set()
576 DEV2G5_MAC_TAGS_CFG(port->portno)); in sparx5_port_max_tags_set()
578 if (sparx5_port_is_2g5(port->portno)) in sparx5_port_max_tags_set()
600 int sparx5_port_fwd_urg(struct sparx5 *sparx5, u32 speed) in sparx5_port_fwd_urg() argument
605 switch (speed) { in sparx5_port_fwd_urg()
624 return urg / clk_period_ps - 1; in sparx5_port_fwd_urg()
635 static int sparx5_port_fc_setup(struct sparx5 *sparx5, in sparx5_port_fc_setup() argument
639 bool fc_obey = conf->pause & MLO_PAUSE_RX ? 1 : 0; in sparx5_port_fc_setup()
640 u32 pause_stop = 0xFFF - 1; /* FC gen disabled */ in sparx5_port_fc_setup()
642 if (conf->pause & MLO_PAUSE_TX) in sparx5_port_fc_setup()
647 spx5_rmw(DSM_MAC_CFG_HDX_BACKPREASSURE_SET(conf->duplex == DUPLEX_HALF), in sparx5_port_fc_setup()
649 sparx5, in sparx5_port_fc_setup()
650 DSM_MAC_CFG(port->portno)); in sparx5_port_fc_setup()
655 sparx5, in sparx5_port_fc_setup()
656 DSM_RX_PAUSE_CFG(port->portno)); in sparx5_port_fc_setup()
661 sparx5, in sparx5_port_fc_setup()
662 QSYS_FWD_PRESSURE(port->portno)); in sparx5_port_fc_setup()
667 sparx5, in sparx5_port_fc_setup()
668 QSYS_PAUSE_CFG(port->portno)); in sparx5_port_fc_setup()
675 if (conf->portmode == PHY_INTERFACE_MODE_1000BASEX) /* cl-37 aneg */ in sparx5_get_aneg_word()
676 return (conf->pause_adv | ADVERTISE_LPACK | ADVERTISE_1000XFULL); in sparx5_get_aneg_word()
681 int sparx5_serdes_set(struct sparx5 *sparx5, in sparx5_serdes_set() argument
685 int portmode, err, speed = conf->speed; in sparx5_serdes_set()
687 if (conf->portmode == PHY_INTERFACE_MODE_QSGMII && in sparx5_serdes_set()
688 ((port->portno % 4) != 0)) { in sparx5_serdes_set()
691 if (sparx5_is_baser(conf->portmode)) { in sparx5_serdes_set()
692 if (conf->portmode == PHY_INTERFACE_MODE_25GBASER) in sparx5_serdes_set()
694 else if (conf->portmode == PHY_INTERFACE_MODE_10GBASER) in sparx5_serdes_set()
700 err = phy_set_media(port->serdes, conf->media); in sparx5_serdes_set()
704 err = phy_set_speed(port->serdes, speed); in sparx5_serdes_set()
708 if (conf->serdes_reset) { in sparx5_serdes_set()
709 err = phy_reset(port->serdes); in sparx5_serdes_set()
715 * For BaseR, the serdes driver supports 10GGBASE-R and speed 5G/10G/25G in sparx5_serdes_set()
717 portmode = conf->portmode; in sparx5_serdes_set()
718 if (sparx5_is_baser(conf->portmode)) in sparx5_serdes_set()
720 err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET, portmode); in sparx5_serdes_set()
723 conf->serdes_reset = false; in sparx5_serdes_set()
727 static int sparx5_port_pcs_low_set(struct sparx5 *sparx5, in sparx5_port_pcs_low_set() argument
734 if (conf->inband) { in sparx5_port_pcs_low_set()
735 if (conf->portmode == PHY_INTERFACE_MODE_SGMII || in sparx5_port_pcs_low_set()
736 conf->portmode == PHY_INTERFACE_MODE_QSGMII) in sparx5_port_pcs_low_set()
737 inband_aneg = true; /* Cisco-SGMII in-band-aneg */ in sparx5_port_pcs_low_set()
738 else if (conf->portmode == PHY_INTERFACE_MODE_1000BASEX && in sparx5_port_pcs_low_set()
739 conf->autoneg) in sparx5_port_pcs_low_set()
740 inband_aneg = true; /* Clause-37 in-band-aneg */ in sparx5_port_pcs_low_set()
742 err = sparx5_serdes_set(sparx5, port, conf); in sparx5_port_pcs_low_set()
744 return -EINVAL; in sparx5_port_pcs_low_set()
752 sparx5, in sparx5_port_pcs_low_set()
753 DEV2G5_PCS1G_MODE_CFG(port->portno)); in sparx5_port_pcs_low_set()
757 sparx5, in sparx5_port_pcs_low_set()
758 DEV2G5_PCS1G_CFG(port->portno)); in sparx5_port_pcs_low_set()
763 /* Enable in-band aneg */ in sparx5_port_pcs_low_set()
768 sparx5, in sparx5_port_pcs_low_set()
769 DEV2G5_PCS1G_ANEG_CFG(port->portno)); in sparx5_port_pcs_low_set()
771 spx5_wr(0, sparx5, DEV2G5_PCS1G_ANEG_CFG(port->portno)); in sparx5_port_pcs_low_set()
781 sparx5, in sparx5_port_pcs_low_set()
782 DEV2G5_DEV_RST_CTRL(port->portno)); in sparx5_port_pcs_low_set()
787 static int sparx5_port_pcs_high_set(struct sparx5 *sparx5, in sparx5_port_pcs_high_set() argument
791 u32 clk_spd = conf->portmode == PHY_INTERFACE_MODE_5GBASER ? 1 : 0; in sparx5_port_pcs_high_set()
792 u32 pix = sparx5_port_dev_index(port->portno); in sparx5_port_pcs_high_set()
793 u32 dev = sparx5_to_high_dev(port->portno); in sparx5_port_pcs_high_set()
794 u32 pcs = sparx5_to_pcs_dev(port->portno); in sparx5_port_pcs_high_set()
799 devinst = spx5_inst_get(sparx5, dev, pix); in sparx5_port_pcs_high_set()
800 pcsinst = spx5_inst_get(sparx5, pcs, pix); in sparx5_port_pcs_high_set()
802 /* SFI : No in-band-aneg. Speeds 5G/10G/25G */ in sparx5_port_pcs_high_set()
803 err = sparx5_serdes_set(sparx5, port, conf); in sparx5_port_pcs_high_set()
805 return -EINVAL; in sparx5_port_pcs_high_set()
806 if (conf->portmode == PHY_INTERFACE_MODE_25GBASER) { in sparx5_port_pcs_high_set()
810 sparx5, in sparx5_port_pcs_high_set()
843 /* Switch between 1G/2500 and 5G/10G/25G devices */
844 static void sparx5_dev_switch(struct sparx5 *sparx5, int port, bool hsd) in sparx5_dev_switch() argument
851 sparx5, in sparx5_dev_switch()
856 sparx5, in sparx5_dev_switch()
861 sparx5, in sparx5_dev_switch()
867 static int sparx5_port_config_low_set(struct sparx5 *sparx5, in sparx5_port_config_low_set() argument
872 bool fdx = conf->duplex == DUPLEX_FULL; in sparx5_port_config_low_set()
873 int spd = conf->speed; in sparx5_port_config_low_set()
886 sparx5, in sparx5_port_config_low_set()
887 DEV2G5_MAC_MODE_CFG(port->portno)); in sparx5_port_config_low_set()
893 sparx5, in sparx5_port_config_low_set()
894 DEV2G5_MAC_IFG_CFG(port->portno)); in sparx5_port_config_low_set()
899 sparx5, in sparx5_port_config_low_set()
900 HSCH_PORT_MODE(port->portno)); in sparx5_port_config_low_set()
905 sparx5, in sparx5_port_config_low_set()
906 DEV2G5_MAC_ENA_CFG(port->portno)); in sparx5_port_config_low_set()
915 sparx5, in sparx5_port_config_low_set()
916 DEV2G5_DEV_RST_CTRL(port->portno)); in sparx5_port_config_low_set()
921 int sparx5_port_pcs_set(struct sparx5 *sparx5, in sparx5_port_pcs_set() argument
926 bool high_speed_dev = sparx5_is_baser(conf->portmode); in sparx5_port_pcs_set()
929 if (sparx5_dev_change(sparx5, port, conf)) { in sparx5_port_pcs_set()
930 /* switch device */ in sparx5_port_pcs_set()
931 sparx5_dev_switch(sparx5, port->portno, high_speed_dev); in sparx5_port_pcs_set()
933 /* Disable the not-in-use device */ in sparx5_port_pcs_set()
934 err = sparx5_port_disable(sparx5, port, !high_speed_dev); in sparx5_port_pcs_set()
938 /* Disable the port before re-configuring */ in sparx5_port_pcs_set()
939 err = sparx5_port_disable(sparx5, port, high_speed_dev); in sparx5_port_pcs_set()
941 return -EINVAL; in sparx5_port_pcs_set()
944 err = sparx5_port_pcs_high_set(sparx5, port, conf); in sparx5_port_pcs_set()
946 err = sparx5_port_pcs_low_set(sparx5, port, conf); in sparx5_port_pcs_set()
949 return -EINVAL; in sparx5_port_pcs_set()
951 if (conf->inband) { in sparx5_port_pcs_set()
955 sparx5, in sparx5_port_pcs_set()
956 ASM_PORT_CFG(port->portno)); in sparx5_port_pcs_set()
961 sparx5, in sparx5_port_pcs_set()
962 DSM_BUF_CFG(port->portno)); in sparx5_port_pcs_set()
965 port->conf = *conf; in sparx5_port_pcs_set()
970 int sparx5_port_config(struct sparx5 *sparx5, in sparx5_port_config() argument
974 bool high_speed_dev = sparx5_is_baser(conf->portmode); in sparx5_port_config()
977 err = sparx5_port_verify_speed(sparx5, port, conf); in sparx5_port_config()
983 sparx5_port_config_low_set(sparx5, port, conf); in sparx5_port_config()
986 err = sparx5_port_fc_setup(sparx5, port, conf); in sparx5_port_config()
991 stop_wm = sparx5_port_fifo_sz(sparx5, port->portno, conf->speed); in sparx5_port_config()
994 sparx5, in sparx5_port_config()
995 DSM_DEV_TX_STOP_WM_CFG(port->portno)); in sparx5_port_config()
998 urgency = sparx5_port_fwd_urg(sparx5, conf->speed); in sparx5_port_config()
1003 sparx5, in sparx5_port_config()
1004 QFWD_SWITCH_PORT_MODE(port->portno)); in sparx5_port_config()
1007 port->conf = *conf; in sparx5_port_config()
1013 int sparx5_port_init(struct sparx5 *sparx5, in sparx5_port_init() argument
1019 u32 devhigh = sparx5_to_high_dev(port->portno); in sparx5_port_init()
1020 u32 pix = sparx5_port_dev_index(port->portno); in sparx5_port_init()
1021 u32 pcs = sparx5_to_pcs_dev(port->portno); in sparx5_port_init()
1022 bool sd_pol = port->signd_active_high; in sparx5_port_init()
1023 bool sd_sel = !port->signd_internal; in sparx5_port_init()
1024 bool sd_ena = port->signd_enable; in sparx5_port_init()
1025 u32 pause_stop = 0xFFF - 1; /* FC generate disabled */ in sparx5_port_init()
1030 devinst = spx5_inst_get(sparx5, devhigh, pix); in sparx5_port_init()
1031 pcsinst = spx5_inst_get(sparx5, pcs, pix); in sparx5_port_init()
1034 err = sparx5_port_mux_set(sparx5, port, conf); in sparx5_port_init()
1039 err = sparx5_port_max_tags_set(sparx5, port); in sparx5_port_init()
1046 sparx5, in sparx5_port_init()
1047 DEV2G5_MAC_MAXLEN_CFG(port->portno)); in sparx5_port_init()
1053 sparx5, in sparx5_port_init()
1054 DEV2G5_PCS1G_SD_CFG(port->portno)); in sparx5_port_init()
1063 sparx5, in sparx5_port_init()
1064 QSYS_PAUSE_CFG(port->portno)); in sparx5_port_init()
1068 sparx5, in sparx5_port_init()
1069 QSYS_ATOP(port->portno)); in sparx5_port_init()
1071 /* Discard pause frame 01-80-C2-00-00-01 */ in sparx5_port_init()
1072 spx5_wr(PAUSE_DISCARD, sparx5, ANA_CL_CAPTURE_BPDU_CFG(port->portno)); in sparx5_port_init()
1077 sparx5, ANA_CL_FILTER_CTRL(port->portno)); in sparx5_port_init()
1079 if (conf->portmode == PHY_INTERFACE_MODE_QSGMII || in sparx5_port_init()
1080 conf->portmode == PHY_INTERFACE_MODE_SGMII) { in sparx5_port_init()
1081 err = sparx5_serdes_set(sparx5, port, conf); in sparx5_port_init()
1085 if (!sparx5_port_is_2g5(port->portno)) in sparx5_port_init()
1089 sparx5, in sparx5_port_init()
1090 DSM_DEV_TX_STOP_WM_CFG(port->portno)); in sparx5_port_init()
1092 sparx5_dev_switch(sparx5, port->portno, false); in sparx5_port_init()
1094 if (conf->portmode == PHY_INTERFACE_MODE_QSGMII) { in sparx5_port_init()
1098 sparx5, in sparx5_port_init()
1099 DEV2G5_DEV_RST_CTRL(port->portno)); in sparx5_port_init()
1105 sparx5, in sparx5_port_init()
1106 DEV2G5_MAC_IFG_CFG(port->portno)); in sparx5_port_init()
1108 if (sparx5_port_is_2g5(port->portno)) in sparx5_port_init()
1109 return 0; /* Low speed device only - return */ in sparx5_port_init()
1112 if (conf->portmode == PHY_INTERFACE_MODE_NA) in sparx5_port_init()
1113 conf->portmode = PHY_INTERFACE_MODE_10GBASER; in sparx5_port_init()
1115 if (sparx5_is_baser(conf->portmode)) in sparx5_port_init()
1116 sparx5_dev_switch(sparx5, port->portno, true); in sparx5_port_init()
1131 if (sparx5_port_is_25g(port->portno)) { in sparx5_port_init()
1136 sparx5, in sparx5_port_init()
1145 struct sparx5 *sparx5 = port->sparx5; in sparx5_port_enable() local
1150 sparx5, in sparx5_port_enable()
1151 QFWD_SWITCH_PORT_MODE(port->portno)); in sparx5_port_enable()
1157 sparx5_port_qos_dscp_set(port, &qos->dscp); in sparx5_port_qos_set()
1158 sparx5_port_qos_pcp_set(port, &qos->pcp); in sparx5_port_qos_set()
1159 sparx5_port_qos_pcp_rewr_set(port, &qos->pcp_rewr); in sparx5_port_qos_set()
1160 sparx5_port_qos_dscp_rewr_set(port, &qos->dscp_rewr); in sparx5_port_qos_set()
1170 struct sparx5 *sparx5 = port->sparx5; in sparx5_port_qos_pcp_rewr_set() local
1177 if (qos->enable) in sparx5_port_qos_pcp_rewr_set()
1183 port->sparx5, REW_TAG_CTRL(port->portno)); in sparx5_port_qos_pcp_rewr_set()
1185 for (i = 0; i < ARRAY_SIZE(qos->map.map); i++) { in sparx5_port_qos_pcp_rewr_set()
1187 pcp = qos->map.map[i]; in sparx5_port_qos_pcp_rewr_set()
1197 * 0:0nd - prio=0 and dp:0 => pcp=0 and dei=0 in sparx5_port_qos_pcp_rewr_set()
1198 * 0:0de - prio=0 and dp:1 => pcp=0 and dei=1 in sparx5_port_qos_pcp_rewr_set()
1202 REW_PCP_MAP_DE1_PCP_DE1, sparx5, in sparx5_port_qos_pcp_rewr_set()
1203 REW_PCP_MAP_DE1(port->portno, i)); in sparx5_port_qos_pcp_rewr_set()
1206 REW_DEI_MAP_DE1_DEI_DE1, port->sparx5, in sparx5_port_qos_pcp_rewr_set()
1207 REW_DEI_MAP_DE1(port->portno, i)); in sparx5_port_qos_pcp_rewr_set()
1210 REW_PCP_MAP_DE0_PCP_DE0, sparx5, in sparx5_port_qos_pcp_rewr_set()
1211 REW_PCP_MAP_DE0(port->portno, i)); in sparx5_port_qos_pcp_rewr_set()
1214 REW_DEI_MAP_DE0_DEI_DE0, port->sparx5, in sparx5_port_qos_pcp_rewr_set()
1215 REW_DEI_MAP_DE0(port->portno, i)); in sparx5_port_qos_pcp_rewr_set()
1225 struct sparx5 *sparx5 = port->sparx5; in sparx5_port_qos_pcp_set() local
1226 u8 *pcp_itr = qos->map.map; in sparx5_port_qos_pcp_set()
1231 spx5_rmw(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_SET(qos->qos_enable) | in sparx5_port_qos_pcp_set()
1232 ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_SET(qos->dp_enable), in sparx5_port_qos_pcp_set()
1234 sparx5, ANA_CL_QOS_CFG(port->portno)); in sparx5_port_qos_pcp_set()
1237 for (i = 0; i < ARRAY_SIZE(qos->map.map); i++) { in sparx5_port_qos_pcp_set()
1243 ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL, sparx5, in sparx5_port_qos_pcp_set()
1244 ANA_CL_PCP_DEI_MAP_CFG(port->portno, i)); in sparx5_port_qos_pcp_set()
1254 ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, port->sparx5, in sparx5_port_qos_dscp_rewr_mode_set()
1255 ANA_CL_QOS_CFG(port->portno)); in sparx5_port_qos_dscp_rewr_mode_set()
1261 struct sparx5 *sparx5 = port->sparx5; in sparx5_port_qos_dscp_rewr_set() local
1269 if (qos->enable) in sparx5_port_qos_dscp_rewr_set()
1273 REW_DSCP_MAP_DSCP_UPDATE_ENA, sparx5, in sparx5_port_qos_dscp_rewr_set()
1274 REW_DSCP_MAP(port->portno)); in sparx5_port_qos_dscp_rewr_set()
1279 for (i = 0; i < ARRAY_SIZE(qos->map.map); i++) { in sparx5_port_qos_dscp_rewr_set()
1280 dscp = qos->map.map[i]; in sparx5_port_qos_dscp_rewr_set()
1282 ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, sparx5, in sparx5_port_qos_dscp_rewr_set()
1292 struct sparx5 *sparx5 = port->sparx5; in sparx5_port_qos_dscp_set() local
1293 u8 *dscp = qos->map.map; in sparx5_port_qos_dscp_set()
1299 spx5_rmw(ANA_CL_QOS_CFG_DSCP_QOS_ENA_SET(qos->qos_enable) | in sparx5_port_qos_dscp_set()
1300 ANA_CL_QOS_CFG_DSCP_DP_ENA_SET(qos->dp_enable) | in sparx5_port_qos_dscp_set()
1303 ANA_CL_QOS_CFG_DSCP_KEEP_ENA, sparx5, in sparx5_port_qos_dscp_set()
1304 ANA_CL_QOS_CFG(port->portno)); in sparx5_port_qos_dscp_set()
1307 for (i = 0; i < ARRAY_SIZE(qos->map.map); i++) { in sparx5_port_qos_dscp_set()
1311 ANA_CL_DSCP_CFG_DSCP_DP_VAL, sparx5, in sparx5_port_qos_dscp_set()
1315 /* Set per-dscp trust */ in sparx5_port_qos_dscp_set()
1316 for (i = 0; i < ARRAY_SIZE(qos->map.map); i++) { in sparx5_port_qos_dscp_set()
1317 if (qos->qos_enable) { in sparx5_port_qos_dscp_set()
1319 ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, sparx5, in sparx5_port_qos_dscp_set()
1330 struct sparx5 *sparx5 = port->sparx5; in sparx5_port_qos_default_set() local
1333 spx5_rmw(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_SET(qos->default_prio) | in sparx5_port_qos_default_set()
1337 sparx5, ANA_CL_QOS_CFG(port->portno)); in sparx5_port_qos_default_set()
1344 sparx5, ANA_CL_VLAN_CTRL(port->portno)); in sparx5_port_qos_default_set()