Searched +full:shared +full:- +full:interrupt (Results 1 – 25 of 1031) sorted by relevance
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/linux-6.12.1/arch/mips/include/asm/ |
D | mips-gic.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h 29 /* For read-only shared registers */ 34 /* For read-write shared registers */ 39 /* For read-only local registers */ 44 /* For read-write local registers */ 49 /* For read-only shared per-interrupt registers */ 62 /* For read-write shared per-interrupt registers */ 81 /* For read-only local per-interrupt registers */ 88 /* For read-write local per-interrupt registers */ [all …]
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/linux-6.12.1/drivers/net/ipa/ |
D | ipa_uc.c | 1 // SPDX-License-Identifier: GPL-2.0 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2024 Linaro Ltd. 26 * The microcontroller can generate two interrupts to the AP. One interrupt 29 * addition, the AP can interrupt the microcontroller by writing a register. 33 * AP and the IPA microcontroller. Each side writes data to the shared area 35 * to the interrupt. Some information found in the shared area is currently 36 * unused. All remaining space in the shared area is reserved, and must not 45 * struct ipa_uc_mem_area - AP/microcontroller shared memory area 46 * @command: command code (AP->microcontroller) [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/ |
D | fsl,ls-msi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 This interrupt controller hardware is a second level interrupt controller that 11 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based 12 platforms. If interrupt-parent is not provided, the default parent interrupt 15 Each PCIe node needs to have property msi-parent that points to 19 - Frank Li <Frank.Li@nxp.com> 24 - fsl,ls1012a-msi [all …]
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D | st,spear3xx-shirq.txt | 1 * SPEAr Shared IRQ layer (shirq) 3 SPEAr3xx architecture includes shared/multiplexed irqs for certain set 4 of devices. The multiplexor provides a single interrupt to parent 5 interrupt controller (VIC) on behalf of a group of devices. 13 A single node in the device tree is used to describe the shared 14 interrupt multiplexor (one node for all groups). A group in the 15 interrupt controller shares config/control registers with other groups. 16 For example, a 32-bit interrupt enable/disable config register can 17 accommodate up to 4 interrupt groups. 20 - compatible: should be, either of [all …]
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D | marvell,icu.txt | 1 Marvell ICU Interrupt Controller 2 -------------------------------- 4 The Marvell ICU (Interrupt Consolidation Unit) controller is 5 responsible for collecting all wired-interrupt sources in the CP and 6 communicating them to the GIC in the AP, the unit translates interrupt 13 - compatible: Should be "marvell,cp110-icu" 15 - reg: Should contain ICU registers location and length. 17 Subnodes: Each group of interrupt is declared as a subnode of the ICU, 22 - compatible: Should be one of: 23 * "marvell,cp110-icu-nsr" [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/mailbox/ |
D | nvidia,tegra186-hsp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 The features that HSP supported are shared mailboxes, shared 29 For shared mailboxes, the first cell composed of two fields: 30 - bits 15..8: 31 A bit mask of flags that further specifies the type of shared [all …]
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D | arm,mhuv3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Sudeep Holla <sudeep.holla@arm.com> 11 - Cristian Marussi <cristian.marussi@arm.com> 27 - Configure the MHU 28 - Send Transfers to the Receiver 29 - Optionally receive acknowledgment of a Transfer from the Receiver 32 - Configure the MHU 33 - Receive Transfers from the Sender [all …]
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/linux-6.12.1/arch/arm/mach-omap2/ |
D | prcm-common.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 8 * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc. 9 * Copyright (C) 2007-2009 Nokia Corporation 30 /* Chip-specific module offsets */ 37 #define OMAP3430_IVA2_MOD -0x800 66 /* 24XX register bits shared between CM & PRM registers */ 68 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 108 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ 122 /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ 130 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/display/ti/ |
D | ti,j721e-dss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Jyri Sarha <jsarha@ti.com> 12 - Tomi Valkeinen <tomi.valkeinen@ti.com> 22 const: ti,j721e-dss 26 - description: common_m DSS Master common 27 - description: common_s0 DSS Shared common 0 28 - description: common_s1 DSS Shared common 1 [all …]
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/linux-6.12.1/drivers/net/ethernet/aquantia/atlantic/hw_atl2/ |
D | hw_atl2_llh.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 13 /* Set TX Interrupt Moderation Control Register */ 41 /* set tx random TC-queue mapping enable bit */ 72 /* get data from firmware shared input buffer */ 76 /* set data into firmware shared input buffer */ 80 /* get data from firmware shared output buffer */ 84 /* set host finished write shared buffer indication */ 87 /* get mcp finished read shared buffer indication */ 96 /* get host interrupt request */ 99 /* clear host interrupt request */
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/linux-6.12.1/drivers/tee/optee/ |
D | optee_smc.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ 3 * Copyright (c) 2015-2021, Linaro Limited 8 #include <linux/arm-smccc.h> 28 * Normal cached memory (write-back), shareable for SMP systems and not 36 * 32-bit registers. 44 * 384fb3e0-e7f8-11e3-af63-0002a5d5c51b. 75 * Used by non-secure world to figure out which Trusted OS is installed. 78 * Returns UUID in a0-4 in the same way as OPTEE_SMC_CALLS_UID 88 * Used by non-secure world to figure out which version of the Trusted OS 92 * Returns revision in a0-1 in the same way as OPTEE_SMC_CALLS_REVISION [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/soc/qcom/ |
D | qcom,smsm.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm Shared Memory State Machine 10 - Andy Gross <agross@kernel.org> 11 - Bjorn Andersson <bjorn.andersson@linaro.org> 12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 15 The Shared Memory State Machine facilitates broadcasting of single bit state 25 '#address-cells': 28 qcom,local-host: [all …]
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D | qcom,smp2p.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm Shared Memory Point 2 Point 10 - Andy Gross <agross@kernel.org> 11 - Bjorn Andersson <bjorn.andersson@linaro.org> 12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 15 The Shared Memory Point to Point (SMP2P) protocol facilitates communication 16 of a single 32-bit value between two processors. Each value has a single 35 $ref: /schemas/types.yaml#/definitions/phandle-array [all …]
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/linux-6.12.1/arch/arm/boot/dts/st/ |
D | stm32mp15xx-osd32.dtsi | 1 /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */ 3 * Copyright (C) 2020 STMicroelectronics - All Rights Reserved 7 #include "stm32mp15-pinctrl.dtsi" 9 #include <dt-bindings/mfd/st,stpmic1.h> 12 reserved-memory { 13 #address-cells = <1>; 14 #size-cells = <1>; 18 compatible = "shared-dma-pool"; 20 no-map; 24 compatible = "shared-dma-pool"; [all …]
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D | stm32mp157c-odyssey-som.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 6 /dts-v1/; 10 #include "stm32mp15-pinctrl.dtsi" 11 #include "stm32mp15xxac-pinctrl.dtsi" 12 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/leds/common.h> 14 #include <dt-bindings/mfd/st,stpmic1.h> 17 model = "Seeed Studio Odyssey-STM32MP157C SOM"; 18 compatible = "seeed,stm32mp157c-odyssey-som", "st,stm32mp157"; 25 reserved-memory { [all …]
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D | stm32mp15xx-dhcor-som.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 3 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved 8 #include "stm32mp15-pinctrl.dtsi" 9 #include "stm32mp15xxac-pinctrl.dtsi" 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/mfd/st,stpmic1.h> 23 reserved-memory { 24 #address-cells = <1>; 25 #size-cells = <1>; 29 compatible = "shared-dma-pool"; [all …]
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/linux-6.12.1/Documentation/power/ |
D | suspend-and-interrupts.rst | 10 ----------------------------------- 12 Device interrupt request lines (IRQs) are generally disabled during system 14 ->prepare, ->suspend and ->suspend_late callbacks have been executed for all 21 interrupt handlers for shared IRQs that device drivers implementing them were 29 Device IRQs are re-enabled during system resume, right before the "early" phase 30 of resuming devices (that is, before starting to execute ->resume_early 35 ------------------------ 38 suspend-resume cycle, including the "noirq" phases of suspending and resuming 41 but also to IPIs and to some other special-purpose interrupts. 44 requesting a special-purpose interrupt. It causes suspend_device_irqs() to [all …]
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/linux-6.12.1/arch/arm/mach-shmobile/ |
D | regulator-quirk-rcar-gen2.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * R-Car Generation 2 da9063(L)/da9210 regulator quirk 6 * regulators. All of these regulators have their interrupt request lines 7 * tied to the same interrupt pin (IRQ2) on the SoC. 9 * After cold boot or da9063-induced restart, both the da9063 and da9210 seem 10 * to assert their interrupt request lines. Hence as soon as one driver 11 * requests this irq, it gets stuck in an interrupt storm, as it only manages 12 * to deassert its own interrupt request line, and the other driver hasn't 13 * installed an interrupt handler yet. 46 bool shared; /* IRQ line is shared */ member [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/gpio/ |
D | sprd,gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Orson Zhai <orsonzhai@gmail.com> 12 - Baolin Wang <baolin.wang7@gmail.com> 13 - Chunyan Zhang <zhang.lyra@gmail.com> 16 The controller's registers are organized as sets of sixteen 16-bit 18 interrupt is shared for all of the banks handled by the controller. 23 - const: sprd,sc9860-gpio 24 - items: [all …]
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/linux-6.12.1/Documentation/virt/hyperv/ |
D | clocks.rst | 1 .. SPDX-License-Identifier: GPL-2.0 7 ----- 8 On arm64, Hyper-V virtualizes the ARMv8 architectural system counter 12 architectural system counter is functional in guest VMs on Hyper-V. 13 While Hyper-V also provides a synthetic system clock and four synthetic 14 per-CPU timers as described in the TLFS, they are not used by the 15 Linux kernel in a Hyper-V guest on arm64. However, older versions 16 of Hyper-V for arm64 only partially virtualize the ARMv8 19 Linux kernel versions on these older Hyper-V versions requires an 20 out-of-tree patch to use the Hyper-V synthetic clocks/timers instead. [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/soc/ti/ |
D | ti,pruss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 TI Programmable Real-Time Unit and Industrial Communication Subsystem 11 - Suman Anna <s-anna@ti.com> 15 The Programmable Real-Time Unit and Industrial Communication Subsystem 16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x, 17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC 18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and 20 communication, and an interrupt controller. [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/net/ |
D | cavium-mix.txt | 4 - compatible: "cavium,octeon-5750-mix" 9 - reg: The base addresses of four separate register banks. The first 11 AGL registers. The third bank are the AGL registers shared by all 12 MIX devices present. The fourth bank is the AGL_PRT_CTL shared by 15 - cell-index: A single cell specifying which portion of the shared 18 - interrupts: Two interrupt specifiers. The first is the MIX 19 interrupt routing and the second the routing for the AGL interrupts. 21 - phy-handle: Optional, see ethernet.txt file in the same directory. 25 compatible = "cavium,octeon-5750-mix"; 30 cell-index = <1>; [all …]
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/linux-6.12.1/drivers/irqchip/ |
D | spear-shirq.c | 2 * SPEAr platform shared irq layer source file 4 * Copyright (C) 2009-2012 ST Microelectronics 18 #include <linux/interrupt.h> 29 * struct spear_shirq: shared irq structure 32 * status_reg: Status register offset for chained interrupt handler 35 * virq_base: Base virtual interrupt number 37 * offset: Bit offset of the first interrupt 38 * irq_chip: Interrupt controller chip used for this instance, 52 /* spear300 shared irq registers offsets and masks */ 61 u32 val, shift = d->irq - shirq->virq_base + shirq->offset; in shirq_irq_mask() [all …]
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/linux-6.12.1/arch/mips/cavium-octeon/ |
D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0 11 non-CN63XXP1 hardware, so it is recommended to select "n" 51 bool "Lock the interrupt handler in L2" 55 Lock the low level interrupt handler into L2. 58 bool "Lock the 2nd level interrupt handler in L2" 62 Lock the 2nd level interrupt handler in L2. 72 int "Memory to reserve for user processes shared region (MB)" 76 Reserve a shared memory region for user processes to use for hardware 84 tristate "Module to measure interrupt latency using Octeon CIU Timer" 86 This driver is a module to measure interrupt latency using the [all …]
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/linux-6.12.1/drivers/soc/qcom/ |
D | smsm.c | 1 // SPDX-License-Identifier: GPL-2.0-only 4 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. 7 #include <linux/interrupt.h> 19 * This driver implements the Qualcomm Shared Memory State Machine, a mechanism 22 * The implementation is based on two sections of shared memory; the first 27 * read-write, while the rest should be considered read-only. 34 * The subscription matrix is laid out in entry-major order: 40 * A third, optional, shared memory region might contain information regarding 46 * Shared memory identifiers, used to acquire handles to respective memory 63 * struct qcom_smsm - smsm driver context [all …]
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