soc/qcom/qcom%2Csmsm.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Shared Memory State Machine
10   - Andy Gross <agross@kernel.org>
11   - Bjorn Andersson <bjorn.andersson@linaro.org>
12   - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15   The Shared Memory State Machine facilitates broadcasting of single bit state
25   '#address-cells':
28   qcom,local-host:
42       (0-indexed).
44   '#size-cells':
48   "^qcom,ipc-[1-4]$":
49     $ref: /schemas/types.yaml#/definitions/phandle-array
51       - items:
52           - description: phandle to a syscon node representing the APCS registers
53           - description: u32 representing offset to the register within the syscon
54           - description: u32 representing the ipc bit within the register
60   "@[0-9a-f]$":
64       node.  Nodes can either be flagged as an interrupt-controller to denote a
72       interrupt-controller:
74           Marks the entry as a interrupt-controller and the state bits to
77       '#interrupt-cells':
86       '#qcom,smem-state-cells':
93       - reg
96       - required:
97           - '#qcom,smem-state-cells'
98       - required:
99           - interrupt-controller
100           - '#interrupt-cells'
101           - interrupts
106   - compatible
107   - '#address-cells'
108   - '#size-cells'
111   - required:
112       - mboxes
113   - anyOf:
114       - required:
115           - qcom,ipc-1
116       - required:
117           - qcom,ipc-2
118       - required:
119           - qcom,ipc-3
120       - required:
121           - qcom,ipc-4
128   # point-of-view. It encompasses one outbound entry and the outgoing interrupt
130   - |
131     #include <dt-bindings/interrupt-controller/arm-gic.h>
133     shared-memory {
135         #address-cells = <1>;
136         #size-cells = <0>;
141             #qcom,smem-state-cells = <1>;
147             interrupt-controller;
148             #interrupt-cells = <2>;