Lines Matching +full:shared +full:- +full:interrupt
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jyri Sarha <jsarha@ti.com>
12 - Tomi Valkeinen <tomi.valkeinen@ti.com>
22 const: ti,j721e-dss
26 - description: common_m DSS Master common
27 - description: common_s0 DSS Shared common 0
28 - description: common_s1 DSS Shared common 1
29 - description: common_s2 DSS Shared common 2
30 - description: VIDL1 light video plane 1
31 - description: VIDL2 light video plane 2
32 - description: VID1 video plane 1
33 - description: VID1 video plane 2
34 - description: OVR1 overlay manager for vp1
35 - description: OVR2 overlay manager for vp2
36 - description: OVR3 overlay manager for vp3
37 - description: OVR4 overlay manager for vp4
38 - description: VP1 video port 1
39 - description: VP2 video port 2
40 - description: VP3 video port 3
41 - description: VP4 video port 4
42 - description: WB Write Back
44 reg-names:
46 - const: common_m
47 - const: common_s0
48 - const: common_s1
49 - const: common_s2
50 - const: vidl1
51 - const: vidl2
52 - const: vid1
53 - const: vid2
54 - const: ovr1
55 - const: ovr2
56 - const: ovr3
57 - const: ovr4
58 - const: vp1
59 - const: vp2
60 - const: vp3
61 - const: vp4
62 - const: wb
66 - description: fck DSS functional clock
67 - description: vp1 Video Port 1 pixel clock
68 - description: vp2 Video Port 2 pixel clock
69 - description: vp3 Video Port 3 pixel clock
70 - description: vp4 Video Port 4 pixel clock
72 clock-names:
74 - const: fck
75 - const: vp1
76 - const: vp2
77 - const: vp3
78 - const: vp4
80 assigned-clocks:
84 assigned-clock-parents:
90 - description: common_m DSS Master common
91 - description: common_s0 DSS Shared common 0
92 - description: common_s1 DSS Shared common 1
93 - description: common_s2 DSS Shared common 2
95 interrupt-names:
97 - const: common_m
98 - const: common_s0
99 - const: common_s1
100 - const: common_s2
102 power-domains:
106 dma-coherent:
133 max-memory-bandwidth:
140 - compatible
141 - reg
142 - reg-names
143 - clocks
144 - clock-names
145 - interrupts
146 - interrupt-names
147 - ports
152 - |
153 #include <dt-bindings/interrupt-controller/arm-gic.h>
154 #include <dt-bindings/interrupt-controller/irq.h>
155 #include <dt-bindings/soc/ti,sci_pm_domain.h>
158 compatible = "ti,j721e-dss";
176 reg-names = "common_m", "common_s0",
187 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
188 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
193 interrupt-names = "common_m",
198 #address-cells = <1>;
199 #size-cells = <0>;
204 remote-endpoint = <&dp_bridge_input>;