| /linux-6.12.1/Documentation/devicetree/bindings/net/ |
| D | nvidia,tegra234-mgbe.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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| /linux-6.12.1/drivers/net/ethernet/freescale/dpaa2/ |
| D | dpaa2-mac.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 #include <linux/pcs-lynx.h>
9 #include "dpaa2-eth.h"
10 #include "dpaa2-mac.h"
23 if (mac->ver_major == ver_major) in dpaa2_mac_cmp_ver()
24 return mac->ver_minor - ver_minor; in dpaa2_mac_cmp_ver()
25 return mac->ver_major - ver_major; in dpaa2_mac_cmp_ver()
30 mac->features = 0; in dpaa2_mac_detect_features()
34 mac->features |= DPAA2_MAC_FEATURE_PROTOCOL_CHANGE; in dpaa2_mac_detect_features()
61 return -EINVAL; in phy_mode()
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| /linux-6.12.1/include/uapi/linux/ |
| D | mdio.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
59 /* Media-dependent registers. */
60 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
61 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
62 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
63 * Lanes B-D are numbered 134-136. */
64 #define MDIO_PMA_10GBR_FSRT_CSR 147 /* 10GBASE-R fast retrain status and control */
65 #define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */
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| /linux-6.12.1/drivers/thunderbolt/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
14 Apple hardware or on PCs with Intel Falcon Ridge or newer.
16 To compile this driver a module, choose M here. The module will be
56 dongle that has TX/RX lines crossed, or by simply connecting a
60 To compile this driver a module, choose M here. The module will be
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| /linux-6.12.1/drivers/net/ethernet/freescale/fman/ |
| D | fman_memac.c | 1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
14 #include <linux/pcs-lynx.h>
24 #define CMD_CFG_REG_LOWP_RXETY 0x01000000 /* 07 Rx low power indication */
56 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */
57 #define IF_MODE_10G 0x00000000 /* 30-31 10G interface */
58 #define IF_MODE_MII 0x00000001 /* 30-31 MII interface */
59 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */
62 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */
63 #define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */
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| /linux-6.12.1/drivers/net/phy/ |
| D | microchip_t1.c | 1 // SPDX-License-Identifier: GPL-2.0
103 /* DSP 100M registers */
111 /* DSP 1000M registers */
122 /* PCS 1000M registers */
138 /* PCS 100M registers */
232 /* TEST_MODE_NORMAL: Non-hybrid results to calculate cable status(open/short/ok)
265 { "RX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG1, 14},
266 { "RX ERR Count detected by PCS", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG3, 16},
268 { "RX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG5, 8},
269 { "RX ERR Count for SGMII MII2GMII", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG6, 8},
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| /linux-6.12.1/drivers/net/ethernet/stmicro/stmmac/ |
| D | stmmac_ethtool.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
45 #define STMMAC_STAT(m) \ argument
46 { #m, sizeof_field(struct stmmac_extra_stats, m), \
47 offsetof(struct stmmac_priv, xstats.m)}
80 /* Tx/Rx IRQ error info */
90 /* Tx/Rx IRQ Events */
130 /* PCS */
168 /* statistics collected in queue which will be summed up for all TX or RX
169 * queues, or summed up for both TX and RX queues(napi_poll, normal_irq_n).
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| /linux-6.12.1/drivers/net/ethernet/sun/ |
| D | cassini.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
81 from RX FIFO to host mem.
82 RX completion reg updated.
86 RX Kick == RX complete */
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| /linux-6.12.1/drivers/net/ethernet/intel/igb/ |
| D | e1000_82575.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
61 * igb_write_vfta_i350 - Write value to VLAN filter table
71 struct igb_adapter *adapter = hw->back; in igb_write_vfta_i350()
74 for (i = 10; i--;) in igb_write_vfta_i350()
78 adapter->shadow_vfta[offset] = value; in igb_write_vfta_i350()
82 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
93 switch (hw->mac.type) { in igb_sgmii_uses_mdio_82575()
114 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
121 struct e1000_phy_info *phy = &hw->phy; in igb_check_for_link_media_swap()
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| D | e1000_defines.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
135 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
138 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
139 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
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| /linux-6.12.1/arch/arm64/boot/dts/nvidia/ |
| D | tegra234.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
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| /linux-6.12.1/drivers/phy/ti/ |
| D | phy-ti-pipe3.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
131 u16 m; member
180 unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */
216 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
242 /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
267 /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */
303 struct pipe3_dpll_map *dpll_map = phy->dpll_map; in ti_pipe3_get_dpll_params()
305 rate = clk_get_rate(phy->sys_clk); in ti_pipe3_get_dpll_params()
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| /linux-6.12.1/drivers/net/ethernet/chelsio/cxgb/ |
| D | vsc7326_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Straight off the data sheet, VMDS-10038 Rev 2.0 and
9 * PD0011-01-14-Meigs-II 2002-12-12
69 * fn = FIFO number, 0-9
84 * bn = bucket number 0-10 (yes, 11 buckets)
114 #define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 */
133 * tri-speed are only defined with the version that needs a port number.
140 /* 10GbE specific, and different from tri-speed */
144 #define REG_STICKY_RX CRA(0x1,0xa,0x06) /* RX debug register */
147 #define REG_MAX_RXHIGH CRA(0x1,0xa,0x0a) /* XGMII lane 0-3 debug */
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| /linux-6.12.1/drivers/net/ethernet/hisilicon/hns/ |
| D | hns_dsaf_gmac.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2014-2015 Hisilicon Limited.
65 /*enable GE rX/tX */ in hns_gmac_enable()
70 /* enable rx pcs */ in hns_gmac_enable()
80 /*disable GE rX/tX */ in hns_gmac_disable()
85 /* disable rx pcs */ in hns_gmac_disable()
91 /* hns_gmac_get_en - get port enable
93 * @rx:rx enable
96 static void hns_gmac_get_en(void *mac_drv, u32 *rx, u32 *tx) in hns_gmac_get_en() argument
103 *rx = dsaf_get_bit(porten, GMAC_PORT_RX_EN_B); in hns_gmac_get_en()
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| /linux-6.12.1/Documentation/networking/device_drivers/ethernet/cirrus/ |
| D | cs89x0.rst | 1 .. SPDX-License-Identifier: GPL-2.0
33 2.1 CS8900-based Adapter Configuration
34 2.2 CS8920-based Adapter Configuration
41 4.3 Compiling the driver to support Rx DMA
46 5.2.1 Diagnostic Self-Test
66 The CS8900-based ISA Ethernet Adapters from Cirrus Logic follow
67 IEEE 802.3 standards and support half or full-duplex operation in ISA bus
69 in 16-bit ISA or EISA bus expansion slots and are available in
70 10BaseT-only or 3-media configurations (10BaseT, 10Base2, and AUI for 10Base-5
73 CS8920-based adapters are similar to the CS8900-based adapter with additional
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| /linux-6.12.1/drivers/net/ethernet/meta/fbnic/ |
| D | fbnic_csr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
93 /* Rx Buffer Descriptor Format
110 (FBNIC_BD_DESC_ADDR_MASK & ~(FBNIC_BD_DESC_ADDR_MASK - 1))
124 /* Rx Completion Queue Descriptors */
137 #define FBNIC_RCD_AL_BUFF_FRAG_MASK (FBNIC_BD_FRAG_COUNT - 1)
296 /* Global QM Rx registers */
416 /* Rx Buffer Registers */
533 /* Rx Parser and Classifier Registers */
576 (FBNIC_RPC_RSS_KEY_DWORD_LEN - 1)
579 FBNIC_RPC_RSS_KEY_DWORD_LEN * 32 - \
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| /linux-6.12.1/drivers/net/dsa/ |
| D | mt7530.c | 1 // SPDX-License-Identifier: GPL-2.0-only
27 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) in pcs_to_mt753x_pcs() argument
29 return container_of(pcs, struct mt753x_pcs, pcs); in pcs_to_mt753x_pcs()
80 if (priv->bus) in mt7530_mutex_lock()
81 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_mutex_lock()
87 if (priv->bus) in mt7530_mutex_unlock()
88 mutex_unlock(&priv->bus->mdio_lock); in mt7530_mutex_unlock()
94 struct mii_bus *bus = priv->bus; in core_write()
100 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
106 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
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| /linux-6.12.1/drivers/net/ethernet/intel/e1000/ |
| D | e1000_hw.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
422 /* MAC decode size is 128K - This is the size of BAR0 */
443 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
486 * E1000_RAR_ENTRIES - 1 multicast addresses.
503 /* Receive Descriptor - Extended */
511 __le32 mrq; /* Multiple Rx Queues */
529 /* Receive Descriptor - Packet Split */
537 __le32 mrq; /* Multiple Rx Queues */
553 __le16 length[3]; /* length of buffers 1-3 */
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| /linux-6.12.1/drivers/scsi/bfa/ |
| D | bfa_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
4 * Copyright (c) 2014- QLogic Corporation.
8 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
34 BFA_MFG_TYPE_LIGHTNING_P0 = 902, /* Lightning mezz card - old */
72 #define bfa_mfg_increment_wwn_mac(m, i) \ argument
74 u32 t = ((u32)(m)[0] << 16) | ((u32)(m)[1] << 8) | \
75 (u32)(m)[2]; \
77 (m)[0] = (t >> 16) & 0xFF; \
78 (m)[1] = (t >> 8) & 0xFF; \
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| /linux-6.12.1/drivers/phy/samsung/ |
| D | phy-exynos5-usbdrd.c | 1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <linux/soc/samsung/exynos-regs-pmu.h>
194 /* Exynos9 - GS101 */
234 /* PCS registers */
300 #define PHY_TUNING_ENTRY_PHY(o, m, v) { \ argument
302 .mask = (m), \
307 #define PHY_TUNING_ENTRY_PCS(o, m, v) { \ argument
309 .mask = (m), \
314 #define PHY_TUNING_ENTRY_PMA(o, m, v) { \ argument
316 .mask = (m), \
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| /linux-6.12.1/drivers/net/dsa/realtek/ |
| D | rtl8365mb.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch.
4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk>
5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk>
7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4
9 * can be connected to the CPU - or another PHY - via either MII, RMII, or
15 * .-----------------------------------.
17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC |
18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC |
19 * UTP <---------------> Giga PHY <-> PCS <-> P2 GMAC |
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| /linux-6.12.1/drivers/net/ethernet/intel/ixgbe/ |
| D | ixgbe_type.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
81 #define IXGBE_CAT(r, m) IXGBE_##r##_##m argument
83 #define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, IDX)])
273 (0x012300 + (((_i) - 24) * 4)))
277 #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
278 #define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
280 #define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
281 #define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
290 #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
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| /linux-6.12.1/drivers/net/ethernet/sfc/ |
| D | mcdi_pcol.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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| /linux-6.12.1/drivers/gpu/drm/bridge/analogix/ |
| D | anx7625.c | 1 // SPDX-License-Identifier: GPL-2.0-only
35 #include <media/v4l2-fwnode.h>
36 #include <sound/hdmi-codec.h>
50 struct device *dev = &client->dev; in i2c_access_workaround()
53 if (client == ctx->last_client) in i2c_access_workaround()
56 ctx->last_client = client; in i2c_access_workaround()
58 if (client == ctx->i2c.tcpc_client) in i2c_access_workaround()
60 else if (client == ctx->i2c.tx_p0_client) in i2c_access_workaround()
62 else if (client == ctx->i2c.tx_p1_client) in i2c_access_workaround()
64 else if (client == ctx->i2c.rx_p0_client) in i2c_access_workaround()
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| /linux-6.12.1/drivers/net/ethernet/mscc/ |
| D | ocelot.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
30 /* Caller must hold &ocelot->mact_lock */
36 /* Caller must hold &ocelot->mact_lock */
48 /* Caller must hold &ocelot->mact_lock */
90 if (mc_ports & BIT(ocelot->num_phys_ports)) in __ocelot_mact_learn()
109 mutex_lock(&ocelot->mact_lock); in ocelot_mact_learn()
111 mutex_unlock(&ocelot->mact_lock); in ocelot_mact_learn()
122 mutex_lock(&ocelot->mact_lock); in ocelot_mact_forget()
133 mutex_unlock(&ocelot->mact_lock); in ocelot_mact_forget()
145 mutex_lock(&ocelot->mact_lock); in ocelot_mact_lookup()
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