Lines Matching +full:rx +full:- +full:pcs +full:- +full:m
1 // SPDX-License-Identifier: GPL-2.0-only
27 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) in pcs_to_mt753x_pcs() argument
29 return container_of(pcs, struct mt753x_pcs, pcs); in pcs_to_mt753x_pcs()
80 if (priv->bus) in mt7530_mutex_lock()
81 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_mutex_lock()
87 if (priv->bus) in mt7530_mutex_unlock()
88 mutex_unlock(&priv->bus->mdio_lock); in mt7530_mutex_unlock()
94 struct mii_bus *bus = priv->bus; in core_write()
100 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
106 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
112 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
118 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
122 dev_err(&bus->dev, "failed to write mmd register\n"); in core_write()
130 struct mii_bus *bus = priv->bus; in core_rmw()
137 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_rmw()
143 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_rmw()
149 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_rmw()
155 val = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_rmw()
160 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_rmw()
164 dev_err(&bus->dev, "failed to write mmd register\n"); in core_rmw()
186 ret = regmap_write(priv->regmap, reg, val); in mt7530_mii_write()
189 dev_err(priv->dev, in mt7530_mii_write()
201 ret = regmap_read(priv->regmap, reg, &val); in mt7530_mii_read()
204 dev_err(priv->dev, in mt7530_mii_read()
225 return mt7530_mii_read(p->priv, p->reg); in _mt7530_unlocked_read()
233 mt7530_mutex_lock(p->priv); in _mt7530_read()
235 val = mt7530_mii_read(p->priv, p->reg); in _mt7530_read()
237 mt7530_mutex_unlock(p->priv); in _mt7530_read()
257 regmap_update_bits(priv->regmap, reg, mask, set); in mt7530_rmw()
289 dev_err(priv->dev, "reset timeout\n"); in mt7530_fdb_cmd()
298 return -EINVAL; in mt7530_fdb_cmd()
316 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", in mt7530_fdb_read()
320 fdb->vid = (reg[1] >> CVID) & CVID_MASK; in mt7530_fdb_read()
321 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; in mt7530_fdb_read()
322 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; in mt7530_fdb_read()
323 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; in mt7530_fdb_read()
324 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; in mt7530_fdb_read()
325 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; in mt7530_fdb_read()
326 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; in mt7530_fdb_read()
327 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; in mt7530_fdb_read()
328 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; in mt7530_fdb_read()
329 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; in mt7530_fdb_read()
406 struct mt7530_priv *priv = ds->priv; in mt7530_setup_port6()
427 if (priv->id == ID_MT7621) { in mt7530_setup_port6()
527 /* Enable 325M clock for SGMII */ in mt7531_pll_setup()
547 struct mt7530_priv *priv = ds->priv; in mt7530_mib_reset()
555 return mdiobus_read_nested(priv->bus, port, regnum); in mt7530_phy_read_c22()
561 return mdiobus_write_nested(priv->bus, port, regnum, val); in mt7530_phy_write_c22()
567 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); in mt7530_phy_read_c45()
573 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); in mt7530_phy_write_c45()
591 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
602 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
613 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
639 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
650 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
661 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
685 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_read()
697 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_read()
723 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_write()
735 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_write()
748 struct mt7530_priv *priv = bus->priv; in mt753x_phy_read_c22()
750 return priv->info->phy_read_c22(priv, port, regnum); in mt753x_phy_read_c22()
756 struct mt7530_priv *priv = bus->priv; in mt753x_phy_read_c45()
758 return priv->info->phy_read_c45(priv, port, devad, regnum); in mt753x_phy_read_c45()
764 struct mt7530_priv *priv = bus->priv; in mt753x_phy_write_c22()
766 return priv->info->phy_write_c22(priv, port, regnum, val); in mt753x_phy_write_c22()
773 struct mt7530_priv *priv = bus->priv; in mt753x_phy_write_c45()
775 return priv->info->phy_write_c45(priv, port, devad, regnum, val); in mt753x_phy_write_c45()
795 struct mt7530_priv *priv = ds->priv; in mt7530_get_ethtool_stats()
802 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; in mt7530_get_ethtool_stats()
805 if (mib->size == 2) { in mt7530_get_ethtool_stats()
824 struct mt7530_priv *priv = ds->priv; in mt7530_set_ageing_time()
827 unsigned int error = -1; in mt7530_set_ageing_time()
833 return -ERANGE; in mt7530_set_ageing_time()
837 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; in mt7530_set_ageing_time()
840 unsigned int tmp_error = secs - in mt7530_set_ageing_time()
875 struct mt7530_priv *priv = ds->priv; in mt7530_setup_port5()
879 mutex_lock(&priv->reg_mutex); in mt7530_setup_port5()
885 switch (priv->p5_mode) { in mt7530_setup_port5()
886 /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ in mt7530_setup_port5()
891 /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ in mt7530_setup_port5()
897 /* GMAC5: P5 -> SoC MAC or external PHY */ in mt7530_setup_port5()
907 /* P5 RGMII RX Clock Control: delay setting for 1000M */ in mt7530_setup_port5()
911 if (!dsa_is_dsa_port(priv->ds, 5) && in mt7530_setup_port5()
927 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, in mt7530_setup_port5()
928 mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); in mt7530_setup_port5()
930 mutex_unlock(&priv->reg_mutex); in mt7530_setup_port5()
933 /* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL)
938 * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
949 * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
966 * Link Layer Discovery Protocol (LLDP), link-local frames. They are not
969 * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail:
971 * Each of the reserved MAC addresses specified in Table 8-1
972 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
973 * permanently configured in the FDB in C-VLAN components and ERs.
975 * Each of the reserved MAC addresses specified in Table 8-2
976 * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
977 * configured in the FDB in S-VLAN components.
979 * Each of the reserved MAC addresses specified in Table 8-3
980 * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in
987 * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
990 * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no
991 * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
992 * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
994 * that appear in Table 8-1, Table 8-2, and Table 8-3
995 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
999 * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
1000 * address that no conformant S-VLAN component, C-VLAN component, or MAC
1003 * appear in both Table 8-1 and Table 8-2 but not in Table 8-3
1004 * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by
1005 * any TPMRs but will propagate no further than the nearest S-VLAN component,
1006 * C-VLAN component, or MAC Bridge.
1008 * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address
1009 * that no conformant C-VLAN component, MAC Bridge can forward; however, it is
1010 * relayed by TPMR components and S-VLAN components. PDUs using this
1011 * destination address, or any of the other addresses that appear in Table 8-1
1012 * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]),
1013 * will be relayed by TPMR components and S-VLAN components but will propagate
1014 * no further than the nearest C-VLAN component or MAC Bridge.
1021 * For link-local frames, only CPU port should be designated as destination port
1026 * Therefore, on the switch with CPU port architecture, link-local frames must
1027 * be trapped to CPU port, and certain link-local frames received by a Port of a
1028 * Bridge comprising a TPMR component or an S-VLAN component must be excluded
1031 * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port
1037 * Therefore, a Bridge of this architecture can only comprise S-VLAN components,
1038 * C-VLAN components, or MAC Bridge components. Since there's no TPMR component,
1040 * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge
1043 * One option to trap link-local frames to CPU port is to add static FDB entries
1047 * Bridge component or a C-VLAN component, there would have to be 16 times 4096
1050 * link-local frames from being discarded when the spanning tree Port State of
1057 * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
1058 * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
1063 * link-local frames with specific destination addresses to CPU port by Bridge,
1066 * Therefore, regardless of the type of the Bridge component, link-local frames
1069 * 01-80-C2-00-00-[00,01,02,03,0E]
1071 * In a Bridge comprising a MAC Bridge component or a C-VLAN component:
1073 * Link-local frames with these destination addresses won't be trapped to CPU
1074 * port which won't conform to IEEE Std 802.1Q-2022:
1076 * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
1078 * In a Bridge comprising an S-VLAN component:
1080 * Link-local frames with these destination addresses will be trapped to CPU
1081 * port which won't conform to IEEE Std 802.1Q-2022:
1083 * 01-80-C2-00-00-00
1085 * Link-local frames with these destination addresses won't be trapped to CPU
1086 * port which won't conform to IEEE Std 802.1Q-2022:
1088 * 01-80-C2-00-00-[04,05,06,07,08,09,0A]
1090 * To trap link-local frames to CPU port as conformant as this switch
1091 * intellectual property can allow, link-local frames are made to be regarded as
1097 * has no PVID assigned on software, VLAN-untagged frames won't be allowed in.
1099 * have link-local frames bypass this function of the Forwarding Process.
1105 * VLAN-untagged. in mt753x_trap_frames()
1116 * them VLAN-untagged. in mt753x_trap_frames()
1127 * them VLAN-untagged. in mt753x_trap_frames()
1141 struct mt7530_priv *priv = ds->priv; in mt753x_cpu_port_enable()
1155 if (priv->id == ID_MT7531 || priv->id == ID_MT7988 || in mt753x_cpu_port_enable()
1156 priv->id == ID_EN7581) in mt753x_cpu_port_enable()
1163 PCR_MATRIX(dsa_user_ports(priv->ds))); in mt753x_cpu_port_enable()
1175 struct mt7530_priv *priv = ds->priv; in mt7530_port_enable()
1177 mutex_lock(&priv->reg_mutex); in mt7530_port_enable()
1184 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_enable()
1186 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); in mt7530_port_enable()
1188 priv->ports[port].enable = true; in mt7530_port_enable()
1190 priv->ports[port].pm); in mt7530_port_enable()
1192 mutex_unlock(&priv->reg_mutex); in mt7530_port_enable()
1194 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) in mt7530_port_enable()
1208 struct mt7530_priv *priv = ds->priv; in mt7530_port_disable()
1210 mutex_lock(&priv->reg_mutex); in mt7530_port_disable()
1215 priv->ports[port].enable = false; in mt7530_port_disable()
1219 mutex_unlock(&priv->reg_mutex); in mt7530_port_disable()
1221 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) in mt7530_port_disable()
1225 if (port == 5 && priv->p5_mode == GMAC5) in mt7530_port_disable()
1234 struct mt7530_priv *priv = ds->priv; in mt7530_port_change_mtu()
1240 * RX length register, only allowing CPU port here is enough. in mt7530_port_change_mtu()
1250 /* RX length also includes Ethernet header, MTK tag, and FCS length */ in mt7530_port_change_mtu()
1280 struct mt7530_priv *priv = ds->priv; in mt7530_stp_state_set()
1308 bool join) __must_hold(&priv->reg_mutex) in mt7530_update_port_member()
1310 struct dsa_port *dp = dsa_to_port(priv->ds, port), *other_dp; in mt7530_update_port_member()
1311 struct mt7530_port *p = &priv->ports[port], *other_p; in mt7530_update_port_member()
1312 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_update_port_member()
1313 u32 port_bitmap = BIT(cpu_dp->index); in mt7530_update_port_member()
1317 dsa_switch_for_each_user_port(other_dp, priv->ds) { in mt7530_update_port_member()
1318 other_port = other_dp->index; in mt7530_update_port_member()
1319 other_p = &priv->ports[other_port]; in mt7530_update_port_member()
1332 isolated = p->isolated && other_p->isolated; in mt7530_update_port_member()
1335 other_p->pm |= PCR_MATRIX(BIT(port)); in mt7530_update_port_member()
1338 other_p->pm &= ~PCR_MATRIX(BIT(port)); in mt7530_update_port_member()
1341 if (other_p->enable) in mt7530_update_port_member()
1343 PCR_MATRIX_MASK, other_p->pm); in mt7530_update_port_member()
1350 p->pm = PCR_MATRIX(port_bitmap); in mt7530_update_port_member()
1351 if (priv->ports[port].enable) in mt7530_update_port_member()
1352 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, p->pm); in mt7530_update_port_member()
1362 return -EINVAL; in mt7530_port_pre_bridge_flags()
1372 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_flags()
1394 priv->ports[port].isolated = !!(flags.val & BR_ISOLATED); in mt7530_port_bridge_flags()
1396 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_flags()
1398 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_flags()
1409 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_join()
1411 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_join()
1419 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_join()
1427 struct mt7530_priv *priv = ds->priv; in mt7530_port_set_vlan_unaware()
1431 /* This is called after .port_bridge_leave when leaving a VLAN-aware in mt7530_port_set_vlan_unaware()
1448 for (i = 0; i < priv->ds->num_ports; i++) { in mt7530_port_set_vlan_unaware()
1461 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_set_vlan_unaware()
1463 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), in mt7530_port_set_vlan_unaware()
1464 PCR_MATRIX(dsa_user_ports(priv->ds))); in mt7530_port_set_vlan_unaware()
1465 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG in mt7530_port_set_vlan_unaware()
1473 struct mt7530_priv *priv = ds->priv; in mt7530_port_set_vlan_aware()
1482 G0_PORT_VID(priv->ports[port].pvid)); in mt7530_port_set_vlan_aware()
1485 if (!priv->ports[port].pvid) in mt7530_port_set_vlan_aware()
1514 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_leave()
1516 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_leave()
1521 * back to the default as is at initial boot which is a VLAN-unaware in mt7530_port_bridge_leave()
1527 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_leave()
1535 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_add()
1539 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_add()
1540 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); in mt7530_port_fdb_add()
1542 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_add()
1552 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_del()
1556 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_del()
1557 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); in mt7530_port_fdb_del()
1559 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_del()
1568 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_dump()
1574 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_dump()
1590 } while (--cnt && in mt7530_port_fdb_dump()
1594 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_dump()
1604 struct mt7530_priv *priv = ds->priv; in mt7530_port_mdb_add()
1605 const u8 *addr = mdb->addr; in mt7530_port_mdb_add()
1606 u16 vid = mdb->vid; in mt7530_port_mdb_add()
1610 mutex_lock(&priv->reg_mutex); in mt7530_port_mdb_add()
1618 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); in mt7530_port_mdb_add()
1621 mutex_unlock(&priv->reg_mutex); in mt7530_port_mdb_add()
1631 struct mt7530_priv *priv = ds->priv; in mt7530_port_mdb_del()
1632 const u8 *addr = mdb->addr; in mt7530_port_mdb_del()
1633 u16 vid = mdb->vid; in mt7530_port_mdb_del()
1637 mutex_lock(&priv->reg_mutex); in mt7530_port_mdb_del()
1645 mt7530_fdb_write(priv, vid, port_mask, addr, -1, in mt7530_port_mdb_del()
1649 mutex_unlock(&priv->reg_mutex); in mt7530_port_mdb_del()
1668 dev_err(priv->dev, "poll timeout\n"); in mt7530_vlan_cmd()
1674 dev_err(priv->dev, "read VTCR invalid\n"); in mt7530_vlan_cmd()
1675 return -EINVAL; in mt7530_vlan_cmd()
1686 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_vlan_filtering()
1689 /* The port is being kept as VLAN-unaware port when bridge is in mt7530_port_vlan_filtering()
1692 * for becoming a VLAN-aware port. in mt7530_port_vlan_filtering()
1695 mt7530_port_set_vlan_aware(ds, cpu_dp->index); in mt7530_port_vlan_filtering()
1707 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); in mt7530_hw_vlan_add()
1711 new_members = entry->old_members | BIT(entry->port); in mt7530_hw_vlan_add()
1729 else if (entry->untagged) in mt7530_hw_vlan_add()
1734 ETAG_CTRL_P_MASK(entry->port), in mt7530_hw_vlan_add()
1735 ETAG_CTRL_P(entry->port, val)); in mt7530_hw_vlan_add()
1745 new_members = entry->old_members & ~BIT(entry->port); in mt7530_hw_vlan_del()
1749 dev_err(priv->dev, in mt7530_hw_vlan_del()
1776 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; in mt7530_hw_vlan_update()
1805 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; in mt7530_port_vlan_add()
1806 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; in mt7530_port_vlan_add()
1808 struct mt7530_priv *priv = ds->priv; in mt7530_port_vlan_add()
1810 mutex_lock(&priv->reg_mutex); in mt7530_port_vlan_add()
1813 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); in mt7530_port_vlan_add()
1816 priv->ports[port].pvid = vlan->vid; in mt7530_port_vlan_add()
1826 G0_PORT_VID(vlan->vid)); in mt7530_port_vlan_add()
1827 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { in mt7530_port_vlan_add()
1829 priv->ports[port].pvid = G0_PORT_VID_DEF; in mt7530_port_vlan_add()
1831 /* Only accept tagged frames if the port is VLAN-aware */ in mt7530_port_vlan_add()
1840 mutex_unlock(&priv->reg_mutex); in mt7530_port_vlan_add()
1850 struct mt7530_priv *priv = ds->priv; in mt7530_port_vlan_del()
1852 mutex_lock(&priv->reg_mutex); in mt7530_port_vlan_del()
1855 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, in mt7530_port_vlan_del()
1861 if (priv->ports[port].pvid == vlan->vid) { in mt7530_port_vlan_del()
1862 priv->ports[port].pvid = G0_PORT_VID_DEF; in mt7530_port_vlan_del()
1864 /* Only accept tagged frames if the port is VLAN-aware */ in mt7530_port_vlan_del()
1874 mutex_unlock(&priv->reg_mutex); in mt7530_port_vlan_del()
1883 struct mt7530_priv *priv = ds->priv; in mt753x_port_mirror_add()
1888 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) in mt753x_port_mirror_add()
1889 return -EEXIST; in mt753x_port_mirror_add()
1891 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); in mt753x_port_mirror_add()
1894 monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val); in mt753x_port_mirror_add()
1895 if (val & MT753X_MIRROR_EN(priv->id) && in mt753x_port_mirror_add()
1896 monitor_port != mirror->to_local_port) in mt753x_port_mirror_add()
1897 return -EEXIST; in mt753x_port_mirror_add()
1899 val |= MT753X_MIRROR_EN(priv->id); in mt753x_port_mirror_add()
1900 val &= ~MT753X_MIRROR_PORT_MASK(priv->id); in mt753x_port_mirror_add()
1901 val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port); in mt753x_port_mirror_add()
1902 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_add()
1907 priv->mirror_rx |= BIT(port); in mt753x_port_mirror_add()
1910 priv->mirror_tx |= BIT(port); in mt753x_port_mirror_add()
1920 struct mt7530_priv *priv = ds->priv; in mt753x_port_mirror_del()
1924 if (mirror->ingress) { in mt753x_port_mirror_del()
1926 priv->mirror_rx &= ~BIT(port); in mt753x_port_mirror_del()
1929 priv->mirror_tx &= ~BIT(port); in mt753x_port_mirror_del()
1933 if (!priv->mirror_rx && !priv->mirror_tx) { in mt753x_port_mirror_del()
1934 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); in mt753x_port_mirror_del()
1935 val &= ~MT753X_MIRROR_EN(priv->id); in mt753x_port_mirror_del()
1936 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_del()
2025 struct device *dev = priv->dev; in mt7530_setup_gpio()
2030 return -ENOMEM; in mt7530_setup_gpio()
2036 gc->label = "mt7530"; in mt7530_setup_gpio()
2037 gc->parent = dev; in mt7530_setup_gpio()
2038 gc->owner = THIS_MODULE; in mt7530_setup_gpio()
2039 gc->get_direction = mt7530_gpio_get_direction; in mt7530_setup_gpio()
2040 gc->direction_input = mt7530_gpio_direction_input; in mt7530_setup_gpio()
2041 gc->direction_output = mt7530_gpio_direction_output; in mt7530_setup_gpio()
2042 gc->get = mt7530_gpio_get; in mt7530_setup_gpio()
2043 gc->set = mt7530_gpio_set; in mt7530_setup_gpio()
2044 gc->base = -1; in mt7530_setup_gpio()
2045 gc->ngpio = 15; in mt7530_setup_gpio()
2046 gc->can_sleep = true; in mt7530_setup_gpio()
2069 irq = irq_find_mapping(priv->irq_domain, p); in mt7530_irq_thread_fn()
2083 priv->irq_enable &= ~BIT(d->hwirq); in mt7530_irq_mask()
2091 priv->irq_enable |= BIT(d->hwirq); in mt7530_irq_unmask()
2107 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); in mt7530_irq_bus_sync_unlock()
2123 irq_set_chip_data(irq, domain->host_data); in mt7530_irq_map()
2141 priv->irq_enable &= ~BIT(d->hwirq); in mt7988_irq_mask()
2142 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); in mt7988_irq_mask()
2150 priv->irq_enable |= BIT(d->hwirq); in mt7988_irq_unmask()
2151 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); in mt7988_irq_unmask()
2164 irq_set_chip_data(irq, domain->host_data); in mt7988_irq_map()
2180 struct dsa_switch *ds = priv->ds; in mt7530_setup_mdio_irq()
2184 if (BIT(p) & ds->phys_mii_mask) { in mt7530_setup_mdio_irq()
2187 irq = irq_create_mapping(priv->irq_domain, p); in mt7530_setup_mdio_irq()
2188 ds->user_mii_bus->irq[p] = irq; in mt7530_setup_mdio_irq()
2196 struct device *dev = priv->dev; in mt7530_setup_irq()
2197 struct device_node *np = dev->of_node; in mt7530_setup_irq()
2200 if (!of_property_read_bool(np, "interrupt-controller")) { in mt7530_setup_irq()
2205 priv->irq = of_irq_get(np, 0); in mt7530_setup_irq()
2206 if (priv->irq <= 0) { in mt7530_setup_irq()
2207 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); in mt7530_setup_irq()
2208 return priv->irq ? : -EINVAL; in mt7530_setup_irq()
2211 if (priv->id == ID_MT7988 || priv->id == ID_EN7581) in mt7530_setup_irq()
2212 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, in mt7530_setup_irq()
2216 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, in mt7530_setup_irq()
2220 if (!priv->irq_domain) { in mt7530_setup_irq()
2222 return -ENOMEM; in mt7530_setup_irq()
2226 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) in mt7530_setup_irq()
2229 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, in mt7530_setup_irq()
2232 irq_domain_remove(priv->irq_domain); in mt7530_setup_irq()
2246 if (BIT(p) & priv->ds->phys_mii_mask) { in mt7530_free_mdio_irq()
2249 irq = irq_find_mapping(priv->irq_domain, p); in mt7530_free_mdio_irq()
2258 free_irq(priv->irq, priv); in mt7530_free_irq_common()
2259 irq_domain_remove(priv->irq_domain); in mt7530_free_irq_common()
2265 struct device_node *mnp, *np = priv->dev->of_node; in mt7530_free_irq()
2278 struct device_node *mnp, *np = priv->dev->of_node; in mt7530_setup_mdio()
2279 struct dsa_switch *ds = priv->ds; in mt7530_setup_mdio()
2280 struct device *dev = priv->dev; in mt7530_setup_mdio()
2292 ret = -ENOMEM; in mt7530_setup_mdio()
2297 ds->user_mii_bus = bus; in mt7530_setup_mdio()
2299 bus->priv = priv; in mt7530_setup_mdio()
2300 bus->name = KBUILD_MODNAME "-mii"; in mt7530_setup_mdio()
2301 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); in mt7530_setup_mdio()
2302 bus->read = mt753x_phy_read_c22; in mt7530_setup_mdio()
2303 bus->write = mt753x_phy_write_c22; in mt7530_setup_mdio()
2304 bus->read_c45 = mt753x_phy_read_c45; in mt7530_setup_mdio()
2305 bus->write_c45 = mt753x_phy_write_c45; in mt7530_setup_mdio()
2306 bus->parent = dev; in mt7530_setup_mdio()
2307 bus->phy_mask = ~ds->phys_mii_mask; in mt7530_setup_mdio()
2309 if (priv->irq && !mnp) in mt7530_setup_mdio()
2315 if (priv->irq && !mnp) in mt7530_setup_mdio()
2327 struct mt7530_priv *priv = ds->priv; in mt7530_setup()
2342 dn = cpu_dp->conduit->dev.of_node->parent; in mt7530_setup()
2350 dev_err(ds->dev, "parent OF node of DSA conduit not found"); in mt7530_setup()
2351 return -EINVAL; in mt7530_setup()
2354 ds->assisted_learning_on_cpu_port = true; in mt7530_setup()
2355 ds->mtu_enforcement_ingress = true; in mt7530_setup()
2357 if (priv->id == ID_MT7530) { in mt7530_setup()
2358 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); in mt7530_setup()
2359 ret = regulator_enable(priv->core_pwr); in mt7530_setup()
2361 dev_err(priv->dev, in mt7530_setup()
2366 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); in mt7530_setup()
2367 ret = regulator_enable(priv->io_pwr); in mt7530_setup()
2369 dev_err(priv->dev, "Failed to enable io pwr: %d\n", in mt7530_setup()
2375 /* Reset whole chip through gpio pin or memory-mapped registers for in mt7530_setup()
2378 if (priv->mcm) { in mt7530_setup()
2379 reset_control_assert(priv->rstc); in mt7530_setup()
2381 reset_control_deassert(priv->rstc); in mt7530_setup()
2383 gpiod_set_value_cansleep(priv->reset, 0); in mt7530_setup()
2385 gpiod_set_value_cansleep(priv->reset, 1); in mt7530_setup()
2393 dev_err(priv->dev, "reset timeout\n"); in mt7530_setup()
2400 dev_err(priv->dev, "chip %x can't be supported\n", id); in mt7530_setup()
2401 return -ENODEV; in mt7530_setup()
2405 dev_err(priv->dev, in mt7530_setup()
2407 return -EINVAL; in mt7530_setup()
2438 for (i = 0; i < priv->ds->num_ports; i++) { in mt7530_setup()
2444 MT753X_FORCE_MODE(priv->id), in mt7530_setup()
2445 MT753X_FORCE_MODE(priv->id)); in mt7530_setup()
2471 /* Setup VLAN ID 0 for VLAN-unaware bridges */ in mt7530_setup()
2479 * Set priv->p5_mode to the appropriate value if PHY muxing is in mt7530_setup()
2484 "mediatek,eth-mac")) in mt7530_setup()
2491 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); in mt7530_setup()
2495 if (phy_node->parent == priv->dev->of_node->parent || in mt7530_setup()
2496 phy_node->parent->parent == priv->dev->of_node) { in mt7530_setup()
2498 if (ret && ret != -ENODEV) { in mt7530_setup()
2503 id = of_mdio_parse_addr(ds->dev, phy_node); in mt7530_setup()
2505 priv->p5_mode = MUX_PHY_P0; in mt7530_setup()
2507 priv->p5_mode = MUX_PHY_P4; in mt7530_setup()
2514 if (priv->p5_mode == MUX_PHY_P0 || in mt7530_setup()
2515 priv->p5_mode == MUX_PHY_P4) { in mt7530_setup()
2522 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { in mt7530_setup()
2540 struct mt7530_priv *priv = ds->priv; in mt7531_setup_common()
2552 for (i = 0; i < priv->ds->num_ports; i++) { in mt7531_setup_common()
2558 MT753X_FORCE_MODE(priv->id), in mt7531_setup_common()
2559 MT753X_FORCE_MODE(priv->id)); in mt7531_setup_common()
2599 struct mt7530_priv *priv = ds->priv; in mt7531_setup()
2604 /* Reset whole chip through gpio pin or memory-mapped registers for in mt7531_setup()
2607 if (priv->mcm) { in mt7531_setup()
2608 reset_control_assert(priv->rstc); in mt7531_setup()
2610 reset_control_deassert(priv->rstc); in mt7531_setup()
2612 gpiod_set_value_cansleep(priv->reset, 0); in mt7531_setup()
2614 gpiod_set_value_cansleep(priv->reset, 1); in mt7531_setup()
2622 dev_err(priv->dev, "reset timeout\n"); in mt7531_setup()
2630 dev_err(priv->dev, "chip %x can't be supported\n", id); in mt7531_setup()
2631 return -ENODEV; in mt7531_setup()
2638 priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); in mt7531_setup()
2641 for (i = 0; i < priv->ds->num_ports; i++) in mt7531_setup()
2647 if (!priv->p5_sgmii) { in mt7531_setup()
2650 /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on in mt7531_setup()
2651 * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO in mt7531_setup()
2663 /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since in mt7531_setup()
2669 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in mt7531_setup()
2674 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in mt7531_setup()
2678 for (i = MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr); in mt7531_setup()
2679 i < MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr) + MT7530_NUM_PHYS; in mt7531_setup()
2689 /* Setup VLAN ID 0 for VLAN-unaware bridges */ in mt7531_setup()
2694 ds->assisted_learning_on_cpu_port = true; in mt7531_setup()
2695 ds->mtu_enforcement_ingress = true; in mt7531_setup()
2703 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; in mt7530_mac_port_get_caps()
2709 config->supported_interfaces); in mt7530_mac_port_get_caps()
2714 phy_interface_set_rgmii(config->supported_interfaces); in mt7530_mac_port_get_caps()
2716 config->supported_interfaces); in mt7530_mac_port_get_caps()
2718 config->supported_interfaces); in mt7530_mac_port_get_caps()
2724 config->supported_interfaces); in mt7530_mac_port_get_caps()
2726 config->supported_interfaces); in mt7530_mac_port_get_caps()
2734 struct mt7530_priv *priv = ds->priv; in mt7531_mac_port_get_caps()
2736 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; in mt7531_mac_port_get_caps()
2742 config->supported_interfaces); in mt7531_mac_port_get_caps()
2749 if (!priv->p5_sgmii) { in mt7531_mac_port_get_caps()
2750 phy_interface_set_rgmii(config->supported_interfaces); in mt7531_mac_port_get_caps()
2758 config->supported_interfaces); in mt7531_mac_port_get_caps()
2760 config->supported_interfaces); in mt7531_mac_port_get_caps()
2762 config->supported_interfaces); in mt7531_mac_port_get_caps()
2764 config->mac_capabilities |= MAC_2500FD; in mt7531_mac_port_get_caps()
2776 config->supported_interfaces); in mt7988_mac_port_get_caps()
2778 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; in mt7988_mac_port_get_caps()
2784 config->supported_interfaces); in mt7988_mac_port_get_caps()
2786 config->mac_capabilities |= MAC_10000FD; in mt7988_mac_port_get_caps()
2798 config->supported_interfaces); in en7581_mac_port_get_caps()
2800 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; in en7581_mac_port_get_caps()
2806 config->supported_interfaces); in en7581_mac_port_get_caps()
2808 config->mac_capabilities |= MAC_10000FD; in en7581_mac_port_get_caps()
2817 struct mt7530_priv *priv = ds->priv; in mt7530_mac_config()
2820 mt7530_setup_port5(priv->ds, interface); in mt7530_mac_config()
2822 mt7530_setup_port6(priv->ds, interface); in mt7530_mac_config()
2869 struct mt7530_priv *priv = ds->priv; in mt7531_mac_config()
2875 phydev = dp->user->phydev; in mt7531_mac_config()
2885 struct mt7530_priv *priv = dp->ds->priv; in mt753x_phylink_mac_select_pcs()
2889 return &priv->pcs[dp->index].pcs; in mt753x_phylink_mac_select_pcs()
2893 return priv->ports[dp->index].sgmii_pcs; in mt753x_phylink_mac_select_pcs()
2904 struct dsa_switch *ds = dp->ds; in mt753x_phylink_mac_config()
2906 int port = dp->index; in mt753x_phylink_mac_config()
2908 priv = ds->priv; in mt753x_phylink_mac_config()
2910 if ((port == 5 || port == 6) && priv->info->mac_port_config) in mt753x_phylink_mac_config()
2911 priv->info->mac_port_config(ds, port, mode, state->interface); in mt753x_phylink_mac_config()
2923 struct mt7530_priv *priv = dp->ds->priv; in mt753x_phylink_mac_link_down()
2925 mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK); in mt753x_phylink_mac_link_down()
2936 struct mt7530_priv *priv = dp->ds->priv; in mt753x_phylink_mac_link_up()
2971 mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr); in mt753x_phylink_mac_link_up()
2977 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_get_caps()
2979 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE; in mt753x_phylink_get_caps()
2981 priv->info->mac_port_get_caps(ds, port, config); in mt753x_phylink_get_caps()
2984 static int mt753x_pcs_validate(struct phylink_pcs *pcs, in mt753x_pcs_validate() argument
2989 if (state->interface == PHY_INTERFACE_MODE_TRGMII || in mt753x_pcs_validate()
2990 phy_interface_mode_is_8023z(state->interface)) in mt753x_pcs_validate()
2996 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, in mt7530_pcs_get_state() argument
2999 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; in mt7530_pcs_get_state()
3000 int port = pcs_to_mt753x_pcs(pcs)->port; in mt7530_pcs_get_state()
3005 state->link = (pmsr & PMSR_LINK); in mt7530_pcs_get_state()
3006 state->an_complete = state->link; in mt7530_pcs_get_state()
3007 state->duplex = !!(pmsr & PMSR_DPX); in mt7530_pcs_get_state()
3011 state->speed = SPEED_10; in mt7530_pcs_get_state()
3014 state->speed = SPEED_100; in mt7530_pcs_get_state()
3017 state->speed = SPEED_1000; in mt7530_pcs_get_state()
3020 state->speed = SPEED_UNKNOWN; in mt7530_pcs_get_state()
3024 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); in mt7530_pcs_get_state()
3026 state->pause |= MLO_PAUSE_RX; in mt7530_pcs_get_state()
3028 state->pause |= MLO_PAUSE_TX; in mt7530_pcs_get_state()
3031 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, in mt753x_pcs_config() argument
3039 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) in mt7530_pcs_an_restart() argument
3053 struct mt7530_priv *priv = ds->priv; in mt753x_setup()
3054 int ret = priv->info->sw_setup(ds); in mt753x_setup()
3065 if (ret && priv->irq) in mt753x_setup()
3070 /* Initialise the PCS devices */ in mt753x_setup()
3071 for (i = 0; i < priv->ds->num_ports; i++) { in mt753x_setup()
3072 priv->pcs[i].pcs.ops = priv->info->pcs_ops; in mt753x_setup()
3073 priv->pcs[i].pcs.neg_mode = true; in mt753x_setup()
3074 priv->pcs[i].priv = priv; in mt753x_setup()
3075 priv->pcs[i].port = i; in mt753x_setup()
3078 if (priv->create_sgmii) { in mt753x_setup()
3079 ret = priv->create_sgmii(priv); in mt753x_setup()
3080 if (ret && priv->irq) in mt753x_setup()
3090 struct mt7530_priv *priv = ds->priv; in mt753x_get_mac_eee()
3093 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); in mt753x_get_mac_eee()
3094 e->tx_lpi_timer = LPI_THRESH_GET(eeecr); in mt753x_get_mac_eee()
3102 struct mt7530_priv *priv = ds->priv; in mt753x_set_mac_eee()
3105 if (e->tx_lpi_timer > 0xFFF) in mt753x_set_mac_eee()
3106 return -EINVAL; in mt753x_set_mac_eee()
3108 set = LPI_THRESH_SET(e->tx_lpi_timer); in mt753x_set_mac_eee()
3109 if (!e->tx_lpi_enabled) in mt753x_set_mac_eee()
3122 struct dsa_port *cpu_dp = conduit->dsa_ptr; in mt753x_conduit_state_change()
3123 struct mt7530_priv *priv = ds->priv; in mt753x_conduit_state_change()
3131 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) in mt753x_conduit_state_change()
3134 mask = BIT(cpu_dp->index); in mt753x_conduit_state_change()
3137 priv->active_cpu_ports |= mask; in mt753x_conduit_state_change()
3139 priv->active_cpu_ports &= ~mask; in mt753x_conduit_state_change()
3141 if (priv->active_cpu_ports) { in mt753x_conduit_state_change()
3143 MT7530_CPU_PORT(__ffs(priv->active_cpu_ports)); in mt753x_conduit_state_change()
3151 struct mt7530_priv *priv = ds->priv; in mt7988_setup()
3154 reset_control_assert(priv->rstc); in mt7988_setup()
3156 reset_control_deassert(priv->rstc); in mt7988_setup()
3266 struct device *dev = priv->dev; in mt7530_probe_common()
3268 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); in mt7530_probe_common()
3269 if (!priv->ds) in mt7530_probe_common()
3270 return -ENOMEM; in mt7530_probe_common()
3272 priv->ds->dev = dev; in mt7530_probe_common()
3273 priv->ds->num_ports = MT7530_NUM_PORTS; in mt7530_probe_common()
3278 priv->info = of_device_get_match_data(dev); in mt7530_probe_common()
3279 if (!priv->info) in mt7530_probe_common()
3280 return -EINVAL; in mt7530_probe_common()
3282 priv->id = priv->info->id; in mt7530_probe_common()
3283 priv->dev = dev; in mt7530_probe_common()
3284 priv->ds->priv = priv; in mt7530_probe_common()
3285 priv->ds->ops = &mt7530_switch_ops; in mt7530_probe_common()
3286 priv->ds->phylink_mac_ops = &mt753x_phylink_mac_ops; in mt7530_probe_common()
3287 mutex_init(&priv->reg_mutex); in mt7530_probe_common()
3297 if (priv->irq) in mt7530_remove_common()
3300 dsa_unregister_switch(priv->ds); in mt7530_remove_common()
3302 mutex_destroy(&priv->reg_mutex); in mt7530_remove_common()