intel/igb/e1000_defines.h

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
135 #define E1000_RCTL_RDMTS_HALF     0x00000000    /* rx desc min threshold size */
138 #define E1000_RCTL_SZ_512         0x00020000    /* rx buffer size 512 */
139 #define E1000_RCTL_SZ_256         0x00030000    /* rx buffer size 256 */
184 #define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
186 #define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
254 /* Constants used to intrepret the masked PCI-X bus speed. */
271 /* 1000/H is not supported, nor spec-compliant. */
309 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
313 #define E1000_DMACR_DMACTHR_MASK        0x00FF0000 /* DMA Coal Rx Threshold */
318 /* DMA Coalescing BMC-to-OS Watchdog Enable */
325 #define E1000_DMCRTRH_UTRESH_MASK       0x0007FFFF /* Rx Traffic Rate Thresh */
326 #define E1000_DMCRTRH_LRPRCW            0x80000000 /* Rx pkt rate curr window */
328 #define E1000_DMCCNT_CCOUNT_MASK        0x01FFFFFF /* DMA Coal Rx Current Cnt */
330 #define E1000_FCRTC_RTH_COAL_MASK       0x0003FFF0 /* FC Rx Thresh High val */
334 /* Timestamp in Rx buffer */
389 #define E1000_ICR_RXSEQ         0x00000008 /* rx sequence error */
390 #define E1000_ICR_RXDMT0        0x00000010 /* rx desc min. threshold (0) */
391 #define E1000_ICR_RXT0          0x00000080 /* rx timer intr (ring 0) */
401 #define E1000_EICR_RX_QUEUE0    0x00000001 /* Rx Queue 0 Interrupt */
402 #define E1000_EICR_RX_QUEUE1    0x00000002 /* Rx Queue 1 Interrupt */
403 #define E1000_EICR_RX_QUEUE2    0x00000004 /* Rx Queue 2 Interrupt */
404 #define E1000_EICR_RX_QUEUE3    0x00000008 /* Rx Queue 3 Interrupt */
433 #define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
434 #define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
435 #define E1000_IMS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
444 #define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
501 /* Loop limit on how long we wait for auto-negotiation to complete */
519 #define E1000_TSYNCRXCTL_VALID      0x00000001 /* rx timestamp valid */
520 #define E1000_TSYNCRXCTL_TYPE_MASK  0x0000000E /* rx type mask */
526 #define E1000_TSYNCRXCTL_ENABLED    0x00000010 /* enable rx timestampping */
642 /* mPHY PCS CLK Register */
643 #define E1000_MPHY_PCS_CLK_REG_OFFSET  0x0004 /* mPHY PCS CLK AFE CSR Offset */
679 /* 1000BASE-T Control Register */
687 /* 1000BASE-T Status Register */
700 #define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
701 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
832 /* NVM Commands - Microwire */
834 /* NVM Commands - SPI */
838 #define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
866 /* PCI/PCI-X/PCI-EX Config space */
871 #define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
904 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
908 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
909  * 0=Normal 10BASE-T Rx Threshold
911 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
918 /* 0 = <50M
919  * 1 = 50-80M
920  * 2 = 80-110M
921  * 3 = 110-140M
922  * 4 = >140M
934  * within 1ms in 1000BASE-T
948 /* Intel i347-AT4 Registers */
957 /* i347-AT4 Extended PHY Specific Control Register */
973 /* i347-AT4 PHY Cable Diagnostics Control */
1002 #define E1000_IPCNFG_EEE_100M_AN     0x00000004  /* EEE Enable 100M AN */
1004 #define E1000_EEER_RX_LPI_EN         0x00020000  /* EEE Rx LPI Enable */
1036 /* Tx Rate-Scheduler Config fields */
1053 /* Fetch Time Delta - bits 31:16