chelsio/cxgb/vsc7326_reg.h

1 /* SPDX-License-Identifier: GPL-2.0 */
8  * Straight off the data sheet, VMDS-10038 Rev 2.0 and
9  * PD0011-01-14-Meigs-II 2002-12-12
69  *   fn = FIFO number, 0-9
84  *   bn = bucket number 0-10 (yes, 11 buckets)
114 #define REG_SPI4_DBG_CNT(n)	CRA(0x5,0x0,0x10+n)	/* Debug counters 0-9 */
133  * tri-speed are only defined with the version that needs a port number.
140 /* 10GbE specific, and different from tri-speed */
144 #define REG_STICKY_RX		CRA(0x1,0xa,0x06)	/* RX debug register */
147 #define REG_MAX_RXHIGH		CRA(0x1,0xa,0x0a)	/* XGMII lane 0-3 debug */
148 #define REG_MAX_RXLOW		CRA(0x1,0xa,0x0b)	/* XGMII lane 4-7 debug */
165 /* pn = port number 0-9 for tri-speed, 10 for 10GbE */
166 /* Both tri-speed and 10GbE */
171 /* tri-speed only
172  * pn = port number, 0-9
178 #define REG_PCS_STATUS_DBG(pn)	CRA(0x1,pn,0x07)	/* PCS status debug */
179 #define REG_PCS_CTRL(pn)	CRA(0x1,pn,0x08)	/* PCS control */
193 #define REG_HDX(pn)		CRA(0x1,pn,0x19)	/* Half-duplex config */
198 /* pn = port number, 0-a, a = 10GbE */
201 	RxInBytes		= 0x00,	// # Rx in octets
219 	RxSize65To127		= 0x12,	// # frames 65-127 octets
220 	RxSize128To255		= 0x13,	// # frames 128-255
221 	RxSize256To511		= 0x14,	// # frames 256-511
222 	RxSize512To1023		= 0x15,	// # frames 512-1023
223 	RxSize1024To1518	= 0x16,	// # frames 1024-1518
224 	RxSize1519ToMax		= 0x17,	// # frames 1519-max
239 	TxSize65To127		= 0x25,	// # frames 65-127 octets
240 	TxSize128To255		= 0x26,	// # frames 128-255
241 	TxSize256To511		= 0x27,	// # frames 256-511
242 	TxSize512To1023		= 0x28,	// # frames 512-1023
243 	TxSize1024To1518	= 0x29,	// # frames 1024-1518
244 	TxSize1519ToMax		= 0x2a,	// # frames 1519-max
264 	StatSticky1G		= 0x3e,	// tri-speed sticky bits
275 /* MII-Management Block registers */
276 /* These are for MII-M interface 0, which is the bidirectional LVTTL one.  If
278  * change to 0x1.  And the current errata states that MII-M 1 doesn't work.
281 #define REG_MIIM_STATUS		CRA(0x3,0x0,0x00)	/* MII-M Status */
282 #define REG_MIIM_CMD		CRA(0x3,0x0,0x01)	/* MII-M Command */
283 #define REG_MIIM_DATA		CRA(0x3,0x0,0x02)	/* MII-M Data */
284 #define REG_MIIM_PRESCALE	CRA(0x3,0x0,0x03)	/* MII-M MDC Prescale */