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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 segments of memory for buffering TX and RX, as well as the capability of
14 offloading TX/RX checksum calculation off the processor.
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
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/linux-6.12.1/drivers/net/pcs/
Dpcs-xpcs-nxp.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/pcs/pcs-xpcs.h>
5 #include "pcs-xpcs.h"
67 /* In NXP SJA1105, the PCS is integrated with a PMA that has the TX lane
69 * normal non-inverted behavior, the TX lane polarity must be inverted in the
70 * PCS, via the DIGITAL_CONTROL_2 register.
117 /* Enable input and output resistor terminations for low BER. */ in nxp_sja1110_pma_config()
126 /* Select PCS as transmitter data source. */ in nxp_sja1110_pma_config()
131 /* Program RX PLL feedback divider and reference divider for correct in nxp_sja1110_pma_config()
146 * when an input signal is not present. in nxp_sja1110_pma_config()
[all …]
Dpcs-rzn1-miic.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/pcs-rzn1-miic.h>
17 #include <dt-bindings/net/pcs-rzn1-miic.h>
52 #define MIIC_MODCTRL_CONF_NONE -1
55 * struct modctrl_match - Matching table entry for convctrl configuration
59 * then index 1 - 5 are CONV1 - CONV5.
122 * struct miic - MII converter structure
125 * @lock: Lock used for read-modify-write access
134 * struct miic_port - Per port MII converter struct
136 * @pcs: PCS structure associated to the port
[all …]
/linux-6.12.1/drivers/net/ethernet/sun/
Dsungem.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */
31 #define GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */
34 #define GREG_CFG_ENBUG2FIX 0x00001000 /* Fix Rx hang after overflow */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
48 #define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */
49 #define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */
50 #define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */
51 #define GREG_STAT_PCS 0x00002000 /* PCS signalled interrupt */
53 #define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */
[all …]
Dcassini.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
81 from RX FIFO to host mem.
82 RX completion reg updated.
86 RX Kick == RX complete */
[all …]
Dcassini.c1 // SPDX-License-Identifier: GPL-2.0+
13 * load balancing (non-VLAN mode)
16 * page-based RX descriptor engine with separate completion rings
17 * Gigabit support (GMII and PCS interface)
20 * RX is handled by page sized buffers that are attached as fragments to
22 * -- driver allocates pages at a time and keeps reference counts
24 * -- the upper protocol layers assume that the header is in the skb
27 * -- driver appends the rest of the data pages as frags to skbuffs
29 * -- on page reclamation, the driver swaps the page with a spare page.
37 * TX has 4 queues. currently these queues are used in a round-robin
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dfsl-ls1088a-ten64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
28 stdout-path = "serial0:115200n8";
32 compatible = "gpio-keys";
[all …]
/linux-6.12.1/include/dt-bindings/clock/
Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
58 /** @brief clock recovered from EAVB input */
126 /** @brief clock recovered from I2S1 input */
130 /** @brief clock recovered from I2S2 input */
134 /** @brief clock recovered from I2S3 input */
138 /** @brief clock recovered from I2S4 input */
142 /** @brief clock recovered from I2S5 input */
146 /** @brief clock recovered from I2S6 input */
192 /** @brief input from Tegra's XTAL_IN */
[all …]
/linux-6.12.1/drivers/net/ethernet/intel/ice/
Dice_ptp_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
67 * struct ice_phy_reg_info_eth56g - ETH56G PHY register parameters
106 * @rx_fixed_delay: Fixed Rx latency measured in 1/100th nanoseconds
109 * and Rx timestamps. This includes frequency values used to compute TUs per
110 * PAR/PCS clock cycle, and static delay values measured during hardware
115 * different link speeds, either the deskew marker for multi-lane link speeds
116 * or the Reed Solomon gearbox marker for RS-FEC.
136 * struct ice_eth56g_mac_reg_cfg - MAC config values for specific PTP registers
140 * @rx_mode: Rx timestamp compensation mode
141 * @rx_mk_dly: Rx timestamp marker start strobe delay
[all …]
Dice_ptp_hw.c1 // SPDX-License-Identifier: GPL-2.0
25 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
27 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
29 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
30 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
35 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
40 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
42 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
44 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
45 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
26 space, Port Logic Registers (PL), Shadow Config-space Registers,
[all …]
/linux-6.12.1/drivers/ata/
Dahci.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * ahci.h - Common AHCI SATA definitions and declarations
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
80 HOST_RESET = BIT(0), /* reset controller; self-clear */
92 HOST_CAP_FBS = BIT(16), /* FIS-based switching support */
98 HOST_CAP_SSS = BIT(27), /* Staggered Spin-up */
102 HOST_CAP_64 = BIT(31), /* PCI DAC (64-bit DMA) support */
115 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
[all …]
/linux-6.12.1/arch/arm64/boot/dts/nvidia/
Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
[all …]
/linux-6.12.1/drivers/phy/mediatek/
Dphy-mtk-xfi-tphy.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MediaTek 10GE SerDes XFI T-PHY driver
6 * Bc-bocun Chen <bc-bocun.chen@mediatek.com>
7 * based on mtk_usxgmii.c and mtk_sgmii.c found in MediaTek's SDK (GPL-2.0)
22 #include "phy-mtk-io.h"
60 * struct mtk_xfi_tphy - run-time data of the XFI phy instance
65 * @da_war: Enables work-around for 10GBase-R mode.
76 * mtk_xfi_tphy_setup() - Setup phy for specified interface mode.
86 * sequence of 32-bit writes, here we try to only modify the actually required
89 …s/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/b72d6cba92bf9e29fb035c03052fa1e86664a25b/21.02/files/t…
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/linux-6.12.1/drivers/phy/qualcomm/
Dphy-qcom-qmp-combo.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
24 #include <drm/bridge/aux-bridge.h>
26 #include <dt-bindings/phy/phy-qcom-qmp.h>
28 #include "phy-qcom-qmp-common.h"
30 #include "phy-qcom-qmp.h"
31 #include "phy-qcom-qmp-pcs-misc-v3.h"
32 #include "phy-qcom-qmp-pcs-usb-v4.h"
33 #include "phy-qcom-qmp-pcs-usb-v5.h"
34 #include "phy-qcom-qmp-pcs-usb-v6.h"
[all …]
/linux-6.12.1/drivers/net/ethernet/amd/xgbe/
Dxgbe-dev.c9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
125 #include "xgbe-common.h"
129 return pdata->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; in xgbe_get_max_frame()
138 DBGPR("-->xgbe_usec_to_riwt\n"); in xgbe_usec_to_riwt()
140 rate = pdata->sysclk_rate; in xgbe_usec_to_riwt()
143 * Convert the input usec value to the watchdog timer value. Each in xgbe_usec_to_riwt()
150 DBGPR("<--xgbe_usec_to_riwt\n"); in xgbe_usec_to_riwt()
161 DBGPR("-->xgbe_riwt_to_usec\n"); in xgbe_riwt_to_usec()
163 rate = pdata->sysclk_rate; in xgbe_riwt_to_usec()
[all …]
/linux-6.12.1/drivers/net/ethernet/chelsio/cxgb/
Dvsc7326_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Straight off the data sheet, VMDS-10038 Rev 2.0 and
9 * PD0011-01-14-Meigs-II 2002-12-12
69 * fn = FIFO number, 0-9
78 #define REG_DEBUG_BUF_CNT(ie,fn) CRA(0x2,ie&1,0x70+fn) /* Input Side Debug Counter */
79 #define REG_BUCKI(fn) CRA(0x2,2,0x20+fn) /* Input Side Debug Counter */
80 #define REG_BUCKE(fn) CRA(0x2,3,0x20+fn) /* Input Side Debug Counter */
84 * bn = bucket number 0-10 (yes, 11 buckets)
114 #define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 */
133 * tri-speed are only defined with the version that needs a port number.
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/linux-6.12.1/drivers/net/ethernet/stmicro/stmmac/
Dstmmac_main.c1 // SPDX-License-Identifier: GPL-2.0-only
3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
6 Copyright(C) 2007-2011 STMicroelectronics Ltd
29 #include <linux/dma-mapping.h>
55 * with fine resolution and binary rollover. This avoid non-monotonic behavior
62 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
70 static int debug = -1;
72 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
74 static int phyaddr = -1;
78 #define STMMAC_TX_THRESH(x) ((x)->dma_conf.dma_tx_size / 4)
[all …]
/linux-6.12.1/drivers/net/ethernet/intel/e1000/
De1000_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
422 /* MAC decode size is 128K - This is the size of BAR0 */
443 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
486 * E1000_RAR_ENTRIES - 1 multicast addresses.
503 /* Receive Descriptor - Extended */
511 __le32 mrq; /* Multiple Rx Queues */
529 /* Receive Descriptor - Packet Split */
537 __le32 mrq; /* Multiple Rx Queues */
553 __le16 length[3]; /* length of buffers 1-3 */
[all …]
/linux-6.12.1/include/linux/
Dethtool.h1 /* SPDX-License-Identifier: GPL-2.0 */
45 * enum ethtool_phys_id_state - indicator state for physical identification
61 ETH_RSS_HASH_TOP_BIT, /* Configurable RSS hash function - Toeplitz */
62 ETH_RSS_HASH_XOR_BIT, /* Configurable RSS hash function - Xor */
63 ETH_RSS_HASH_CRC32_BIT, /* Configurable RSS hash function - Crc32 */
73 * struct kernel_ethtool_ringparam - RX/TX ring configuration
74 * @rx_buf_len: Current length of buffers on the rx ring.
77 * @rx_push: The flag of rx push mode
78 * @cqe_size: Size of TX/RX completion queue event
93 * enum ethtool_supported_ring_param - indicator caps for setting ring params
[all …]
/linux-6.12.1/drivers/net/ethernet/mediatek/
Dmtk_eth_soc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
12 #include <linux/dma-mapping.h>
57 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
62 #define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD)
136 /* Unicast Filter MAC Address Register - Low */
140 /* Unicast Filter MAC Address Register - High */
156 /* PSE Input Queue Reservation Register*/
[all …]
/linux-6.12.1/drivers/net/ethernet/intel/igb/
Digb_ethtool.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
104 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
106 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
130 "legacy-rx",
139 struct e1000_hw *hw = &adapter->hw; in igb_get_link_ksettings()
140 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in igb_get_link_ksettings()
141 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; in igb_get_link_ksettings()
146 status = pm_runtime_suspended(&adapter->pdev->dev) ? in igb_get_link_ksettings()
148 if (hw->phy.media_type == e1000_media_type_copper) { in igb_get_link_ksettings()
[all …]
/linux-6.12.1/drivers/net/hamradio/
Dyam.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * yam.c -- YAM radio modem driver.
61 /* --------------------------------------------------------------------- */
67 /* --------------------------------------------------------------------- */
94 #define DEFAULT_PERS 64 /* 0->255 */
127 /* Rx section */
147 /* --------------------------------------------------------------------- */
175 #define IER_RX 1 /* enable rx interrupt */
184 #define MCR_OUT2 0x08 /* Master Interrupt enable (must be set on PCs) */
188 #define MSR_DCTS 0x01 /* Delta CTS input */
[all …]
/linux-6.12.1/drivers/net/dsa/sja1105/
Dsja1105_main.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
18 #include <linux/pcs/pcs-xpcs.h>
77 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries; in sja1105_is_vlan_configured()
78 count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count; in sja1105_is_vlan_configured()
85 return -1; in sja1105_is_vlan_configured()
90 struct sja1105_private *priv = ds->priv; in sja1105_drop_untagged()
93 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; in sja1105_drop_untagged()
108 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; in sja1105_pvid_apply()
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