drivers/ata/ahci.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  *  ahci.h - Common AHCI SATA definitions and declarations
6  *    		    Please ALWAYS copy linux-ide@vger.kernel.org
9  *  Copyright 2004-2005 Red Hat, Inc.
12  * as Documentation/driver-api/libata.rst
80 	HOST_RESET		= BIT(0),  /* reset controller; self-clear */
92 	HOST_CAP_FBS		= BIT(16), /* FIS-based switching support */
98 	HOST_CAP_SSS		= BIT(27), /* Staggered Spin-up */
102 	HOST_CAP_64		= BIT(31), /* PCI DAC (64-bit DMA) support */
115 	PORT_FIS_ADDR		= 0x08, /* FIS rx buf addr */
116 	PORT_FIS_ADDR_HI	= 0x0c, /* FIS rx buf addr hi */
128 	PORT_FBS		= 0x40, /* FIS-based Switching */
137 	PORT_IRQ_IF_NONFATAL	= BIT(26), /* interface non-fatal error */
145 	PORT_IRQ_UNK_FIS	= BIT(4),  /* unknown FIS rx'd */
146 	PORT_IRQ_SDB_FIS	= BIT(3),  /* Set Device Bits FIS rx'd */
147 	PORT_IRQ_DMAS_FIS	= BIT(2),  /* DMA Setup FIS rx'd */
148 	PORT_IRQ_PIOS_FIS	= BIT(1),  /* PIO Setup FIS rx'd */
149 	PORT_IRQ_D2H_REG_FIS	= BIT(0),  /* D2H Register FIS rx'd */
209 	/* hpriv->flags bits */
230 						      error-handling stage) */
235 	AHCI_HFLAG_MULTI_MSI		= BIT(20), /* per-port MSI(-X) */
248 	AHCI_HFLAG_INTEL_PCS_QUIRK	= BIT(28), /* apply Intel PCS quirk */
250 	/* ap->flags bits */
256 	PCS_6				= 0x92, /* 6 port PCS */
257 	PCS_7				= 0x94, /* 7+ port PCS (Denverton) */
271 	EM_CTL_SES		= BIT(18), /* SES-2 messages supported */
272 	EM_CTL_SAFTE		= BIT(17), /* SAF-TE messages supported */
277 	EM_MSG_TYPE_SAFTE	= BIT(1), /* SAF-TE */
278 	EM_MSG_TYPE_SES2	= BIT(2), /* SES-2 */
329 	/* Input fields */
333 	void __iomem *		mmio;		/* bus-independent mem map */
377 	/* only required for per-port MSI(-X) support */
439 	void __iomem *mmio = hpriv->mmio;  in __ahci_port_base()
446 	struct ahci_host_priv *hpriv = ap->host->private_data;  in ahci_port_base()
448 	return __ahci_port_base(hpriv, ap->port_no);  in ahci_port_base()