Lines Matching +full:rx +full:- +full:pcs +full:- +full:input
1 // SPDX-License-Identifier: GPL-2.0+
13 * load balancing (non-VLAN mode)
16 * page-based RX descriptor engine with separate completion rings
17 * Gigabit support (GMII and PCS interface)
20 * RX is handled by page sized buffers that are attached as fragments to
22 * -- driver allocates pages at a time and keeps reference counts
24 * -- the upper protocol layers assume that the header is in the skb
27 * -- driver appends the rest of the data pages as frags to skbuffs
29 * -- on page reclamation, the driver swaps the page with a spare page.
37 * TX has 4 queues. currently these queues are used in a round-robin
41 * alternatively, the queues can be configured via use of the all-purpose
44 * RX DATA: the rx completion ring has all the info, but the rx desc
45 * ring has all of the data. RX can conceivably come in under multiple
49 * encrypted and non-encrypted packets, but we use them for buffering
52 * by default, the selective clear mask is set up to process rx packets.
71 #include <linux/dma-mapping.h>
111 * also, we need to make cp->lock finer-grained.
120 /* rx processing options */
121 #define USE_PAGE_ORDER /* specify to allocate large rx pages */
125 #undef RX_COUNT_BUFFERS /* define to calculate RX buffer stats */
142 * and dev->tx_timeout() should be called to fix the problem
155 * max mtu == 2 * page size - ethernet header - 64 - swivel =
156 * 2 * page_size - 0x50
161 #define CAS_MAX_MTU min(((cp->page_size << 1) - 0x50), 9000)
177 static int cassini_debug = -1; /* -1 == use CAS_DEF_MSG_ENABLE as value */
190 * Work around for a PCS bug in which the link goes down due to the chip
195 * Value in seconds, for user input.
200 "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
237 spin_lock_nested(&cp->tx_lock[i], i); in cas_lock_tx()
251 spin_lock_irqsave(&xxxcp->lock, flags); \
259 for (i = N_TX_RINGS; i > 0; i--) in cas_unlock_tx()
260 spin_unlock(&cp->tx_lock[i - 1]); in cas_unlock_tx()
267 spin_unlock_irqrestore(&xxxcp->lock, flags); \
274 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK); in cas_disable_irq()
279 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { in cas_disable_irq()
292 cp->regs + REG_PLUS_INTRN_MASK(ring)); in cas_disable_irq()
296 writel(INTRN_MASK_CLEAR_ALL, cp->regs + in cas_disable_irq()
314 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK); in cas_enable_irq()
318 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { in cas_enable_irq()
330 writel(INTRN_MASK_RX_EN, cp->regs + in cas_enable_irq()
351 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0) in cas_entropy_gather()
354 batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV), in cas_entropy_gather()
355 readl(cp->regs + REG_ENTROPY_IV), in cas_entropy_gather()
363 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0) in cas_entropy_reset()
367 cp->regs + REG_BIM_LOCAL_DEV_EN); in cas_entropy_reset()
368 writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET); in cas_entropy_reset()
369 writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG); in cas_entropy_reset()
372 if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0) in cas_entropy_reset()
373 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV; in cas_entropy_reset()
378 * be in frame rather than bit-bang mode
386 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr); in cas_phy_read()
389 writel(cmd, cp->regs + REG_MIF_FRAME); in cas_phy_read()
392 while (limit-- > 0) { in cas_phy_read()
394 cmd = readl(cp->regs + REG_MIF_FRAME); in cas_phy_read()
398 return 0xFFFF; /* -1 */ in cas_phy_read()
407 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr); in cas_phy_write()
411 writel(cmd, cp->regs + REG_MIF_FRAME); in cas_phy_write()
414 while (limit-- > 0) { in cas_phy_write()
416 cmd = readl(cp->regs + REG_MIF_FRAME); in cas_phy_write()
420 return -1; in cas_phy_write()
443 /* cp->lock held. note: the last put_page will free the buffer */
446 dma_unmap_page(&cp->pdev->dev, page->dma_addr, cp->page_size, in cas_page_free()
448 __free_pages(page->buffer, cp->page_order); in cas_page_free()
454 #define RX_USED_ADD(x, y) ((x)->used += (y))
455 #define RX_USED_SET(x, y) ((x)->used = (y))
472 INIT_LIST_HEAD(&page->list); in cas_page_alloc()
474 page->buffer = alloc_pages(flags, cp->page_order); in cas_page_alloc()
475 if (!page->buffer) in cas_page_alloc()
477 page->dma_addr = dma_map_page(&cp->pdev->dev, page->buffer, 0, in cas_page_alloc()
478 cp->page_size, DMA_FROM_DEVICE); in cas_page_alloc()
486 /* initialize spare pool of rx buffers, but allocate during the open */
489 spin_lock(&cp->rx_inuse_lock); in cas_spare_init()
490 INIT_LIST_HEAD(&cp->rx_inuse_list); in cas_spare_init()
491 spin_unlock(&cp->rx_inuse_lock); in cas_spare_init()
493 spin_lock(&cp->rx_spare_lock); in cas_spare_init()
494 INIT_LIST_HEAD(&cp->rx_spare_list); in cas_spare_init()
495 cp->rx_spares_needed = RX_SPARE_COUNT; in cas_spare_init()
496 spin_unlock(&cp->rx_spare_lock); in cas_spare_init()
506 spin_lock(&cp->rx_spare_lock); in cas_spare_free()
507 list_splice_init(&cp->rx_spare_list, &list); in cas_spare_free()
508 spin_unlock(&cp->rx_spare_lock); in cas_spare_free()
519 spin_lock(&cp->rx_inuse_lock); in cas_spare_free()
520 list_splice_init(&cp->rx_inuse_list, &list); in cas_spare_free()
521 spin_unlock(&cp->rx_inuse_lock); in cas_spare_free()
523 spin_lock(&cp->rx_spare_lock); in cas_spare_free()
524 list_splice_init(&cp->rx_inuse_list, &list); in cas_spare_free()
525 spin_unlock(&cp->rx_spare_lock); in cas_spare_free()
544 spin_lock(&cp->rx_inuse_lock); in cas_spare_recover()
545 list_splice_init(&cp->rx_inuse_list, &list); in cas_spare_recover()
546 spin_unlock(&cp->rx_inuse_lock); in cas_spare_recover()
555 * and skip it as in-use. Ideally we would be able to reclaim in cas_spare_recover()
563 if (page_count(page->buffer) > 1) in cas_spare_recover()
567 spin_lock(&cp->rx_spare_lock); in cas_spare_recover()
568 if (cp->rx_spares_needed > 0) { in cas_spare_recover()
569 list_add(elem, &cp->rx_spare_list); in cas_spare_recover()
570 cp->rx_spares_needed--; in cas_spare_recover()
571 spin_unlock(&cp->rx_spare_lock); in cas_spare_recover()
573 spin_unlock(&cp->rx_spare_lock); in cas_spare_recover()
580 spin_lock(&cp->rx_inuse_lock); in cas_spare_recover()
581 list_splice(&list, &cp->rx_inuse_list); in cas_spare_recover()
582 spin_unlock(&cp->rx_inuse_lock); in cas_spare_recover()
585 spin_lock(&cp->rx_spare_lock); in cas_spare_recover()
586 needed = cp->rx_spares_needed; in cas_spare_recover()
587 spin_unlock(&cp->rx_spare_lock); in cas_spare_recover()
598 list_add(&spare->list, &list); in cas_spare_recover()
602 spin_lock(&cp->rx_spare_lock); in cas_spare_recover()
603 list_splice(&list, &cp->rx_spare_list); in cas_spare_recover()
604 cp->rx_spares_needed -= i; in cas_spare_recover()
605 spin_unlock(&cp->rx_spare_lock); in cas_spare_recover()
614 spin_lock(&cp->rx_spare_lock); in cas_page_dequeue()
615 if (list_empty(&cp->rx_spare_list)) { in cas_page_dequeue()
617 spin_unlock(&cp->rx_spare_lock); in cas_page_dequeue()
619 spin_lock(&cp->rx_spare_lock); in cas_page_dequeue()
620 if (list_empty(&cp->rx_spare_list)) { in cas_page_dequeue()
621 netif_err(cp, rx_err, cp->dev, in cas_page_dequeue()
623 spin_unlock(&cp->rx_spare_lock); in cas_page_dequeue()
628 entry = cp->rx_spare_list.next; in cas_page_dequeue()
630 recover = ++cp->rx_spares_needed; in cas_page_dequeue()
631 spin_unlock(&cp->rx_spare_lock); in cas_page_dequeue()
634 if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) { in cas_page_dequeue()
636 atomic_inc(&cp->reset_task_pending); in cas_page_dequeue()
637 atomic_inc(&cp->reset_task_pending_spare); in cas_page_dequeue()
638 schedule_work(&cp->reset_task); in cas_page_dequeue()
640 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE); in cas_page_dequeue()
641 schedule_work(&cp->reset_task); in cas_page_dequeue()
652 cfg = readl(cp->regs + REG_MIF_CFG); in cas_mif_poll()
655 if (cp->phy_type & CAS_PHY_MII_MDIO1) in cas_mif_poll()
662 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr); in cas_mif_poll()
665 cp->regs + REG_MIF_MASK); in cas_mif_poll()
666 writel(cfg, cp->regs + REG_MIF_CFG); in cas_mif_poll()
669 /* Must be invoked under cp->lock */
677 int oldstate = cp->lstate; in cas_begin_auto_negotiation()
683 lcntl = cp->link_cntl; in cas_begin_auto_negotiation()
684 if (ep->base.autoneg == AUTONEG_ENABLE) { in cas_begin_auto_negotiation()
685 cp->link_cntl = BMCR_ANENABLE; in cas_begin_auto_negotiation()
687 u32 speed = ep->base.speed; in cas_begin_auto_negotiation()
688 cp->link_cntl = 0; in cas_begin_auto_negotiation()
690 cp->link_cntl |= BMCR_SPEED100; in cas_begin_auto_negotiation()
692 cp->link_cntl |= CAS_BMCR_SPEED1000; in cas_begin_auto_negotiation()
693 if (ep->base.duplex == DUPLEX_FULL) in cas_begin_auto_negotiation()
694 cp->link_cntl |= BMCR_FULLDPLX; in cas_begin_auto_negotiation()
697 changed = (lcntl != cp->link_cntl); in cas_begin_auto_negotiation()
700 if (cp->lstate == link_up) { in cas_begin_auto_negotiation()
701 netdev_info(cp->dev, "PCS link down\n"); in cas_begin_auto_negotiation()
704 netdev_info(cp->dev, "link configuration changed\n"); in cas_begin_auto_negotiation()
707 cp->lstate = link_down; in cas_begin_auto_negotiation()
708 cp->link_transition = LINK_TRANSITION_LINK_DOWN; in cas_begin_auto_negotiation()
709 if (!cp->hw_running) in cas_begin_auto_negotiation()
714 * to replicate everything we do elsewhere on a link-down in cas_begin_auto_negotiation()
715 * event when we were already in a link-up state.. in cas_begin_auto_negotiation()
718 netif_carrier_off(cp->dev); in cas_begin_auto_negotiation()
723 * fixes the link-problems we were having for forced mode. in cas_begin_auto_negotiation()
725 atomic_inc(&cp->reset_task_pending); in cas_begin_auto_negotiation()
726 atomic_inc(&cp->reset_task_pending_all); in cas_begin_auto_negotiation()
727 schedule_work(&cp->reset_task); in cas_begin_auto_negotiation()
728 cp->timer_ticks = 0; in cas_begin_auto_negotiation()
729 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT); in cas_begin_auto_negotiation()
733 if (cp->phy_type & CAS_PHY_SERDES) { in cas_begin_auto_negotiation()
734 u32 val = readl(cp->regs + REG_PCS_MII_CTRL); in cas_begin_auto_negotiation()
736 if (cp->link_cntl & BMCR_ANENABLE) { in cas_begin_auto_negotiation()
738 cp->lstate = link_aneg; in cas_begin_auto_negotiation()
740 if (cp->link_cntl & BMCR_FULLDPLX) in cas_begin_auto_negotiation()
743 cp->lstate = link_force_ok; in cas_begin_auto_negotiation()
745 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; in cas_begin_auto_negotiation()
746 writel(val, cp->regs + REG_PCS_MII_CTRL); in cas_begin_auto_negotiation()
753 ctl |= cp->link_cntl; in cas_begin_auto_negotiation()
756 cp->lstate = link_aneg; in cas_begin_auto_negotiation()
758 cp->lstate = link_force_ok; in cas_begin_auto_negotiation()
760 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; in cas_begin_auto_negotiation()
765 cp->timer_ticks = 0; in cas_begin_auto_negotiation()
766 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT); in cas_begin_auto_negotiation()
769 /* Must be invoked under cp->lock. */
777 while (--limit) { in cas_reset_mii_phy()
792 if (PHY_NS_DP83065 != cp->phy_id) in cas_saturn_firmware_init()
795 err = request_firmware(&fw, fw_name, &cp->pdev->dev); in cas_saturn_firmware_init()
801 if (fw->size < 2) { in cas_saturn_firmware_init()
803 fw->size, fw_name); in cas_saturn_firmware_init()
806 cp->fw_load_addr= fw->data[1] << 8 | fw->data[0]; in cas_saturn_firmware_init()
807 cp->fw_size = fw->size - 2; in cas_saturn_firmware_init()
808 cp->fw_data = vmalloc(cp->fw_size); in cas_saturn_firmware_init()
809 if (!cp->fw_data) in cas_saturn_firmware_init()
811 memcpy(cp->fw_data, &fw->data[2], cp->fw_size); in cas_saturn_firmware_init()
820 if (!cp->fw_data) in cas_saturn_firmware_load()
840 cas_phy_write(cp, DP83065_MII_REGE, cp->fw_load_addr); in cas_saturn_firmware_load()
841 for (i = 0; i < cp->fw_size; i++) in cas_saturn_firmware_load()
842 cas_phy_write(cp, DP83065_MII_REGD, cp->fw_data[i]); in cas_saturn_firmware_load()
856 if (CAS_PHY_MII(cp->phy_type)) { in cas_phy_init()
858 cp->regs + REG_PCS_DATAPATH_MODE); in cas_phy_init()
863 if (PHY_LUCENT_B0 == cp->phy_id) { in cas_phy_init()
869 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) { in cas_phy_init()
883 } else if (PHY_BROADCOM_5411 == cp->phy_id) { in cas_phy_init()
892 } else if (cp->cas_flags & CAS_FLAG_SATURN) { in cas_phy_init()
893 writel((cp->phy_type & CAS_PHY_MII_MDIO0) ? in cas_phy_init()
895 cp->regs + REG_SATURN_PCFG); in cas_phy_init()
897 /* load firmware to address 10Mbps auto-negotiation in cas_phy_init()
901 if (PHY_NS_DP83065 == cp->phy_id) { in cas_phy_init()
920 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) { in cas_phy_init()
931 /* reset pcs for serdes */ in cas_phy_init()
936 cp->regs + REG_PCS_DATAPATH_MODE); in cas_phy_init()
939 if (cp->cas_flags & CAS_FLAG_SATURN) in cas_phy_init()
940 writel(0, cp->regs + REG_SATURN_PCFG); in cas_phy_init()
942 /* Reset PCS unit. */ in cas_phy_init()
943 val = readl(cp->regs + REG_PCS_MII_CTRL); in cas_phy_init()
945 writel(val, cp->regs + REG_PCS_MII_CTRL); in cas_phy_init()
948 while (--limit > 0) { in cas_phy_init()
950 if ((readl(cp->regs + REG_PCS_MII_CTRL) & in cas_phy_init()
955 netdev_warn(cp->dev, "PCS reset bit would not clear [%08x]\n", in cas_phy_init()
956 readl(cp->regs + REG_PCS_STATE_MACHINE)); in cas_phy_init()
958 /* Make sure PCS is disabled while changing advertisement in cas_phy_init()
961 writel(0x0, cp->regs + REG_PCS_CFG); in cas_phy_init()
963 /* Advertise all capabilities except half-duplex. */ in cas_phy_init()
964 val = readl(cp->regs + REG_PCS_MII_ADVERT); in cas_phy_init()
968 writel(val, cp->regs + REG_PCS_MII_ADVERT); in cas_phy_init()
970 /* enable PCS */ in cas_phy_init()
971 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG); in cas_phy_init()
973 /* pcs workaround: enable sync detect */ in cas_phy_init()
975 cp->regs + REG_PCS_SERDES_CTRL); in cas_phy_init()
989 stat = readl(cp->regs + REG_PCS_MII_STATUS); in cas_pcs_link_check()
991 stat = readl(cp->regs + REG_PCS_MII_STATUS); in cas_pcs_link_check()
993 /* The remote-fault indication is only valid in cas_pcs_link_check()
999 netif_info(cp, link, cp->dev, "PCS RemoteFault\n"); in cas_pcs_link_check()
1001 /* work around link detection issue by querying the PCS state in cas_pcs_link_check()
1004 state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE); in cas_pcs_link_check()
1012 if (cp->lstate != link_up) { in cas_pcs_link_check()
1013 if (cp->opened) { in cas_pcs_link_check()
1014 cp->lstate = link_up; in cas_pcs_link_check()
1015 cp->link_transition = LINK_TRANSITION_LINK_UP; in cas_pcs_link_check()
1018 netif_carrier_on(cp->dev); in cas_pcs_link_check()
1021 } else if (cp->lstate == link_up) { in cas_pcs_link_check()
1022 cp->lstate = link_down; in cas_pcs_link_check()
1024 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET && in cas_pcs_link_check()
1025 !cp->link_transition_jiffies_valid) { in cas_pcs_link_check()
1028 * link-failure problem. May want to move this to a in cas_pcs_link_check()
1035 * link timer is running - this clears the flag after in cas_pcs_link_check()
1039 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET; in cas_pcs_link_check()
1040 cp->link_transition_jiffies = jiffies; in cas_pcs_link_check()
1041 cp->link_transition_jiffies_valid = 1; in cas_pcs_link_check()
1043 cp->link_transition = LINK_TRANSITION_ON_FAILURE; in cas_pcs_link_check()
1045 netif_carrier_off(cp->dev); in cas_pcs_link_check()
1046 if (cp->opened) in cas_pcs_link_check()
1047 netif_info(cp, link, cp->dev, "PCS link down\n"); in cas_pcs_link_check()
1053 * 2) read pcs status register to verify link down. in cas_pcs_link_check()
1057 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) { in cas_pcs_link_check()
1059 stat = readl(cp->regs + REG_PCS_SERDES_STATE); in cas_pcs_link_check()
1063 } else if (cp->lstate == link_down) { in cas_pcs_link_check()
1065 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET && in cas_pcs_link_check()
1066 !cp->link_transition_jiffies_valid) { in cas_pcs_link_check()
1068 * link-failure problem. May want to move in cas_pcs_link_check()
1073 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET; in cas_pcs_link_check()
1074 cp->link_transition_jiffies = jiffies; in cas_pcs_link_check()
1075 cp->link_transition_jiffies_valid = 1; in cas_pcs_link_check()
1077 cp->link_transition = LINK_TRANSITION_STILL_FAILED; in cas_pcs_link_check()
1087 u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS); in cas_pcs_interrupt()
1097 u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS); in cas_txmac_interrupt()
1102 netif_printk(cp, intr, KERN_DEBUG, cp->dev, in cas_txmac_interrupt()
1112 spin_lock(&cp->stat_lock[0]); in cas_txmac_interrupt()
1115 cp->net_stats[0].tx_fifo_errors++; in cas_txmac_interrupt()
1120 cp->net_stats[0].tx_errors++; in cas_txmac_interrupt()
1123 /* The rest are all cases of one of the 16-bit TX in cas_txmac_interrupt()
1127 cp->net_stats[0].collisions += 0x10000; in cas_txmac_interrupt()
1130 cp->net_stats[0].tx_aborted_errors += 0x10000; in cas_txmac_interrupt()
1131 cp->net_stats[0].collisions += 0x10000; in cas_txmac_interrupt()
1135 cp->net_stats[0].tx_aborted_errors += 0x10000; in cas_txmac_interrupt()
1136 cp->net_stats[0].collisions += 0x10000; in cas_txmac_interrupt()
1138 spin_unlock(&cp->stat_lock[0]); in cas_txmac_interrupt()
1153 while ((inst = firmware) && inst->note) { in cas_load_firmware()
1154 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR); in cas_load_firmware()
1156 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val); in cas_load_firmware()
1157 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask); in cas_load_firmware()
1158 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI); in cas_load_firmware()
1160 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10); in cas_load_firmware()
1161 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop); in cas_load_firmware()
1162 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext); in cas_load_firmware()
1163 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff); in cas_load_firmware()
1164 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext); in cas_load_firmware()
1165 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff); in cas_load_firmware()
1166 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op); in cas_load_firmware()
1167 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID); in cas_load_firmware()
1169 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask); in cas_load_firmware()
1170 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift); in cas_load_firmware()
1171 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab); in cas_load_firmware()
1172 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg); in cas_load_firmware()
1173 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW); in cas_load_firmware()
1181 u64 desc_dma = cp->block_dvma; in cas_init_rx_dma()
1185 /* rx free descriptors */ in cas_init_rx_dma()
1190 (cp->cas_flags & CAS_FLAG_REG_PLUS)) /* do desc 2 */ in cas_init_rx_dma()
1192 writel(val, cp->regs + REG_RX_CFG); in cas_init_rx_dma()
1194 val = (unsigned long) cp->init_rxds[0] - in cas_init_rx_dma()
1195 (unsigned long) cp->init_block; in cas_init_rx_dma()
1196 writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI); in cas_init_rx_dma()
1197 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW); in cas_init_rx_dma()
1198 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK); in cas_init_rx_dma()
1200 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { in cas_init_rx_dma()
1201 /* rx desc 2 is for IPSEC packets. however, in cas_init_rx_dma()
1204 val = (unsigned long) cp->init_rxds[1] - in cas_init_rx_dma()
1205 (unsigned long) cp->init_block; in cas_init_rx_dma()
1206 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI); in cas_init_rx_dma()
1207 writel((desc_dma + val) & 0xffffffff, cp->regs + in cas_init_rx_dma()
1209 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs + in cas_init_rx_dma()
1213 /* rx completion registers */ in cas_init_rx_dma()
1214 val = (unsigned long) cp->init_rxcs[0] - in cas_init_rx_dma()
1215 (unsigned long) cp->init_block; in cas_init_rx_dma()
1216 writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI); in cas_init_rx_dma()
1217 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW); in cas_init_rx_dma()
1219 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { in cas_init_rx_dma()
1220 /* rx comp 2-4 */ in cas_init_rx_dma()
1222 val = (unsigned long) cp->init_rxcs[i] - in cas_init_rx_dma()
1223 (unsigned long) cp->init_block; in cas_init_rx_dma()
1224 writel((desc_dma + val) >> 32, cp->regs + in cas_init_rx_dma()
1226 writel((desc_dma + val) & 0xffffffff, cp->regs + in cas_init_rx_dma()
1235 readl(cp->regs + REG_INTR_STATUS_ALIAS); in cas_init_rx_dma()
1236 writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR); in cas_init_rx_dma()
1240 cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM); in cas_init_rx_dma()
1242 cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM); in cas_init_rx_dma()
1243 writel(val, cp->regs + REG_RX_PAUSE_THRESH); in cas_init_rx_dma()
1247 writel(i, cp->regs + REG_RX_TABLE_ADDR); in cas_init_rx_dma()
1248 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW); in cas_init_rx_dma()
1249 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID); in cas_init_rx_dma()
1250 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI); in cas_init_rx_dma()
1254 writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR); in cas_init_rx_dma()
1255 writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR); in cas_init_rx_dma()
1261 writel(val, cp->regs + REG_RX_BLANK); in cas_init_rx_dma()
1263 writel(0x0, cp->regs + REG_RX_BLANK); in cas_init_rx_dma()
1268 * housekeeping for rx descs. we don't use the free interrupt in cas_init_rx_dma()
1273 writel(val, cp->regs + REG_RX_AE_THRESH); in cas_init_rx_dma()
1274 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { in cas_init_rx_dma()
1276 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH); in cas_init_rx_dma()
1282 writel(0x0, cp->regs + REG_RX_RED); in cas_init_rx_dma()
1286 if (cp->page_size == 0x1000) in cas_init_rx_dma()
1288 else if (cp->page_size == 0x2000) in cas_init_rx_dma()
1290 else if (cp->page_size == 0x4000) in cas_init_rx_dma()
1294 size = cp->dev->mtu + 64; in cas_init_rx_dma()
1295 if (size > cp->page_size) in cas_init_rx_dma()
1296 size = cp->page_size; in cas_init_rx_dma()
1307 cp->mtu_stride = 1 << (i + 10); in cas_init_rx_dma()
1310 val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10)); in cas_init_rx_dma()
1312 writel(val, cp->regs + REG_RX_PAGE_SIZE); in cas_init_rx_dma()
1321 writel(val, cp->regs + REG_HP_CFG); in cas_init_rx_dma()
1327 rxc->word4 = cpu_to_le64(RX_COMP4_ZERO); in cas_rxc_init()
1330 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
1336 cas_page_t *page = cp->rx_pages[1][index]; in cas_page_spare()
1339 if (page_count(page->buffer) == 1) in cas_page_spare()
1344 spin_lock(&cp->rx_inuse_lock); in cas_page_spare()
1345 list_add(&page->list, &cp->rx_inuse_list); in cas_page_spare()
1346 spin_unlock(&cp->rx_inuse_lock); in cas_page_spare()
1351 /* this needs to be changed if we actually use the ENC RX DESC ring */
1355 cas_page_t **page0 = cp->rx_pages[0]; in cas_page_swap()
1356 cas_page_t **page1 = cp->rx_pages[1]; in cas_page_swap()
1359 if (page_count(page0[index]->buffer) > 1) { in cas_page_swap()
1373 struct cas_rx_desc *rxd = cp->init_rxds[0]; in cas_clean_rxds()
1376 /* release all rx flows */ in cas_clean_rxds()
1379 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) { in cas_clean_rxds()
1388 rxd[i].buffer = cpu_to_le64(page->dma_addr); in cas_clean_rxds()
1393 cp->rx_old[0] = RX_DESC_RINGN_SIZE(0) - 4; in cas_clean_rxds()
1394 cp->rx_last[0] = 0; in cas_clean_rxds()
1395 cp->cas_flags &= ~CAS_FLAG_RXD_POST(0); in cas_clean_rxds()
1402 /* take ownership of rx comp descriptors */ in cas_clean_rxcs()
1403 memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS); in cas_clean_rxcs()
1404 memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS); in cas_clean_rxcs()
1406 struct cas_rx_comp *rxc = cp->init_rxcs[i]; in cas_clean_rxcs()
1414 /* When we get a RX fifo overflow, the RX unit is probably hung
1422 struct net_device *dev = cp->dev;
1426 /* First, reset MAC RX. */
1427 writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1429 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1434 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
1438 /* Second, disable RX DMA. */
1439 writel(0, cp->regs + REG_RX_CFG);
1441 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1446 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
1452 /* Execute RX reset command. */
1453 writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1455 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1460 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
1464 /* reset driver rx state */
1468 /* Now, reprogram the rest of RX unit. */
1471 /* re-enable */
1472 val = readl(cp->regs + REG_RX_CFG);
1473 writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1474 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1475 val = readl(cp->regs + REG_MAC_RX_CFG);
1476 writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1484 u32 stat = readl(cp->regs + REG_MAC_RX_STATUS); in cas_rxmac_interrupt()
1489 netif_dbg(cp, intr, cp->dev, "rxmac interrupt, stat: 0x%x\n", stat); in cas_rxmac_interrupt()
1492 spin_lock(&cp->stat_lock[0]); in cas_rxmac_interrupt()
1494 cp->net_stats[0].rx_frame_errors += 0x10000; in cas_rxmac_interrupt()
1497 cp->net_stats[0].rx_crc_errors += 0x10000; in cas_rxmac_interrupt()
1500 cp->net_stats[0].rx_length_errors += 0x10000; in cas_rxmac_interrupt()
1503 cp->net_stats[0].rx_over_errors++; in cas_rxmac_interrupt()
1504 cp->net_stats[0].rx_fifo_errors++; in cas_rxmac_interrupt()
1510 spin_unlock(&cp->stat_lock[0]); in cas_rxmac_interrupt()
1517 u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS); in cas_mac_interrupt()
1522 netif_printk(cp, intr, KERN_DEBUG, cp->dev, in cas_mac_interrupt()
1530 cp->pause_entered++; in cas_mac_interrupt()
1533 cp->pause_last_time_recvd = (stat >> 16); in cas_mac_interrupt()
1539 /* Must be invoked under cp->lock. */
1544 switch (cp->lstate) { in cas_mdio_link_not_up()
1546 netif_info(cp, link, cp->dev, "Autoneg failed again, keeping forced mode\n"); in cas_mdio_link_not_up()
1547 cas_phy_write(cp, MII_BMCR, cp->link_fcntl); in cas_mdio_link_not_up()
1548 cp->timer_ticks = 5; in cas_mdio_link_not_up()
1549 cp->lstate = link_force_ok; in cas_mdio_link_not_up()
1550 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; in cas_mdio_link_not_up()
1557 * 1000 full -> 100 full/half -> 10 half in cas_mdio_link_not_up()
1561 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ? in cas_mdio_link_not_up()
1564 cp->timer_ticks = 5; in cas_mdio_link_not_up()
1565 cp->lstate = link_force_try; in cas_mdio_link_not_up()
1566 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; in cas_mdio_link_not_up()
1572 cp->timer_ticks = 5; in cas_mdio_link_not_up()
1597 /* must be invoked with cp->lock held */
1608 if ((cp->lstate == link_force_try) && in cas_mii_link_check()
1609 (cp->link_cntl & BMCR_ANENABLE)) { in cas_mii_link_check()
1610 cp->lstate = link_force_ret; in cas_mii_link_check()
1611 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; in cas_mii_link_check()
1613 cp->link_fcntl = cas_phy_read(cp, MII_BMCR); in cas_mii_link_check()
1614 cp->timer_ticks = 5; in cas_mii_link_check()
1615 if (cp->opened) in cas_mii_link_check()
1616 netif_info(cp, link, cp->dev, in cas_mii_link_check()
1619 cp->link_fcntl | BMCR_ANENABLE | in cas_mii_link_check()
1623 } else if (cp->lstate != link_up) { in cas_mii_link_check()
1624 cp->lstate = link_up; in cas_mii_link_check()
1625 cp->link_transition = LINK_TRANSITION_LINK_UP; in cas_mii_link_check()
1627 if (cp->opened) { in cas_mii_link_check()
1629 netif_carrier_on(cp->dev); in cas_mii_link_check()
1639 if (cp->lstate == link_up) { in cas_mii_link_check()
1640 cp->lstate = link_down; in cas_mii_link_check()
1641 cp->link_transition = LINK_TRANSITION_LINK_DOWN; in cas_mii_link_check()
1643 netif_carrier_off(cp->dev); in cas_mii_link_check()
1644 if (cp->opened) in cas_mii_link_check()
1645 netif_info(cp, link, cp->dev, "Link down\n"); in cas_mii_link_check()
1648 } else if (++cp->timer_ticks > 10) in cas_mii_link_check()
1657 u32 stat = readl(cp->regs + REG_MIF_STATUS); in cas_mif_interrupt()
1671 u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS); in cas_pci_interrupt()
1677 stat, readl(cp->regs + REG_BIM_DIAG)); in cas_pci_interrupt()
1681 ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0)) in cas_pci_interrupt()
1700 pci_errs = pci_status_get_and_clear_errors(cp->pdev); in cas_pci_interrupt()
1721 /* All non-normal interrupt conditions get serviced here.
1722 * Returns non-zero if we should just exit the interrupt
1730 /* corrupt RX tag framing */ in cas_abnormal_irq()
1731 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev, in cas_abnormal_irq()
1732 "corrupt rx tag framing\n"); in cas_abnormal_irq()
1733 spin_lock(&cp->stat_lock[0]); in cas_abnormal_irq()
1734 cp->net_stats[0].rx_errors++; in cas_abnormal_irq()
1735 spin_unlock(&cp->stat_lock[0]); in cas_abnormal_irq()
1741 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev, in cas_abnormal_irq()
1742 "length mismatch for rx frame\n"); in cas_abnormal_irq()
1743 spin_lock(&cp->stat_lock[0]); in cas_abnormal_irq()
1744 cp->net_stats[0].rx_errors++; in cas_abnormal_irq()
1745 spin_unlock(&cp->stat_lock[0]); in cas_abnormal_irq()
1782 atomic_inc(&cp->reset_task_pending); in cas_abnormal_irq()
1783 atomic_inc(&cp->reset_task_pending_all); in cas_abnormal_irq()
1785 schedule_work(&cp->reset_task); in cas_abnormal_irq()
1787 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL); in cas_abnormal_irq()
1789 schedule_work(&cp->reset_task); in cas_abnormal_irq()
1797 #define CAS_TABORT(x) (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1798 #define CAS_ROUND_PAGE(x) (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1806 if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN) in cas_calc_tabort()
1815 struct net_device *dev = cp->dev; in cas_tx_ringN()
1818 spin_lock(&cp->tx_lock[ring]); in cas_tx_ringN()
1819 txds = cp->init_txds[ring]; in cas_tx_ringN()
1820 skbs = cp->tx_skbs[ring]; in cas_tx_ringN()
1821 entry = cp->tx_old[ring]; in cas_tx_ringN()
1837 count -= skb_shinfo(skb)->nr_frags + in cas_tx_ringN()
1838 + cp->tx_tiny_use[ring][entry].nbufs + 1; in cas_tx_ringN()
1842 netif_printk(cp, tx_done, KERN_DEBUG, cp->dev, in cas_tx_ringN()
1846 cp->tx_tiny_use[ring][entry].nbufs = 0; in cas_tx_ringN()
1848 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { in cas_tx_ringN()
1851 daddr = le64_to_cpu(txd->buffer); in cas_tx_ringN()
1853 le64_to_cpu(txd->control)); in cas_tx_ringN()
1854 dma_unmap_page(&cp->pdev->dev, daddr, dlen, in cas_tx_ringN()
1859 if (cp->tx_tiny_use[ring][entry].used) { in cas_tx_ringN()
1860 cp->tx_tiny_use[ring][entry].used = 0; in cas_tx_ringN()
1865 spin_lock(&cp->stat_lock[ring]); in cas_tx_ringN()
1866 cp->net_stats[ring].tx_packets++; in cas_tx_ringN()
1867 cp->net_stats[ring].tx_bytes += skb->len; in cas_tx_ringN()
1868 spin_unlock(&cp->stat_lock[ring]); in cas_tx_ringN()
1871 cp->tx_old[ring] = entry; in cas_tx_ringN()
1880 spin_unlock(&cp->tx_lock[ring]); in cas_tx_ringN()
1888 u64 compwb = le64_to_cpu(cp->init_block->tx_compwb); in cas_tx()
1890 netif_printk(cp, intr, KERN_DEBUG, cp->dev, in cas_tx()
1901 limit = readl(cp->regs + REG_TX_COMPN(ring)); in cas_tx()
1903 if (cp->tx_old[ring] != limit) in cas_tx()
1930 skb = netdev_alloc_skb(cp->dev, alloclen + swivel + cp->crc_size); in cas_rx_process_pkt()
1932 return -1; in cas_rx_process_pkt()
1937 p = skb->data; in cas_rx_process_pkt()
1941 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; in cas_rx_process_pkt()
1947 i += cp->crc_size; in cas_rx_process_pkt()
1948 dma_sync_single_for_cpu(&cp->pdev->dev, page->dma_addr + off, in cas_rx_process_pkt()
1950 memcpy(p, page_address(page->buffer) + off, i); in cas_rx_process_pkt()
1951 dma_sync_single_for_device(&cp->pdev->dev, in cas_rx_process_pkt()
1952 page->dma_addr + off, i, in cas_rx_process_pkt()
1961 skb_frag_t *frag = skb_shinfo(skb)->frags; in cas_rx_process_pkt()
1965 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; in cas_rx_process_pkt()
1968 hlen = min(cp->page_size - off, dlen); in cas_rx_process_pkt()
1970 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev, in cas_rx_process_pkt()
1971 "rx page overflow: %d\n", hlen); in cas_rx_process_pkt()
1973 return -1; in cas_rx_process_pkt()
1977 i += cp->crc_size; in cas_rx_process_pkt()
1978 dma_sync_single_for_cpu(&cp->pdev->dev, page->dma_addr + off, in cas_rx_process_pkt()
1983 if (p == (char *) skb->data) { /* not split */ in cas_rx_process_pkt()
1984 memcpy(p, page_address(page->buffer) + off, in cas_rx_process_pkt()
1986 dma_sync_single_for_device(&cp->pdev->dev, in cas_rx_process_pkt()
1987 page->dma_addr + off, i, in cas_rx_process_pkt()
1991 RX_USED_ADD(page, cp->mtu_stride); in cas_rx_process_pkt()
1997 skb_shinfo(skb)->nr_frags++; in cas_rx_process_pkt()
1998 skb->data_len += hlen - swivel; in cas_rx_process_pkt()
1999 skb->truesize += hlen - swivel; in cas_rx_process_pkt()
2000 skb->len += hlen - swivel; in cas_rx_process_pkt()
2002 skb_frag_fill_page_desc(frag, page->buffer, off, hlen - swivel); in cas_rx_process_pkt()
2006 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) { in cas_rx_process_pkt()
2011 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; in cas_rx_process_pkt()
2012 dma_sync_single_for_cpu(&cp->pdev->dev, in cas_rx_process_pkt()
2013 page->dma_addr, in cas_rx_process_pkt()
2014 hlen + cp->crc_size, in cas_rx_process_pkt()
2016 dma_sync_single_for_device(&cp->pdev->dev, in cas_rx_process_pkt()
2017 page->dma_addr, in cas_rx_process_pkt()
2018 hlen + cp->crc_size, in cas_rx_process_pkt()
2021 skb_shinfo(skb)->nr_frags++; in cas_rx_process_pkt()
2022 skb->data_len += hlen; in cas_rx_process_pkt()
2023 skb->len += hlen; in cas_rx_process_pkt()
2026 skb_frag_fill_page_desc(frag, page->buffer, 0, hlen); in cas_rx_process_pkt()
2028 RX_USED_ADD(page, hlen + cp->crc_size); in cas_rx_process_pkt()
2031 if (cp->crc_size) in cas_rx_process_pkt()
2032 crcaddr = page_address(page->buffer) + off + hlen; in cas_rx_process_pkt()
2040 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; in cas_rx_process_pkt()
2042 hlen = min(cp->page_size - off, dlen); in cas_rx_process_pkt()
2044 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev, in cas_rx_process_pkt()
2045 "rx page overflow: %d\n", hlen); in cas_rx_process_pkt()
2047 return -1; in cas_rx_process_pkt()
2051 i += cp->crc_size; in cas_rx_process_pkt()
2052 dma_sync_single_for_cpu(&cp->pdev->dev, page->dma_addr + off, in cas_rx_process_pkt()
2054 memcpy(p, page_address(page->buffer) + off, i); in cas_rx_process_pkt()
2055 dma_sync_single_for_device(&cp->pdev->dev, in cas_rx_process_pkt()
2056 page->dma_addr + off, i, in cas_rx_process_pkt()
2058 if (p == (char *) skb->data) /* not split */ in cas_rx_process_pkt()
2059 RX_USED_ADD(page, cp->mtu_stride); in cas_rx_process_pkt()
2064 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) { in cas_rx_process_pkt()
2067 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; in cas_rx_process_pkt()
2068 dma_sync_single_for_cpu(&cp->pdev->dev, in cas_rx_process_pkt()
2069 page->dma_addr, in cas_rx_process_pkt()
2070 dlen + cp->crc_size, in cas_rx_process_pkt()
2072 memcpy(p, page_address(page->buffer), dlen + cp->crc_size); in cas_rx_process_pkt()
2073 dma_sync_single_for_device(&cp->pdev->dev, in cas_rx_process_pkt()
2074 page->dma_addr, in cas_rx_process_pkt()
2075 dlen + cp->crc_size, in cas_rx_process_pkt()
2077 RX_USED_ADD(page, dlen + cp->crc_size); in cas_rx_process_pkt()
2080 if (cp->crc_size) in cas_rx_process_pkt()
2081 crcaddr = skb->data + alloclen; in cas_rx_process_pkt()
2087 if (cp->crc_size) { in cas_rx_process_pkt()
2089 csum = csum_fold(csum_partial(crcaddr, cp->crc_size, in cas_rx_process_pkt()
2092 skb->protocol = eth_type_trans(skb, cp->dev); in cas_rx_process_pkt()
2093 if (skb->protocol == htons(ETH_P_IP)) { in cas_rx_process_pkt()
2094 skb->csum = csum_unfold(~csum); in cas_rx_process_pkt()
2095 skb->ip_summed = CHECKSUM_COMPLETE; in cas_rx_process_pkt()
2102 /* we can handle up to 64 rx flows at a time. we do the same thing
2119 int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1); in cas_rx_flow_pkt()
2120 struct sk_buff_head *flow = &cp->rx_flows[flowid]; in cas_rx_flow_pkt()
2134 /* put rx descriptor back on ring. if a buffer is in use by a higher
2142 entry = cp->rx_old[ring]; in cas_post_page()
2145 cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr); in cas_post_page()
2146 cp->init_rxds[ring][entry].index = in cas_post_page()
2151 cp->rx_old[ring] = entry; in cas_post_page()
2157 writel(entry, cp->regs + REG_RX_KICK); in cas_post_page()
2159 (cp->cas_flags & CAS_FLAG_REG_PLUS)) in cas_post_page()
2160 writel(entry, cp->regs + REG_PLUS_RX_KICK1); in cas_post_page()
2169 cas_page_t **page = cp->rx_pages[ring]; in cas_post_rxds_ringN()
2171 entry = cp->rx_old[ring]; in cas_post_rxds_ringN()
2173 netif_printk(cp, intr, KERN_DEBUG, cp->dev, in cas_post_rxds_ringN()
2176 cluster = -1; in cas_post_rxds_ringN()
2178 last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4); in cas_post_rxds_ringN()
2182 if (page_count(page[entry]->buffer) > 1) { in cas_post_rxds_ringN()
2188 cp->cas_flags |= CAS_FLAG_RXD_POST(ring); in cas_post_rxds_ringN()
2189 if (!timer_pending(&cp->link_timer)) in cas_post_rxds_ringN()
2190 mod_timer(&cp->link_timer, jiffies + in cas_post_rxds_ringN()
2192 cp->rx_old[ring] = entry; in cas_post_rxds_ringN()
2193 cp->rx_last[ring] = num ? num - released : 0; in cas_post_rxds_ringN()
2194 return -ENOMEM; in cas_post_rxds_ringN()
2196 spin_lock(&cp->rx_inuse_lock); in cas_post_rxds_ringN()
2197 list_add(&page[entry]->list, &cp->rx_inuse_list); in cas_post_rxds_ringN()
2198 spin_unlock(&cp->rx_inuse_lock); in cas_post_rxds_ringN()
2199 cp->init_rxds[ring][entry].buffer = in cas_post_rxds_ringN()
2200 cpu_to_le64(new->dma_addr); in cas_post_rxds_ringN()
2212 cp->rx_old[ring] = entry; in cas_post_rxds_ringN()
2218 writel(cluster, cp->regs + REG_RX_KICK); in cas_post_rxds_ringN()
2220 (cp->cas_flags & CAS_FLAG_REG_PLUS)) in cas_post_rxds_ringN()
2221 writel(cluster, cp->regs + REG_PLUS_RX_KICK1); in cas_post_rxds_ringN()
2233 * NOTE: RX page posting is done in this routine as well. while there's
2234 * the capability of using multiple RX completion rings, it isn't
2240 struct cas_rx_comp *rxcs = cp->init_rxcs[ring]; in cas_rx_ringN()
2244 netif_printk(cp, intr, KERN_DEBUG, cp->dev, in cas_rx_ringN()
2245 "rx[%d] interrupt, done: %d/%d\n", in cas_rx_ringN()
2247 readl(cp->regs + REG_RX_COMP_HEAD), cp->rx_new[ring]); in cas_rx_ringN()
2249 entry = cp->rx_new[ring]; in cas_rx_ringN()
2258 words[0] = le64_to_cpu(rxc->word1); in cas_rx_ringN()
2259 words[1] = le64_to_cpu(rxc->word2); in cas_rx_ringN()
2260 words[2] = le64_to_cpu(rxc->word3); in cas_rx_ringN()
2261 words[3] = le64_to_cpu(rxc->word4); in cas_rx_ringN()
2275 spin_lock(&cp->stat_lock[ring]); in cas_rx_ringN()
2276 cp->net_stats[ring].rx_errors++; in cas_rx_ringN()
2278 cp->net_stats[ring].rx_length_errors++; in cas_rx_ringN()
2280 cp->net_stats[ring].rx_crc_errors++; in cas_rx_ringN()
2281 spin_unlock(&cp->stat_lock[ring]); in cas_rx_ringN()
2285 spin_lock(&cp->stat_lock[ring]); in cas_rx_ringN()
2286 ++cp->net_stats[ring].rx_dropped; in cas_rx_ringN()
2287 spin_unlock(&cp->stat_lock[ring]); in cas_rx_ringN()
2297 /* see if it's a flow re-assembly or not. the driver in cas_rx_ringN()
2301 /* non-reassm: these always get released */ in cas_rx_ringN()
2307 spin_lock(&cp->stat_lock[ring]); in cas_rx_ringN()
2308 cp->net_stats[ring].rx_packets++; in cas_rx_ringN()
2309 cp->net_stats[ring].rx_bytes += len; in cas_rx_ringN()
2310 spin_unlock(&cp->stat_lock[ring]); in cas_rx_ringN()
2345 cp->rx_new[ring] = entry; in cas_rx_ringN()
2348 netdev_info(cp->dev, "Memory squeeze, deferring packet\n"); in cas_rx_ringN()
2357 struct cas_rx_comp *rxc = cp->init_rxcs[ring]; in cas_post_rxcs_ringN()
2360 last = cp->rx_cur[ring]; in cas_post_rxcs_ringN()
2361 entry = cp->rx_new[ring]; in cas_post_rxcs_ringN()
2364 ring, readl(cp->regs + REG_RX_COMP_HEAD), entry); in cas_post_rxcs_ringN()
2366 /* zero and re-mark descriptors */ in cas_post_rxcs_ringN()
2371 cp->rx_cur[ring] = last; in cas_post_rxcs_ringN()
2374 writel(last, cp->regs + REG_RX_COMP_TAIL); in cas_post_rxcs_ringN()
2375 else if (cp->cas_flags & CAS_FLAG_REG_PLUS) in cas_post_rxcs_ringN()
2376 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring)); in cas_post_rxcs_ringN()
2398 int ring = (irq == cp->pci_irq_INTC) ? 2 : 3; in cas_interruptN()
2399 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring)); in cas_interruptN()
2405 spin_lock_irqsave(&cp->lock, flags); in cas_interruptN()
2406 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */ in cas_interruptN()
2409 napi_schedule(&cp->napi); in cas_interruptN()
2418 spin_unlock_irqrestore(&cp->lock, flags); in cas_interruptN()
2424 /* everything but rx packets */
2428 /* Frame arrived, no free RX buffers available. in cas_handle_irq1()
2431 spin_lock(&cp->stat_lock[1]); in cas_handle_irq1()
2432 cp->net_stats[1].rx_dropped++; in cas_handle_irq1()
2433 spin_unlock(&cp->stat_lock[1]); in cas_handle_irq1()
2437 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) - in cas_handle_irq1()
2450 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1)); in cas_interrupt1()
2456 spin_lock_irqsave(&cp->lock, flags); in cas_interrupt1()
2457 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */ in cas_interrupt1()
2460 napi_schedule(&cp->napi); in cas_interrupt1()
2468 spin_unlock_irqrestore(&cp->lock, flags); in cas_interrupt1()
2481 /* Frame arrived, no free RX buffers available. in cas_handle_irq()
2485 spin_lock(&cp->stat_lock[0]); in cas_handle_irq()
2486 cp->net_stats[0].rx_dropped++; in cas_handle_irq()
2487 spin_unlock(&cp->stat_lock[0]); in cas_handle_irq()
2489 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) - in cas_handle_irq()
2502 u32 status = readl(cp->regs + REG_INTR_STATUS); in cas_interrupt()
2507 spin_lock_irqsave(&cp->lock, flags); in cas_interrupt()
2516 napi_schedule(&cp->napi); in cas_interrupt()
2525 spin_unlock_irqrestore(&cp->lock, flags); in cas_interrupt()
2534 struct net_device *dev = cp->dev; in cas_poll()
2536 u32 status = readl(cp->regs + REG_INTR_STATUS); in cas_poll()
2539 spin_lock_irqsave(&cp->lock, flags); in cas_poll()
2541 spin_unlock_irqrestore(&cp->lock, flags); in cas_poll()
2543 /* NAPI rx packets. we spread the credits across all of the in cas_poll()
2564 /* final rx completion */ in cas_poll()
2565 spin_lock_irqsave(&cp->lock, flags); in cas_poll()
2571 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1)); in cas_poll()
2579 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2)); in cas_poll()
2587 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3)); in cas_poll()
2592 spin_unlock_irqrestore(&cp->lock, flags); in cas_poll()
2607 cas_interrupt(cp->pdev->irq, dev); in cas_netpoll()
2633 if (!cp->hw_running) { in cas_tx_timeout()
2639 readl(cp->regs + REG_MIF_STATE_MACHINE)); in cas_tx_timeout()
2642 readl(cp->regs + REG_MAC_STATE_MACHINE)); in cas_tx_timeout()
2645 readl(cp->regs + REG_TX_CFG), in cas_tx_timeout()
2646 readl(cp->regs + REG_MAC_TX_STATUS), in cas_tx_timeout()
2647 readl(cp->regs + REG_MAC_TX_CFG), in cas_tx_timeout()
2648 readl(cp->regs + REG_TX_FIFO_PKT_CNT), in cas_tx_timeout()
2649 readl(cp->regs + REG_TX_FIFO_WRITE_PTR), in cas_tx_timeout()
2650 readl(cp->regs + REG_TX_FIFO_READ_PTR), in cas_tx_timeout()
2651 readl(cp->regs + REG_TX_SM_1), in cas_tx_timeout()
2652 readl(cp->regs + REG_TX_SM_2)); in cas_tx_timeout()
2655 readl(cp->regs + REG_RX_CFG), in cas_tx_timeout()
2656 readl(cp->regs + REG_MAC_RX_STATUS), in cas_tx_timeout()
2657 readl(cp->regs + REG_MAC_RX_CFG)); in cas_tx_timeout()
2660 readl(cp->regs + REG_HP_STATE_MACHINE), in cas_tx_timeout()
2661 readl(cp->regs + REG_HP_STATUS0), in cas_tx_timeout()
2662 readl(cp->regs + REG_HP_STATUS1), in cas_tx_timeout()
2663 readl(cp->regs + REG_HP_STATUS2)); in cas_tx_timeout()
2666 atomic_inc(&cp->reset_task_pending); in cas_tx_timeout()
2667 atomic_inc(&cp->reset_task_pending_all); in cas_tx_timeout()
2668 schedule_work(&cp->reset_task); in cas_tx_timeout()
2670 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL); in cas_tx_timeout()
2671 schedule_work(&cp->reset_task); in cas_tx_timeout()
2678 if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1))) in cas_intme()
2687 struct cas_tx_desc *txd = cp->init_txds[ring] + entry; in cas_write_txd()
2694 txd->control = cpu_to_le64(ctrl); in cas_write_txd()
2695 txd->buffer = cpu_to_le64(mapping); in cas_write_txd()
2701 return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry; in tx_tiny_buf()
2707 cp->tx_tiny_use[ring][tentry].nbufs++; in tx_tiny_map()
2708 cp->tx_tiny_use[ring][entry].used = 1; in tx_tiny_map()
2709 return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry; in tx_tiny_map()
2715 struct net_device *dev = cp->dev; in cas_xmit_tx_ringN()
2722 spin_lock_irqsave(&cp->tx_lock[ring], flags); in cas_xmit_tx_ringN()
2726 CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) { in cas_xmit_tx_ringN()
2728 spin_unlock_irqrestore(&cp->tx_lock[ring], flags); in cas_xmit_tx_ringN()
2734 if (skb->ip_summed == CHECKSUM_PARTIAL) { in cas_xmit_tx_ringN()
2736 const u64 csum_stuff_off = csum_start_off + skb->csum_offset; in cas_xmit_tx_ringN()
2743 entry = cp->tx_new[ring]; in cas_xmit_tx_ringN()
2744 cp->tx_skbs[ring][entry] = skb; in cas_xmit_tx_ringN()
2746 nr_frags = skb_shinfo(skb)->nr_frags; in cas_xmit_tx_ringN()
2748 mapping = dma_map_page(&cp->pdev->dev, virt_to_page(skb->data), in cas_xmit_tx_ringN()
2749 offset_in_page(skb->data), len, DMA_TO_DEVICE); in cas_xmit_tx_ringN()
2752 tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len); in cas_xmit_tx_ringN()
2755 cas_write_txd(cp, ring, entry, mapping, len - tabort, in cas_xmit_tx_ringN()
2759 skb_copy_from_linear_data_offset(skb, len - tabort, in cas_xmit_tx_ringN()
2771 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; in cas_xmit_tx_ringN()
2774 mapping = skb_frag_dma_map(&cp->pdev->dev, fragp, 0, len, in cas_xmit_tx_ringN()
2780 cas_write_txd(cp, ring, entry, mapping, len - tabort, in cas_xmit_tx_ringN()
2785 skb_frag_off(fragp) + len - tabort, in cas_xmit_tx_ringN()
2796 cp->tx_new[ring] = entry; in cas_xmit_tx_ringN()
2802 ring, entry, skb->len, TX_BUFFS_AVAIL(cp, ring)); in cas_xmit_tx_ringN()
2803 writel(entry, cp->regs + REG_TX_KICKN(ring)); in cas_xmit_tx_ringN()
2804 spin_unlock_irqrestore(&cp->tx_lock[ring], flags); in cas_xmit_tx_ringN()
2812 /* this is only used as a load-balancing hint, so it doesn't in cas_start_xmit()
2817 if (skb_padto(skb, cp->min_frame_size)) in cas_start_xmit()
2820 /* XXX: we need some higher-level QoS hooks to steer packets to in cas_start_xmit()
2830 u64 desc_dma = cp->block_dvma; in cas_init_tx_dma()
2835 /* set up tx completion writeback registers. must be 8-byte aligned */ in cas_init_tx_dma()
2838 writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI); in cas_init_tx_dma()
2839 writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW); in cas_init_tx_dma()
2843 * disable read pipe, and disable pre-interrupt compwbs in cas_init_tx_dma()
2852 off = (unsigned long) cp->init_txds[i] - in cas_init_tx_dma()
2853 (unsigned long) cp->init_block; in cas_init_tx_dma()
2856 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i)); in cas_init_tx_dma()
2857 writel((desc_dma + off) & 0xffffffff, cp->regs + in cas_init_tx_dma()
2863 writel(val, cp->regs + REG_TX_CFG); in cas_init_tx_dma()
2869 writel(0x800, cp->regs + REG_TX_MAXBURST_0); in cas_init_tx_dma()
2870 writel(0x1600, cp->regs + REG_TX_MAXBURST_1); in cas_init_tx_dma()
2871 writel(0x2400, cp->regs + REG_TX_MAXBURST_2); in cas_init_tx_dma()
2872 writel(0x4800, cp->regs + REG_TX_MAXBURST_3); in cas_init_tx_dma()
2874 writel(0x800, cp->regs + REG_TX_MAXBURST_0); in cas_init_tx_dma()
2875 writel(0x800, cp->regs + REG_TX_MAXBURST_1); in cas_init_tx_dma()
2876 writel(0x800, cp->regs + REG_TX_MAXBURST_2); in cas_init_tx_dma()
2877 writel(0x800, cp->regs + REG_TX_MAXBURST_3); in cas_init_tx_dma()
2881 /* Must be invoked under cp->lock. */
2896 netdev_for_each_mc_addr(ha, cp->dev) { in cas_process_mc_list()
2901 writel((ha->addr[4] << 8) | ha->addr[5], in cas_process_mc_list()
2902 cp->regs + REG_MAC_ADDRN(i*3 + 0)); in cas_process_mc_list()
2903 writel((ha->addr[2] << 8) | ha->addr[3], in cas_process_mc_list()
2904 cp->regs + REG_MAC_ADDRN(i*3 + 1)); in cas_process_mc_list()
2905 writel((ha->addr[0] << 8) | ha->addr[1], in cas_process_mc_list()
2906 cp->regs + REG_MAC_ADDRN(i*3 + 2)); in cas_process_mc_list()
2913 crc = ether_crc_le(ETH_ALEN, ha->addr); in cas_process_mc_list()
2915 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf)); in cas_process_mc_list()
2919 writel(hash_table[i], cp->regs + REG_MAC_HASH_TABLEN(i)); in cas_process_mc_list()
2922 /* Must be invoked under cp->lock. */
2928 if (cp->dev->flags & IFF_PROMISC) { in cas_setup_multicast()
2931 } else if (cp->dev->flags & IFF_ALLMULTI) { in cas_setup_multicast()
2933 writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i)); in cas_setup_multicast()
2944 /* must be invoked under cp->stat_lock[N_TX_RINGS] */
2947 writel(0, cp->regs + REG_MAC_COLL_NORMAL); in cas_clear_mac_err()
2948 writel(0, cp->regs + REG_MAC_COLL_FIRST); in cas_clear_mac_err()
2949 writel(0, cp->regs + REG_MAC_COLL_EXCESS); in cas_clear_mac_err()
2950 writel(0, cp->regs + REG_MAC_COLL_LATE); in cas_clear_mac_err()
2951 writel(0, cp->regs + REG_MAC_TIMER_DEFER); in cas_clear_mac_err()
2952 writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK); in cas_clear_mac_err()
2953 writel(0, cp->regs + REG_MAC_RECV_FRAME); in cas_clear_mac_err()
2954 writel(0, cp->regs + REG_MAC_LEN_ERR); in cas_clear_mac_err()
2955 writel(0, cp->regs + REG_MAC_ALIGN_ERR); in cas_clear_mac_err()
2956 writel(0, cp->regs + REG_MAC_FCS_ERR); in cas_clear_mac_err()
2957 writel(0, cp->regs + REG_MAC_RX_CODE_ERR); in cas_clear_mac_err()
2965 /* do both TX and RX reset */ in cas_mac_reset()
2966 writel(0x1, cp->regs + REG_MAC_TX_RESET); in cas_mac_reset()
2967 writel(0x1, cp->regs + REG_MAC_RX_RESET); in cas_mac_reset()
2971 while (i-- > 0) { in cas_mac_reset()
2972 if (readl(cp->regs + REG_MAC_TX_RESET) == 0) in cas_mac_reset()
2977 /* wait for RX */ in cas_mac_reset()
2979 while (i-- > 0) { in cas_mac_reset()
2980 if (readl(cp->regs + REG_MAC_RX_RESET) == 0) in cas_mac_reset()
2985 if (readl(cp->regs + REG_MAC_TX_RESET) | in cas_mac_reset()
2986 readl(cp->regs + REG_MAC_RX_RESET)) in cas_mac_reset()
2987 netdev_err(cp->dev, "mac tx[%d]/rx[%d] reset failed [%08x]\n", in cas_mac_reset()
2988 readl(cp->regs + REG_MAC_TX_RESET), in cas_mac_reset()
2989 readl(cp->regs + REG_MAC_RX_RESET), in cas_mac_reset()
2990 readl(cp->regs + REG_MAC_STATE_MACHINE)); in cas_mac_reset()
2994 /* Must be invoked under cp->lock. */
2997 const unsigned char *e = &cp->dev->dev_addr[0]; in cas_init_mac()
3002 writel(CAWR_RR_DIS, cp->regs + REG_CAWR); in cas_init_mac()
3008 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0) in cas_init_mac()
3009 writel(INF_BURST_EN, cp->regs + REG_INF_BURST); in cas_init_mac()
3012 writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE); in cas_init_mac()
3014 writel(0x00, cp->regs + REG_MAC_IPG0); in cas_init_mac()
3015 writel(0x08, cp->regs + REG_MAC_IPG1); in cas_init_mac()
3016 writel(0x04, cp->regs + REG_MAC_IPG2); in cas_init_mac()
3019 writel(0x40, cp->regs + REG_MAC_SLOT_TIME); in cas_init_mac()
3022 writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN); in cas_init_mac()
3025 * specify the maximum frame size to prevent RX tag errors on in cas_init_mac()
3031 cp->regs + REG_MAC_FRAMESIZE_MAX); in cas_init_mac()
3033 /* NOTE: crc_size is used as a surrogate for half-duplex. in cas_init_mac()
3034 * workaround saturn half-duplex issue by increasing preamble in cas_init_mac()
3037 if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size) in cas_init_mac()
3038 writel(0x41, cp->regs + REG_MAC_PA_SIZE); in cas_init_mac()
3040 writel(0x07, cp->regs + REG_MAC_PA_SIZE); in cas_init_mac()
3041 writel(0x04, cp->regs + REG_MAC_JAM_SIZE); in cas_init_mac()
3042 writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT); in cas_init_mac()
3043 writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE); in cas_init_mac()
3045 writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED); in cas_init_mac()
3047 writel(0, cp->regs + REG_MAC_ADDR_FILTER0); in cas_init_mac()
3048 writel(0, cp->regs + REG_MAC_ADDR_FILTER1); in cas_init_mac()
3049 writel(0, cp->regs + REG_MAC_ADDR_FILTER2); in cas_init_mac()
3050 writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK); in cas_init_mac()
3051 writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK); in cas_init_mac()
3055 writel(0x0, cp->regs + REG_MAC_ADDRN(i)); in cas_init_mac()
3057 writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0)); in cas_init_mac()
3058 writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1)); in cas_init_mac()
3059 writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2)); in cas_init_mac()
3061 writel(0x0001, cp->regs + REG_MAC_ADDRN(42)); in cas_init_mac()
3062 writel(0xc200, cp->regs + REG_MAC_ADDRN(43)); in cas_init_mac()
3063 writel(0x0180, cp->regs + REG_MAC_ADDRN(44)); in cas_init_mac()
3065 cp->mac_rx_cfg = cas_setup_multicast(cp); in cas_init_mac()
3067 spin_lock(&cp->stat_lock[N_TX_RINGS]); in cas_init_mac()
3069 spin_unlock(&cp->stat_lock[N_TX_RINGS]); in cas_init_mac()
3073 * normal rx/tx as the DMA engine tells us that. in cas_init_mac()
3075 writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK); in cas_init_mac()
3076 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK); in cas_init_mac()
3081 writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK); in cas_init_mac()
3084 /* Must be invoked under cp->lock. */
3088 * full RX fifo size effectively disables PAUSE generation in cas_init_pause_thresholds()
3090 if (cp->rx_fifo_size <= (2 * 1024)) { in cas_init_pause_thresholds()
3091 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size; in cas_init_pause_thresholds()
3093 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63; in cas_init_pause_thresholds()
3094 if (max_frame * 3 > cp->rx_fifo_size) { in cas_init_pause_thresholds()
3095 cp->rx_pause_off = 7104; in cas_init_pause_thresholds()
3096 cp->rx_pause_on = 960; in cas_init_pause_thresholds()
3098 int off = (cp->rx_fifo_size - (max_frame * 2)); in cas_init_pause_thresholds()
3099 int on = off - max_frame; in cas_init_pause_thresholds()
3100 cp->rx_pause_off = off; in cas_init_pause_thresholds()
3101 cp->rx_pause_on = on; in cas_init_pause_thresholds()
3122 * 1) vpd info has order-dependent mac addresses for multinic cards
3133 void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START; in cas_get_vpd_info()
3149 cp->regs + REG_BIM_LOCAL_DEV_EN); in cas_get_vpd_info()
3183 while ((p - kstart) < len) { in cas_get_vpd_info()
3191 * -- correct length == 29 in cas_get_vpd_info()
3193 * 18 (strlen("local-mac-address") + 1) + in cas_get_vpd_info()
3195 * -- VPD Instance 'I' in cas_get_vpd_info()
3196 * -- VPD Type Bytes 'B' in cas_get_vpd_info()
3197 * -- VPD data length == 6 in cas_get_vpd_info()
3198 * -- property string == local-mac-address in cas_get_vpd_info()
3200 * -- correct length == 24 in cas_get_vpd_info()
3202 * 12 (strlen("entropy-dev") + 1) + in cas_get_vpd_info()
3204 * -- VPD Instance 'I' in cas_get_vpd_info()
3205 * -- VPD Type String 'B' in cas_get_vpd_info()
3206 * -- VPD data length == 7 in cas_get_vpd_info()
3207 * -- property string == entropy-dev in cas_get_vpd_info()
3209 * -- correct length == 18 in cas_get_vpd_info()
3211 * 9 (strlen("phy-type") + 1) + in cas_get_vpd_info()
3212 * 4 (strlen("pcs") + 1) in cas_get_vpd_info()
3213 * -- VPD Instance 'I' in cas_get_vpd_info()
3214 * -- VPD Type String 'S' in cas_get_vpd_info()
3215 * -- VPD data length == 4 in cas_get_vpd_info()
3216 * -- property string == phy-type in cas_get_vpd_info()
3218 * -- correct length == 23 in cas_get_vpd_info()
3220 * 14 (strlen("phy-interface") + 1) + in cas_get_vpd_info()
3221 * 4 (strlen("pcs") + 1) in cas_get_vpd_info()
3222 * -- VPD Instance 'I' in cas_get_vpd_info()
3223 * -- VPD Type String 'S' in cas_get_vpd_info()
3224 * -- VPD data length == 4 in cas_get_vpd_info()
3225 * -- property string == phy-interface in cas_get_vpd_info()
3235 "local-mac-address")) { in cas_get_vpd_info()
3252 cas_vpd_match(p + 5, "entropy-dev") && in cas_get_vpd_info()
3254 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV; in cas_get_vpd_info()
3263 cas_vpd_match(p + 5, "phy-type")) { in cas_get_vpd_info()
3264 if (cas_vpd_match(p + 14, "pcs")) { in cas_get_vpd_info()
3271 cas_vpd_match(p + 5, "phy-interface")) { in cas_get_vpd_info()
3272 if (cas_vpd_match(p + 19, "pcs")) { in cas_get_vpd_info()
3295 addr = of_get_property(cp->of_node, "local-mac-address", NULL); in cas_get_vpd_info()
3310 writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN); in cas_get_vpd_info()
3317 struct pci_dev *pdev = cp->pdev; in cas_check_pci_invariants()
3319 cp->cas_flags = 0; in cas_check_pci_invariants()
3320 if ((pdev->vendor == PCI_VENDOR_ID_SUN) && in cas_check_pci_invariants()
3321 (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) { in cas_check_pci_invariants()
3322 if (pdev->revision >= CAS_ID_REVPLUS) in cas_check_pci_invariants()
3323 cp->cas_flags |= CAS_FLAG_REG_PLUS; in cas_check_pci_invariants()
3324 if (pdev->revision < CAS_ID_REVPLUS02u) in cas_check_pci_invariants()
3325 cp->cas_flags |= CAS_FLAG_TARGET_ABORT; in cas_check_pci_invariants()
3330 if (pdev->revision < CAS_ID_REV2) in cas_check_pci_invariants()
3331 cp->cas_flags |= CAS_FLAG_NO_HW_CSUM; in cas_check_pci_invariants()
3334 cp->cas_flags |= CAS_FLAG_REG_PLUS; in cas_check_pci_invariants()
3339 if ((pdev->vendor == PCI_VENDOR_ID_NS) && in cas_check_pci_invariants()
3340 (pdev->device == PCI_DEVICE_ID_NS_SATURN)) in cas_check_pci_invariants()
3341 cp->cas_flags |= CAS_FLAG_SATURN; in cas_check_pci_invariants()
3348 struct pci_dev *pdev = cp->pdev; in cas_check_invariants()
3353 /* get page size for rx buffers. */ in cas_check_invariants()
3354 cp->page_order = 0; in cas_check_invariants()
3359 CAS_JUMBO_PAGE_SHIFT - in cas_check_invariants()
3362 __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT); in cas_check_invariants()
3363 cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT; in cas_check_invariants()
3369 cp->page_size = (PAGE_SIZE << cp->page_order); in cas_check_invariants()
3372 cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64; in cas_check_invariants()
3373 cp->rx_fifo_size = RX_FIFO_SIZE; in cas_check_invariants()
3378 cp->phy_type = cas_get_vpd_info(cp, addr, PCI_SLOT(pdev->devfn)); in cas_check_invariants()
3379 eth_hw_addr_set(cp->dev, addr); in cas_check_invariants()
3380 if (cp->phy_type & CAS_PHY_SERDES) { in cas_check_invariants()
3381 cp->cas_flags |= CAS_FLAG_1000MB_CAP; in cas_check_invariants()
3386 cfg = readl(cp->regs + REG_MIF_CFG); in cas_check_invariants()
3388 cp->phy_type = CAS_PHY_MII_MDIO1; in cas_check_invariants()
3390 cp->phy_type = CAS_PHY_MII_MDIO0; in cas_check_invariants()
3394 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE); in cas_check_invariants()
3401 cp->phy_addr = i; in cas_check_invariants()
3405 cp->phy_id = phy_id; in cas_check_invariants()
3411 readl(cp->regs + REG_MIF_STATE_MACHINE)); in cas_check_invariants()
3412 return -1; in cas_check_invariants()
3419 cp->cas_flags |= CAS_FLAG_1000MB_CAP; in cas_check_invariants()
3423 /* Must be invoked under cp->lock. */
3431 val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN; in cas_start_dma()
3432 writel(val, cp->regs + REG_TX_CFG); in cas_start_dma()
3433 val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN; in cas_start_dma()
3434 writel(val, cp->regs + REG_RX_CFG); in cas_start_dma()
3437 val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN; in cas_start_dma()
3438 writel(val, cp->regs + REG_MAC_TX_CFG); in cas_start_dma()
3439 val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN; in cas_start_dma()
3440 writel(val, cp->regs + REG_MAC_RX_CFG); in cas_start_dma()
3443 while (i-- > 0) { in cas_start_dma()
3444 val = readl(cp->regs + REG_MAC_TX_CFG); in cas_start_dma()
3451 while (i-- > 0) { in cas_start_dma()
3452 val = readl(cp->regs + REG_MAC_RX_CFG); in cas_start_dma()
3455 netdev_err(cp->dev, in cas_start_dma()
3457 readl(cp->regs + REG_MIF_STATE_MACHINE), in cas_start_dma()
3458 readl(cp->regs + REG_MAC_STATE_MACHINE)); in cas_start_dma()
3464 netdev_err(cp->dev, "enabling mac failed [%s:%08x:%08x]\n", in cas_start_dma()
3465 (txfailed ? "tx,rx" : "rx"), in cas_start_dma()
3466 readl(cp->regs + REG_MIF_STATE_MACHINE), in cas_start_dma()
3467 readl(cp->regs + REG_MAC_STATE_MACHINE)); in cas_start_dma()
3471 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK); in cas_start_dma()
3472 writel(0, cp->regs + REG_RX_COMP_TAIL); in cas_start_dma()
3474 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { in cas_start_dma()
3476 writel(RX_DESC_RINGN_SIZE(1) - 4, in cas_start_dma()
3477 cp->regs + REG_PLUS_RX_KICK1); in cas_start_dma()
3481 /* Must be invoked under cp->lock. */
3485 u32 val = readl(cp->regs + REG_PCS_MII_LPA); in cas_read_pcs_link_mode()
3493 /* Must be invoked under cp->lock. */
3516 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) { in cas_read_mii_link_mode()
3525 /* A link-up condition has occurred, initialize and enable the
3528 * Must be invoked under cp->lock.
3539 if (CAS_PHY_MII(cp->phy_type)) { in cas_set_link_modes()
3552 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ? in cas_set_link_modes()
3558 val = readl(cp->regs + REG_PCS_MII_CTRL); in cas_set_link_modes()
3566 netif_info(cp, link, cp->dev, "Link up at %d Mbps, %s-duplex\n", in cas_set_link_modes()
3570 if (CAS_PHY_MII(cp->phy_type)) { in cas_set_link_modes()
3579 writel(val, cp->regs + REG_MAC_XIF_CFG); in cas_set_link_modes()
3594 /* If gigabit and half-duplex, enable carrier extension in cas_set_link_modes()
3601 cp->regs + REG_MAC_TX_CFG); in cas_set_link_modes()
3603 val = readl(cp->regs + REG_MAC_RX_CFG); in cas_set_link_modes()
3606 cp->regs + REG_MAC_RX_CFG); in cas_set_link_modes()
3608 writel(0x200, cp->regs + REG_MAC_SLOT_TIME); in cas_set_link_modes()
3610 cp->crc_size = 4; in cas_set_link_modes()
3612 cp->min_frame_size = CAS_1000MB_MIN_FRAME; in cas_set_link_modes()
3615 writel(val, cp->regs + REG_MAC_TX_CFG); in cas_set_link_modes()
3618 * half-duplex mode in cas_set_link_modes()
3620 val = readl(cp->regs + REG_MAC_RX_CFG); in cas_set_link_modes()
3623 cp->crc_size = 0; in cas_set_link_modes()
3624 cp->min_frame_size = CAS_MIN_MTU; in cas_set_link_modes()
3627 cp->crc_size = 4; in cas_set_link_modes()
3628 cp->min_frame_size = CAS_MIN_FRAME; in cas_set_link_modes()
3631 cp->regs + REG_MAC_RX_CFG); in cas_set_link_modes()
3632 writel(0x40, cp->regs + REG_MAC_SLOT_TIME); in cas_set_link_modes()
3637 netdev_info(cp->dev, "Pause is enabled (rxfifo: %d off: %d on: %d)\n", in cas_set_link_modes()
3638 cp->rx_fifo_size, in cas_set_link_modes()
3639 cp->rx_pause_off, in cas_set_link_modes()
3640 cp->rx_pause_on); in cas_set_link_modes()
3642 netdev_info(cp->dev, "TX pause enabled\n"); in cas_set_link_modes()
3644 netdev_info(cp->dev, "Pause is disabled\n"); in cas_set_link_modes()
3648 val = readl(cp->regs + REG_MAC_CTRL_CFG); in cas_set_link_modes()
3656 writel(val, cp->regs + REG_MAC_CTRL_CFG); in cas_set_link_modes()
3660 /* Must be invoked under cp->lock. */
3672 cp->timer_ticks = 0; in cas_init_hw()
3674 } else if (cp->lstate == link_up) { in cas_init_hw()
3676 netif_carrier_on(cp->dev); in cas_init_hw()
3680 /* Must be invoked under cp->lock. on earlier cassini boards,
3686 writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN); in cas_hard_reset()
3688 pci_restore_state(cp->pdev); in cas_hard_reset()
3697 if (blkflag && !CAS_PHY_MII(cp->phy_type)) { in cas_global_reset()
3698 /* For PCS, when the blkflag is set, we should set the in cas_global_reset()
3705 cp->regs + REG_SW_RESET); in cas_global_reset()
3707 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET); in cas_global_reset()
3714 while (limit-- > 0) { in cas_global_reset()
3715 u32 val = readl(cp->regs + REG_SW_RESET); in cas_global_reset()
3720 netdev_err(cp->dev, "sw reset failed\n"); in cas_global_reset()
3725 BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG); in cas_global_reset()
3733 PCI_ERR_BIM_DMA_READ), cp->regs + in cas_global_reset()
3736 /* set up for MII by default to address mac rx reset timeout in cas_global_reset()
3739 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE); in cas_global_reset()
3752 val = readl(cp->regs + REG_TX_CFG); in cas_reset()
3754 writel(val, cp->regs + REG_TX_CFG); in cas_reset()
3756 val = readl(cp->regs + REG_RX_CFG); in cas_reset()
3758 writel(val, cp->regs + REG_RX_CFG); in cas_reset()
3761 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) || in cas_reset()
3769 spin_lock(&cp->stat_lock[N_TX_RINGS]); in cas_reset()
3771 spin_unlock(&cp->stat_lock[N_TX_RINGS]); in cas_reset()
3779 /* Make us not-running to avoid timers respawning */ in cas_shutdown()
3780 cp->hw_running = 0; in cas_shutdown()
3782 del_timer_sync(&cp->link_timer); in cas_shutdown()
3786 while (atomic_read(&cp->reset_task_pending_mtu) || in cas_shutdown()
3787 atomic_read(&cp->reset_task_pending_spare) || in cas_shutdown()
3788 atomic_read(&cp->reset_task_pending_all)) in cas_shutdown()
3792 while (atomic_read(&cp->reset_task_pending)) in cas_shutdown()
3798 if (cp->cas_flags & CAS_FLAG_SATURN) in cas_shutdown()
3807 WRITE_ONCE(dev->mtu, new_mtu); in cas_change_mtu()
3813 atomic_inc(&cp->reset_task_pending); in cas_change_mtu()
3814 if ((cp->phy_type & CAS_PHY_SERDES)) { in cas_change_mtu()
3815 atomic_inc(&cp->reset_task_pending_all); in cas_change_mtu()
3817 atomic_inc(&cp->reset_task_pending_mtu); in cas_change_mtu()
3819 schedule_work(&cp->reset_task); in cas_change_mtu()
3821 atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ? in cas_change_mtu()
3824 schedule_work(&cp->reset_task); in cas_change_mtu()
3827 flush_work(&cp->reset_task); in cas_change_mtu()
3833 struct cas_tx_desc *txd = cp->init_txds[ring]; in cas_clean_txd()
3834 struct sk_buff *skb, **skbs = cp->tx_skbs[ring]; in cas_clean_txd()
3848 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { in cas_clean_txd()
3849 int ent = i & (size - 1); in cas_clean_txd()
3857 dma_unmap_page(&cp->pdev->dev, daddr, dlen, in cas_clean_txd()
3860 if (frag != skb_shinfo(skb)->nr_frags) { in cas_clean_txd()
3866 ent = i & (size - 1); in cas_clean_txd()
3867 if (cp->tx_tiny_use[ring][ent].used) in cas_clean_txd()
3875 memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring])); in cas_clean_txd()
3881 cas_page_t **page = cp->rx_pages[ring]; in cas_free_rx_desc()
3901 /* Must be invoked under cp->lock. */
3907 memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS); in cas_clean_rings()
3908 memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS); in cas_clean_rings()
3913 memset(cp->init_block, 0, sizeof(struct cas_init_block)); in cas_clean_rings()
3921 cas_page_t **page = cp->rx_pages[ring]; in cas_alloc_rx_desc()
3927 return -1; in cas_alloc_rx_desc()
3939 return -1; in cas_alloc_rxds()
3949 int pending = atomic_read(&cp->reset_task_pending); in cas_reset_task()
3951 int pending_all = atomic_read(&cp->reset_task_pending_all); in cas_reset_task()
3952 int pending_spare = atomic_read(&cp->reset_task_pending_spare); in cas_reset_task()
3953 int pending_mtu = atomic_read(&cp->reset_task_pending_mtu); in cas_reset_task()
3959 atomic_dec(&cp->reset_task_pending); in cas_reset_task()
3967 if (cp->hw_running) { in cas_reset_task()
3971 netif_device_detach(cp->dev); in cas_reset_task()
3974 if (cp->opened) { in cas_reset_task()
3994 * PCS case) when auto negotiation is not restarted. in cas_reset_task()
3998 if (cp->opened) in cas_reset_task()
4003 if (cp->opened) in cas_reset_task()
4010 netif_device_attach(cp->dev); in cas_reset_task()
4013 atomic_sub(pending_all, &cp->reset_task_pending_all); in cas_reset_task()
4014 atomic_sub(pending_spare, &cp->reset_task_pending_spare); in cas_reset_task()
4015 atomic_sub(pending_mtu, &cp->reset_task_pending_mtu); in cas_reset_task()
4016 atomic_dec(&cp->reset_task_pending); in cas_reset_task()
4018 atomic_set(&cp->reset_task_pending, 0); in cas_reset_task()
4029 cp->link_transition_jiffies_valid && in cas_link_timer()
4030 time_is_before_jiffies(cp->link_transition_jiffies + in cas_link_timer()
4032 /* One-second counter so link-down workaround doesn't in cas_link_timer()
4036 cp->link_transition_jiffies_valid = 0; in cas_link_timer()
4039 if (!cp->hw_running) in cas_link_timer()
4042 spin_lock_irqsave(&cp->lock, flags); in cas_link_timer()
4050 if (atomic_read(&cp->reset_task_pending_all) || in cas_link_timer()
4051 atomic_read(&cp->reset_task_pending_spare) || in cas_link_timer()
4052 atomic_read(&cp->reset_task_pending_mtu)) in cas_link_timer()
4055 if (atomic_read(&cp->reset_task_pending)) in cas_link_timer()
4059 /* check for rx cleaning */ in cas_link_timer()
4060 if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) { in cas_link_timer()
4069 if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) { in cas_link_timer()
4073 cp->cas_flags &= ~rmask; in cas_link_timer()
4077 if (CAS_PHY_MII(cp->phy_type)) { in cas_link_timer()
4082 * may be due to the PCS case and the use of a in cas_link_timer()
4088 readl(cp->regs + REG_MIF_STATUS); /* avoid dups */ in cas_link_timer()
4098 if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) { in cas_link_timer()
4099 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE); in cas_link_timer()
4105 netif_printk(cp, tx_err, KERN_DEBUG, cp->dev, in cas_link_timer()
4111 val = readl(cp->regs + REG_TX_FIFO_PKT_CNT); in cas_link_timer()
4112 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR); in cas_link_timer()
4113 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR); in cas_link_timer()
4115 netif_printk(cp, tx_err, KERN_DEBUG, cp->dev, in cas_link_timer()
4128 atomic_inc(&cp->reset_task_pending); in cas_link_timer()
4129 atomic_inc(&cp->reset_task_pending_all); in cas_link_timer()
4130 schedule_work(&cp->reset_task); in cas_link_timer()
4132 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL); in cas_link_timer()
4134 schedule_work(&cp->reset_task); in cas_link_timer()
4139 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT); in cas_link_timer()
4141 spin_unlock_irqrestore(&cp->lock, flags); in cas_link_timer()
4149 struct pci_dev *pdev = cp->pdev; in cas_tx_tiny_free()
4153 if (!cp->tx_tiny_bufs[i]) in cas_tx_tiny_free()
4156 dma_free_coherent(&pdev->dev, TX_TINY_BUF_BLOCK, in cas_tx_tiny_free()
4157 cp->tx_tiny_bufs[i], cp->tx_tiny_dvma[i]); in cas_tx_tiny_free()
4158 cp->tx_tiny_bufs[i] = NULL; in cas_tx_tiny_free()
4164 struct pci_dev *pdev = cp->pdev; in cas_tx_tiny_alloc()
4168 cp->tx_tiny_bufs[i] = in cas_tx_tiny_alloc()
4169 dma_alloc_coherent(&pdev->dev, TX_TINY_BUF_BLOCK, in cas_tx_tiny_alloc()
4170 &cp->tx_tiny_dvma[i], GFP_KERNEL); in cas_tx_tiny_alloc()
4171 if (!cp->tx_tiny_bufs[i]) { in cas_tx_tiny_alloc()
4173 return -1; in cas_tx_tiny_alloc()
4186 mutex_lock(&cp->pm_mutex); in cas_open()
4188 hw_was_up = cp->hw_running; in cas_open()
4190 /* The power-management mutex protects the hw_running in cas_open()
4191 * etc. state so it is safe to do this bit without cp->lock in cas_open()
4193 if (!cp->hw_running) { in cas_open()
4198 * argument set to non-zero, which will force in cas_open()
4202 cp->hw_running = 1; in cas_open()
4206 err = -ENOMEM; in cas_open()
4210 /* alloc rx descriptors */ in cas_open()
4223 if (request_irq(cp->pdev->irq, cas_interrupt, in cas_open()
4224 IRQF_SHARED, dev->name, (void *) dev)) { in cas_open()
4225 netdev_err(cp->dev, "failed to request irq !\n"); in cas_open()
4226 err = -EAGAIN; in cas_open()
4231 napi_enable(&cp->napi); in cas_open()
4237 cp->opened = 1; in cas_open()
4241 mutex_unlock(&cp->pm_mutex); in cas_open()
4250 mutex_unlock(&cp->pm_mutex); in cas_open()
4260 napi_disable(&cp->napi); in cas_close()
4263 mutex_lock(&cp->pm_mutex); in cas_close()
4269 cp->opened = 0; in cas_close()
4276 free_irq(cp->pdev->irq, (void *) dev); in cas_close()
4280 mutex_unlock(&cp->pm_mutex); in cas_close()
4309 {-MII_BMSR},
4310 {-MII_BMCR},
4337 spin_lock_irqsave(&cp->lock, flags); in cas_read_regs()
4343 -ethtool_register_table[i].offsets); in cas_read_regs()
4346 val= readl(cp->regs+ethtool_register_table[i].offsets); in cas_read_regs()
4350 spin_unlock_irqrestore(&cp->lock, flags); in cas_read_regs()
4356 struct net_device_stats *stats = cp->net_stats; in cas_get_stats()
4362 if (!cp->hw_running) in cas_get_stats()
4367 * stored in 32-bit words. Added a mask of 0xffff to be safe, in cas_get_stats()
4373 spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags); in cas_get_stats()
4375 readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff; in cas_get_stats()
4377 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff; in cas_get_stats()
4379 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff; in cas_get_stats()
4381 tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) + in cas_get_stats()
4382 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff); in cas_get_stats()
4385 tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff); in cas_get_stats()
4388 readl(cp->regs + REG_MAC_COLL_EXCESS); in cas_get_stats()
4389 stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) + in cas_get_stats()
4390 readl(cp->regs + REG_MAC_COLL_LATE); in cas_get_stats()
4395 spin_lock(&cp->stat_lock[0]); in cas_get_stats()
4402 spin_unlock(&cp->stat_lock[0]); in cas_get_stats()
4405 spin_lock(&cp->stat_lock[i]); in cas_get_stats()
4418 spin_unlock(&cp->stat_lock[i]); in cas_get_stats()
4420 spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags); in cas_get_stats()
4432 if (!cp->hw_running) in cas_set_multicast()
4435 spin_lock_irqsave(&cp->lock, flags); in cas_set_multicast()
4436 rxcfg = readl(cp->regs + REG_MAC_RX_CFG); in cas_set_multicast()
4438 /* disable RX MAC and wait for completion */ in cas_set_multicast()
4439 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG); in cas_set_multicast()
4440 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) { in cas_set_multicast()
4441 if (!limit--) in cas_set_multicast()
4449 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG); in cas_set_multicast()
4450 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) { in cas_set_multicast()
4451 if (!limit--) in cas_set_multicast()
4457 cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp); in cas_set_multicast()
4459 writel(rxcfg, cp->regs + REG_MAC_RX_CFG); in cas_set_multicast()
4460 spin_unlock_irqrestore(&cp->lock, flags); in cas_set_multicast()
4466 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); in cas_get_drvinfo()
4467 strscpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); in cas_get_drvinfo()
4468 strscpy(info->bus_info, pci_name(cp->pdev), sizeof(info->bus_info)); in cas_get_drvinfo()
4483 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) { in cas_get_link_ksettings()
4489 spin_lock_irqsave(&cp->lock, flags); in cas_get_link_ksettings()
4491 linkstate = cp->lstate; in cas_get_link_ksettings()
4492 if (CAS_PHY_MII(cp->phy_type)) { in cas_get_link_ksettings()
4493 cmd->base.port = PORT_MII; in cas_get_link_ksettings()
4494 cmd->base.phy_address = cp->phy_addr; in cas_get_link_ksettings()
4508 if (cp->hw_running) { in cas_get_link_ksettings()
4517 cmd->base.port = PORT_FIBRE; in cas_get_link_ksettings()
4518 cmd->base.phy_address = 0; in cas_get_link_ksettings()
4522 if (cp->hw_running) { in cas_get_link_ksettings()
4523 /* pcs uses the same bits as mii */ in cas_get_link_ksettings()
4524 bmcr = readl(cp->regs + REG_PCS_MII_CTRL); in cas_get_link_ksettings()
4529 spin_unlock_irqrestore(&cp->lock, flags); in cas_get_link_ksettings()
4533 cmd->base.autoneg = AUTONEG_ENABLE; in cas_get_link_ksettings()
4534 cmd->base.speed = ((speed == 10) ? in cas_get_link_ksettings()
4538 cmd->base.duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF; in cas_get_link_ksettings()
4540 cmd->base.autoneg = AUTONEG_DISABLE; in cas_get_link_ksettings()
4541 cmd->base.speed = ((bmcr & CAS_BMCR_SPEED1000) ? in cas_get_link_ksettings()
4545 cmd->base.duplex = (bmcr & BMCR_FULLDPLX) ? in cas_get_link_ksettings()
4551 * speed to 0, but not cmd->duplex, in cas_get_link_ksettings()
4559 if (cp->link_cntl & BMCR_ANENABLE) { in cas_get_link_ksettings()
4560 cmd->base.speed = 0; in cas_get_link_ksettings()
4561 cmd->base.duplex = 0xff; in cas_get_link_ksettings()
4563 cmd->base.speed = SPEED_10; in cas_get_link_ksettings()
4564 if (cp->link_cntl & BMCR_SPEED100) { in cas_get_link_ksettings()
4565 cmd->base.speed = SPEED_100; in cas_get_link_ksettings()
4566 } else if (cp->link_cntl & CAS_BMCR_SPEED1000) { in cas_get_link_ksettings()
4567 cmd->base.speed = SPEED_1000; in cas_get_link_ksettings()
4569 cmd->base.duplex = (cp->link_cntl & BMCR_FULLDPLX) ? in cas_get_link_ksettings()
4574 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, in cas_get_link_ksettings()
4576 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, in cas_get_link_ksettings()
4587 u32 speed = cmd->base.speed; in cas_set_link_ksettings()
4590 if (cmd->base.autoneg != AUTONEG_ENABLE && in cas_set_link_ksettings()
4591 cmd->base.autoneg != AUTONEG_DISABLE) in cas_set_link_ksettings()
4592 return -EINVAL; in cas_set_link_ksettings()
4594 if (cmd->base.autoneg == AUTONEG_DISABLE && in cas_set_link_ksettings()
4598 (cmd->base.duplex != DUPLEX_HALF && in cas_set_link_ksettings()
4599 cmd->base.duplex != DUPLEX_FULL))) in cas_set_link_ksettings()
4600 return -EINVAL; in cas_set_link_ksettings()
4603 spin_lock_irqsave(&cp->lock, flags); in cas_set_link_ksettings()
4605 spin_unlock_irqrestore(&cp->lock, flags); in cas_set_link_ksettings()
4614 if ((cp->link_cntl & BMCR_ANENABLE) == 0) in cas_nway_reset()
4615 return -EINVAL; in cas_nway_reset()
4618 spin_lock_irqsave(&cp->lock, flags); in cas_nway_reset()
4620 spin_unlock_irqrestore(&cp->lock, flags); in cas_nway_reset()
4628 return cp->lstate == link_up; in cas_get_link()
4634 return cp->msg_enable; in cas_get_msglevel()
4640 cp->msg_enable = value; in cas_set_msglevel()
4646 return min_t(int, cp->casreg_len, CAS_MAX_REGS); in cas_get_regs_len()
4653 regs->version = 0; in cas_get_regs()
4654 /* cas_read_regs handles locks (cp->lock). */ in cas_get_regs()
4655 cas_read_regs(cp, p, regs->len / sizeof(u32)); in cas_get_regs()
4664 return -EOPNOTSUPP; in cas_get_sset_count()
4678 struct net_device_stats *stats = cas_get_stats(cp->dev); in cas_get_ethtool_stats()
4680 data[i++] = stats->collisions; in cas_get_ethtool_stats()
4681 data[i++] = stats->rx_bytes; in cas_get_ethtool_stats()
4682 data[i++] = stats->rx_crc_errors; in cas_get_ethtool_stats()
4683 data[i++] = stats->rx_dropped; in cas_get_ethtool_stats()
4684 data[i++] = stats->rx_errors; in cas_get_ethtool_stats()
4685 data[i++] = stats->rx_fifo_errors; in cas_get_ethtool_stats()
4686 data[i++] = stats->rx_frame_errors; in cas_get_ethtool_stats()
4687 data[i++] = stats->rx_length_errors; in cas_get_ethtool_stats()
4688 data[i++] = stats->rx_over_errors; in cas_get_ethtool_stats()
4689 data[i++] = stats->rx_packets; in cas_get_ethtool_stats()
4690 data[i++] = stats->tx_aborted_errors; in cas_get_ethtool_stats()
4691 data[i++] = stats->tx_bytes; in cas_get_ethtool_stats()
4692 data[i++] = stats->tx_dropped; in cas_get_ethtool_stats()
4693 data[i++] = stats->tx_errors; in cas_get_ethtool_stats()
4694 data[i++] = stats->tx_fifo_errors; in cas_get_ethtool_stats()
4695 data[i++] = stats->tx_packets; in cas_get_ethtool_stats()
4719 int rc = -EOPNOTSUPP; in cas_ioctl()
4724 mutex_lock(&cp->pm_mutex); in cas_ioctl()
4727 data->phy_id = cp->phy_addr; in cas_ioctl()
4731 spin_lock_irqsave(&cp->lock, flags); in cas_ioctl()
4733 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f); in cas_ioctl()
4735 spin_unlock_irqrestore(&cp->lock, flags); in cas_ioctl()
4740 spin_lock_irqsave(&cp->lock, flags); in cas_ioctl()
4742 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in); in cas_ioctl()
4744 spin_unlock_irqrestore(&cp->lock, flags); in cas_ioctl()
4750 mutex_unlock(&cp->pm_mutex); in cas_ioctl()
4760 struct pci_dev *pdev = cas_pdev->bus->self; in cas_program_bridge()
4766 if (pdev->vendor != 0x8086 || pdev->device != 0x537c) in cas_program_bridge()
4771 * 0x41. Using a 32-bit word read/modify/write at 0x40 in cas_program_bridge()
4778 /* Max out the Multi-Transaction Timer settings since in cas_program_bridge()
4781 * The register is 16-bit and lives at 0x50. When the in cas_program_bridge()
4789 * 1 -- 16 clocks in cas_program_bridge()
4790 * 2 -- 32 clocks in cas_program_bridge()
4791 * 3 -- 64 clocks in cas_program_bridge()
4792 * 4 -- 128 clocks in cas_program_bridge()
4793 * 5 -- 256 clocks in cas_program_bridge()
4802 /* The Read Prefecth Policy register is 16-bit and sits at in cas_program_bridge()
4803 * offset 0x52. It enables a "smart" pre-fetch policy. We in cas_program_bridge()
4812 * 15:13 --- ReRead Primary Bus in cas_program_bridge()
4813 * 12:10 --- FirstRead Primary Bus in cas_program_bridge()
4814 * 09:07 --- ReRead Secondary Bus in cas_program_bridge()
4815 * 06:04 --- FirstRead Secondary Bus in cas_program_bridge()
4869 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); in cas_init_one()
4874 dev_err(&pdev->dev, "Cannot find proper PCI device " in cas_init_one()
4876 err = -ENODEV; in cas_init_one()
4882 err = -ENOMEM; in cas_init_one()
4885 SET_NETDEV_DEV(dev, &pdev->dev); in cas_init_one()
4887 err = pci_request_regions(pdev, dev->name); in cas_init_one()
4889 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); in cas_init_one()
4923 dev_err(&pdev->dev, "Could not set PCI cache " in cas_init_one()
4932 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in cas_init_one()
4934 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); in cas_init_one()
4941 cp->pdev = pdev; in cas_init_one()
4944 cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0; in cas_init_one()
4946 cp->dev = dev; in cas_init_one()
4947 cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE : in cas_init_one()
4951 cp->of_node = pci_device_to_OF_node(pdev); in cas_init_one()
4954 cp->link_transition = LINK_TRANSITION_UNKNOWN; in cas_init_one()
4955 cp->link_transition_jiffies_valid = 0; in cas_init_one()
4957 spin_lock_init(&cp->lock); in cas_init_one()
4958 spin_lock_init(&cp->rx_inuse_lock); in cas_init_one()
4959 spin_lock_init(&cp->rx_spare_lock); in cas_init_one()
4961 spin_lock_init(&cp->stat_lock[i]); in cas_init_one()
4962 spin_lock_init(&cp->tx_lock[i]); in cas_init_one()
4964 spin_lock_init(&cp->stat_lock[N_TX_RINGS]); in cas_init_one()
4965 mutex_init(&cp->pm_mutex); in cas_init_one()
4967 timer_setup(&cp->link_timer, cas_link_timer, 0); in cas_init_one()
4973 atomic_set(&cp->reset_task_pending, 0); in cas_init_one()
4974 atomic_set(&cp->reset_task_pending_all, 0); in cas_init_one()
4975 atomic_set(&cp->reset_task_pending_spare, 0); in cas_init_one()
4976 atomic_set(&cp->reset_task_pending_mtu, 0); in cas_init_one()
4978 INIT_WORK(&cp->reset_task, cas_reset_task); in cas_init_one()
4982 cp->link_cntl = link_modes[link_mode]; in cas_init_one()
4984 cp->link_cntl = BMCR_ANENABLE; in cas_init_one()
4985 cp->lstate = link_down; in cas_init_one()
4986 cp->link_transition = LINK_TRANSITION_LINK_DOWN; in cas_init_one()
4987 netif_carrier_off(cp->dev); in cas_init_one()
4988 cp->timer_ticks = 0; in cas_init_one()
4991 cp->regs = pci_iomap(pdev, 0, casreg_len); in cas_init_one()
4992 if (!cp->regs) { in cas_init_one()
4993 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); in cas_init_one()
4996 cp->casreg_len = casreg_len; in cas_init_one()
5004 if (cp->cas_flags & CAS_FLAG_SATURN) in cas_init_one()
5007 cp->init_block = in cas_init_one()
5008 dma_alloc_coherent(&pdev->dev, sizeof(struct cas_init_block), in cas_init_one()
5009 &cp->block_dvma, GFP_KERNEL); in cas_init_one()
5010 if (!cp->init_block) { in cas_init_one()
5011 dev_err(&pdev->dev, "Cannot allocate init block, aborting\n"); in cas_init_one()
5016 cp->init_txds[i] = cp->init_block->txds[i]; in cas_init_one()
5019 cp->init_rxds[i] = cp->init_block->rxds[i]; in cas_init_one()
5022 cp->init_rxcs[i] = cp->init_block->rxcs[i]; in cas_init_one()
5025 skb_queue_head_init(&cp->rx_flows[i]); in cas_init_one()
5027 dev->netdev_ops = &cas_netdev_ops; in cas_init_one()
5028 dev->ethtool_ops = &cas_ethtool_ops; in cas_init_one()
5029 dev->watchdog_timeo = CAS_TX_TIMEOUT; in cas_init_one()
5032 netif_napi_add(dev, &cp->napi, cas_poll); in cas_init_one()
5034 dev->irq = pdev->irq; in cas_init_one()
5035 dev->dma = 0; in cas_init_one()
5038 if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0) in cas_init_one()
5039 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG; in cas_init_one()
5041 dev->features |= NETIF_F_HIGHDMA; in cas_init_one()
5043 /* MTU range: 60 - varies or 9000 */ in cas_init_one()
5044 dev->min_mtu = CAS_MIN_MTU; in cas_init_one()
5045 dev->max_mtu = CAS_MAX_MTU; in cas_init_one()
5048 dev_err(&pdev->dev, "Cannot register net device, aborting\n"); in cas_init_one()
5052 i = readl(cp->regs + REG_BIM_CFG); in cas_init_one()
5054 (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "", in cas_init_one()
5057 (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq, in cas_init_one()
5058 dev->dev_addr); in cas_init_one()
5061 cp->hw_running = 1; in cas_init_one()
5068 dma_free_coherent(&pdev->dev, sizeof(struct cas_init_block), in cas_init_one()
5069 cp->init_block, cp->block_dvma); in cas_init_one()
5072 mutex_lock(&cp->pm_mutex); in cas_init_one()
5073 if (cp->hw_running) in cas_init_one()
5075 mutex_unlock(&cp->pm_mutex); in cas_init_one()
5077 vfree(cp->fw_data); in cas_init_one()
5079 pci_iounmap(pdev, cp->regs); in cas_init_one()
5095 return -ENODEV; in cas_init_one()
5108 vfree(cp->fw_data); in cas_remove_one()
5110 mutex_lock(&cp->pm_mutex); in cas_remove_one()
5111 cancel_work_sync(&cp->reset_task); in cas_remove_one()
5112 if (cp->hw_running) in cas_remove_one()
5114 mutex_unlock(&cp->pm_mutex); in cas_remove_one()
5117 if (cp->orig_cacheline_size) { in cas_remove_one()
5122 cp->orig_cacheline_size); in cas_remove_one()
5125 dma_free_coherent(&pdev->dev, sizeof(struct cas_init_block), in cas_remove_one()
5126 cp->init_block, cp->block_dvma); in cas_remove_one()
5127 pci_iounmap(pdev, cp->regs); in cas_remove_one()
5139 mutex_lock(&cp->pm_mutex); in cas_suspend()
5142 if (cp->opened) { in cas_suspend()
5157 if (cp->hw_running) in cas_suspend()
5159 mutex_unlock(&cp->pm_mutex); in cas_suspend()
5171 mutex_lock(&cp->pm_mutex); in cas_resume()
5173 if (cp->opened) { in cas_resume()
5177 cp->hw_running = 1; in cas_resume()
5184 mutex_unlock(&cp->pm_mutex); in cas_resume()