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/linux-6.12.1/arch/arm/mach-mvebu/
Dmvebu-soc-id.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ID and revision information for mvebu SoCs
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * revision that can be read from the PCI control register. This is
12 * ID and revision are retrieved, the mapping is freed.
15 #define pr_fmt(fmt) "mvebu-soc-id: " fmt
26 #include "mvebu-soc-id.h"
39 { .compatible = "marvell,armada-xp-pcie", },
40 { .compatible = "marvell,armada-370-pcie", },
41 { .compatible = "marvell,kirkwood-pcie" },
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Dmvebu-soc-id.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Marvell EBU SoC ID and revision definitions.
11 /* Armada XP ID */
16 /* Armada XP Revision */
20 /* Amada 370 ID */
23 /* Amada 370 Revision */
26 /* Armada 375 ID */
33 /* Armada 38x ID */
38 /* Armada 38x Revision */
47 return -1; in mvebu_get_soc_id()
/linux-6.12.1/drivers/ssb/
Ddriver_chipcommon.c7 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
45 struct ssb_device *ccdev = cc->dev; in ssb_chipco_set_clockmode()
51 bus = ccdev->bus; in ssb_chipco_set_clockmode()
54 if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW) in ssb_chipco_set_clockmode()
57 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) in ssb_chipco_set_clockmode()
59 WARN_ON(ccdev->id.revision >= 20); in ssb_chipco_set_clockmode()
62 if (ccdev->id.revision < 6) in ssb_chipco_set_clockmode()
66 if (ccdev->id.revision >= 10) in ssb_chipco_set_clockmode()
69 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) in ssb_chipco_set_clockmode()
79 if (ccdev->id.revision < 10) { in ssb_chipco_set_clockmode()
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/linux-6.12.1/drivers/gpu/drm/amd/include/
Ddiscovery.h79 uint32_t id; /* Table ID */ member
94 uint16_t hw_id; /* Hardware ID */
99 uint8_t revision; /* HCID Revision */ member
112 uint16_t hw_id; /* Hardware ID */
115 uint8_t major; /* Hardware ID.major version */
116 uint8_t minor; /* Hardware ID.minor version */
117 uint8_t revision; /* Hardware ID.revision version */ member
120 uint8_t sub_revision : 4; /* HCID Sub-Revision */
122 uint8_t sub_revision : 4; /* HCID Sub-Revision */
129 uint16_t hw_id; /* Hardware ID */
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/linux-6.12.1/drivers/scsi/mvsas/
Dmv_94xx.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
17 struct mvs_phy *phy = &mvi->phy[i]; in mvs_94xx_detect_porttype()
23 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); in mvs_94xx_detect_porttype()
26 phy->phy_type |= PORT_TYPE_SAS; in mvs_94xx_detect_porttype()
30 phy->phy_type |= PORT_TYPE_SATA; in mvs_94xx_detect_porttype()
43 * R0Ch -> R118h[15:0] (Adapted DFE F3 - F5 coefficient) in set_phy_tuning()
44 * R0Dh -> R118h[31:16] (Generation 1 Setting 0) in set_phy_tuning()
45 * R0Eh -> R11Ch[15:0] (Generation 1 Setting 1) in set_phy_tuning()
46 * R0Fh -> R11Ch[31:16] (Generation 2 Setting 0) in set_phy_tuning()
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/linux-6.12.1/drivers/soc/samsung/
Dexynos-chipid.c1 // SPDX-License-Identifier: GPL-2.0
7 * Exynos - CHIP ID support
12 * Samsung Exynos SoC Adaptive Supply Voltage and Chip ID support
23 #include <linux/soc/samsung/exynos-chipid.h>
26 #include "exynos-asv.h"
29 unsigned int rev_reg; /* revision register offset */
30 unsigned int main_rev_shift; /* main revision offset in rev_reg */
31 unsigned int sub_rev_shift; /* sub revision offset in rev_reg */
36 u32 revision; member
41 unsigned int id; member
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/bios/
Dbios_parser2.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
48 bp->base.ctx->logger
92 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
96 kfree(bp->base.bios_local_image); in bios_parser2_destruct()
97 kfree(bp->base.integrated_info); in bios_parser2_destruct()
122 /* initialize the revision to 0 which is invalid revision */ in get_atom_data_table_revision()
123 tbl_revision->major = 0; in get_atom_data_table_revision()
124 tbl_revision->minor = 0; in get_atom_data_table_revision()
129 tbl_revision->major = in get_atom_data_table_revision()
130 (uint32_t) atom_data_tbl->format_revision & 0x3f; in get_atom_data_table_revision()
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Dbios_parser.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
52 bp->base.ctx->logger
54 #define DATA_TABLES(table) (bp->master_data_tbl->ListOfDataTables.table)
62 struct graphics_object_id id);
104 return &bp->base; in bios_parser_create()
113 kfree(bp->base.bios_local_image); in bios_parser_destruct()
114 kfree(bp->base.integrated_info); in bios_parser_destruct()
136 uint32_t object_table_offset = bp->object_info_tbl_offset + offset; in get_number_of_objects()
138 table = ((ATOM_OBJECT_TABLE *) bios_get_image(&bp->base, in get_number_of_objects()
145 return table->ucNumberOfObjects; in get_number_of_objects()
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/linux-6.12.1/drivers/watchdog/
Dpcwd.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * 960108 Fixed end-of-file pointer (Thanks to Dan Hollis), added
24 * added watchdog disable/re-enable routines. Added firmware
26 * Removed some extra defines, added an autodetect Revision
60 #include <linux/errno.h> /* For the -ENODEV/... values */
71 #include <linux/ioport.h> /* For io-port access */
79 #define WATCHDOG_DRIVER_NAME "ISA-PC Watchdog"
94 * These are the auto-probe addresses available.
96 * Revision A only uses ports 0x270 and 0x370. Revision C introduced 0x350.
97 * Revision A has an address range of 2 addresses, while Revision C has 4.
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/linux-6.12.1/kernel/bpf/
Dmprog.c1 // SPDX-License-Identifier: GPL-2.0
11 struct bpf_link *link = ERR_PTR(-EINVAL); in bpf_mprog_link()
12 bool id = flags & BPF_F_ID; in bpf_mprog_link() local
14 if (id) in bpf_mprog_link()
20 if (type && link->prog->type != type) { in bpf_mprog_link()
22 return -EINVAL; in bpf_mprog_link()
25 tuple->link = link; in bpf_mprog_link()
26 tuple->prog = link->prog; in bpf_mprog_link()
34 struct bpf_prog *prog = ERR_PTR(-EINVAL); in bpf_mprog_prog()
35 bool id = flags & BPF_F_ID; in bpf_mprog_prog() local
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/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Damdgpu_cgs.c41 ((struct amdgpu_cgs_device *)cgs_device)->adev
142 if (adev->asic_type >= CHIP_TOPAZ) in fw_type_convert()
167 fw_version = adev->sdma.instance[0].fw_version; in amdgpu_get_firmware_version()
170 fw_version = adev->sdma.instance[1].fw_version; in amdgpu_get_firmware_version()
173 fw_version = adev->gfx.ce_fw_version; in amdgpu_get_firmware_version()
176 fw_version = adev->gfx.pfp_fw_version; in amdgpu_get_firmware_version()
179 fw_version = adev->gfx.me_fw_version; in amdgpu_get_firmware_version()
182 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
185 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
188 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
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/linux-6.12.1/Documentation/ABI/testing/
Dsysfs-bus-cdx18 Vendor ID for this CDX device, in hexadecimal. Vendor ID is
20 Combination of Vendor ID and Device ID identifies a device.
26 Device ID for this CDX device, in hexadecimal. Device ID is
29 Combination of Vendor ID and Device ID identifies a device.
35 Subsystem Vendor ID for this CDX device, in hexadecimal.
36 Subsystem Vendor ID is 16 bit identifier specific to the
43 Subsystem Device ID for this CDX device, in hexadecimal
44 Subsystem Device ID is 16 bit identifier specific to the
54 What: /sys/bus/cdx/devices/.../revision
58 This file contains the revision field of the CDX device, in hexadecimal.
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/linux-6.12.1/drivers/soc/imx/
Dsoc-imx8m.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/arm-smccc.h>
62 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-ocotp"); in imx8mq_soc_revision()
77 * SOC revision on older imx8mq is not available in fuses so query in imx8mq_soc_revision()
107 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-ocotp"); in imx8mm_soc_uid()
137 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); in imx8mm_soc_revision()
191 const struct of_device_id *id; in imx8_soc_init() local
198 return -ENOMEM; in imx8_soc_init()
200 soc_dev_attr->family = "Freescale i.MX"; in imx8_soc_init()
202 ret = of_property_read_string(of_root, "model", &soc_dev_attr->machine); in imx8_soc_init()
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/linux-6.12.1/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
10 int revision; member
66 { .id = 0, .pp = 0, .dspp = 0,
68 { .id = 1, .pp = 1, .dspp = 1,
70 { .id = 2, .pp = 2, .dspp = 2,
72 { .id = 3, .pp = -1, .dspp = -1,
74 { .id = 4, .pp = -1, .dspp = -1,
155 { .id = 0, .pp = 0, .dspp = 0,
157 { .id = 1, .pp = -1, .dspp = -1,
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/linux-6.12.1/drivers/soc/aspeed/
Daspeed-socinfo.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 const u32 id; member
34 unsigned int id = siliconid & 0xff00ffff; in siliconid_to_name() local
38 if (rev_table[i].id == id) in siliconid_to_name()
88 np = of_find_compatible_node(NULL, NULL, "aspeed,silicon-id"); in aspeed_socinfo_init()
91 return -ENODEV; in aspeed_socinfo_init()
97 return -ENODEV; in aspeed_socinfo_init()
114 return -ENODEV; in aspeed_socinfo_init()
119 * Revision: A1 in aspeed_socinfo_init()
120 * SoC ID: raw silicon revision id in aspeed_socinfo_init()
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/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ddr/
Djedec,lpddr2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - elpida,ECB240ABACN
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Djedec,lpddr-props.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Krzysztof Kozlowski <krzk@kernel.org>
23 lpddrX-YY,ZZZZ where X is the LPDDR version, YY is the manufacturer ID
24 (from MR5) and ZZZZ is the revision ID (from MR6 and MR7). Both IDs are
36 revision-id:
37 $ref: /schemas/types.yaml#/definitions/uint32-array
39 Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>).
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/linux-6.12.1/fs/smb/client/
Dcifsacl.c1 // SPDX-License-Identifier: LGPL-2.1
15 #include <linux/key-type.h>
19 #include <keys/user-type.h>
29 /* security id for everyone/world system group */
32 /* security id for Authenticated Users system group */
36 /* S-1-22-1 Unmapped Unix users */
40 /* S-1-22-2 Unmapped Unix groups */
45 * See https://technet.microsoft.com/en-us/library/hh509017(v=ws.10).aspx
48 /* S-1-5-88 MS NFS and Apple style UID/GID/mode */
50 /* S-1-5-88-1 Unix uid */
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/linux-6.12.1/include/linux/
Dmcb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
21 * struct mcb_bus - MEN Chameleon Bus
27 * @revision: the FPGA's revision number
35 u8 revision; member
48 * struct mcb_device - MEN Chameleon Bus device
54 * @id: mcb device id
59 * @rev: revision in Chameleon table
67 u16 id; member
81 * struct mcb_driver - MEN Chameleon Bus device driver
84 * @id_table: mcb id table
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Ddfl.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * enum dfl_id_type - define the DFL FIU types
24 * struct dfl_device - represent an dfl device on dfl bus
27 * @id: id of the dfl device.
30 * @revision: revision of this dfl device feature.
35 * @id_entry: matched id entry in dfl driver's id table.
42 int id; member
45 u8 revision; member
57 * struct dfl_driver - represent an dfl device driver
85 * module_dfl_driver() - Helper macro for drivers that don't do
/linux-6.12.1/arch/mips/pci/
Dfixup-cobalt.c33 * The Cobalt board ID information. The boards have an ID number wired
42 * document "GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs",
47 * Code does not cause a problem for these non-compliant BIOSes, so we used
48 * this as the default in the GT-64111.
56 if (dev->devfn == PCI_DEVFN(0, 0) && in qube_raq_galileo_early_fixup()
57 (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) { in qube_raq_galileo_early_fixup()
59 dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff); in qube_raq_galileo_early_fixup()
93 if (dev->devfn != PCI_DEVFN(0, 0)) in qube_raq_galileo_fixup()
96 /* Fix PCI latency-timer and cache-line-size values in Galileo in qube_raq_galileo_fixup()
108 * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x-- in qube_raq_galileo_fixup()
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/linux-6.12.1/drivers/cdx/
Dcdx.h1 /* SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
14 * struct cdx_dev_params - CDX device parameters
17 * @vendor: Vendor ID for CDX device
18 * @device: Device ID for CDX device
19 * @subsys_vendor: Sub vendor ID for CDX device
20 * @subsys_device: Sub device ID for CDX device
25 * @req_id: Requestor ID associated with CDX device
27 * @revision: Revision of the CDX device
28 * @msi_dev_id: MSI device ID associated with CDX device
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/linux-6.12.1/drivers/firmware/imx/
Dimx-scu-soc.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/firmware/imx/rsrc.h>
23 u32 id; member
40 hdr->ver = IMX_SC_RPC_VERSION; in imx_scu_soc_uid()
41 hdr->svc = IMX_SC_RPC_SVC_MISC; in imx_scu_soc_uid()
42 hdr->func = IMX_SC_MISC_FUNC_UNIQUE_ID; in imx_scu_soc_uid()
43 hdr->size = 1; in imx_scu_soc_uid()
64 hdr->ver = IMX_SC_RPC_VERSION; in imx_scu_soc_id()
65 hdr->svc = IMX_SC_RPC_SVC_MISC; in imx_scu_soc_id()
66 hdr->func = IMX_SC_MISC_FUNC_GET_CONTROL; in imx_scu_soc_id()
[all …]
/linux-6.12.1/include/uapi/linux/
Dpfrut.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
16 * PFRU_IOC_SET_REV - _IOW(PFRUT_IOCTL_MAGIC, 0x01, unsigned int)
19 * * 0 - success
20 * * -EFAULT - fail to read the revision id
21 * * -EINVAL - user provides an invalid revision id
23 * Set the Revision ID for Platform Firmware Runtime Update.
28 * PFRU_IOC_STAGE - _IOW(PFRUT_IOCTL_MAGIC, 0x02, unsigned int)
31 * * 0 - success
32 * * -EINVAL - stage phase returns invalid result
39 * PFRU_IOC_ACTIVATE - _IOW(PFRUT_IOCTL_MAGIC, 0x03, unsigned int)
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/linux-6.12.1/drivers/gpu/drm/panfrost/
Dpanfrost_gpu.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/dma-mapping.h>
27 if (test_bit(PANFROST_COMP_BIT_GPU, pfdev->is_suspended)) in panfrost_gpu_irq_handler()
39 dev_warn(pfdev->dev, "GPU Fault 0x%08x (%s) at 0x%016llx\n", in panfrost_gpu_irq_handler()
44 dev_warn(pfdev->dev, "There were multiple GPU faults - some have not been reported\n"); in panfrost_gpu_irq_handler()
68 clear_bit(PANFROST_COMP_BIT_GPU, pfdev->is_suspended); in panfrost_gpu_soft_reset()
71 ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, in panfrost_gpu_soft_reset()
75 dev_err(pfdev->dev, "gpu soft reset timed out, attempting hard reset\n"); in panfrost_gpu_soft_reset()
78 ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, val, in panfrost_gpu_soft_reset()
81 dev_err(pfdev->dev, "gpu hard reset timed out\n"); in panfrost_gpu_soft_reset()
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