Lines Matching +full:revision +full:- +full:id
1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
17 struct mvs_phy *phy = &mvi->phy[i]; in mvs_94xx_detect_porttype()
23 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); in mvs_94xx_detect_porttype()
26 phy->phy_type |= PORT_TYPE_SAS; in mvs_94xx_detect_porttype()
30 phy->phy_type |= PORT_TYPE_SATA; in mvs_94xx_detect_porttype()
43 * R0Ch -> R118h[15:0] (Adapted DFE F3 - F5 coefficient) in set_phy_tuning()
44 * R0Dh -> R118h[31:16] (Generation 1 Setting 0) in set_phy_tuning()
45 * R0Eh -> R11Ch[15:0] (Generation 1 Setting 1) in set_phy_tuning()
46 * R0Fh -> R11Ch[31:16] (Generation 2 Setting 0) in set_phy_tuning()
47 * R10h -> R120h[15:0] (Generation 2 Setting 1) in set_phy_tuning()
48 * R11h -> R120h[31:16] (Generation 3 Setting 0) in set_phy_tuning()
49 * R12h -> R124h[15:0] (Generation 3 Setting 1) in set_phy_tuning()
50 * R13h -> R124h[31:16] (Generation 4 Setting 0 (Reserved)) in set_phy_tuning()
54 if (mvi->pdev->revision == VANIR_A0_REV) in set_phy_tuning()
103 if ((mvi->pdev->revision == VANIR_A0_REV) in set_phy_ffe_tuning()
104 || (mvi->pdev->revision == VANIR_B0_REV)) in set_phy_ffe_tuning()
137 /* R110h DFE F0-F1 Coefficient Control/DFE Update Control in set_phy_ffe_tuning()
206 temp = (u32)(*(u32 *)&mvi->hba_info_param.phy_tuning[phy_id]); in mvs_94xx_config_reg_from_hba()
208 mvi->hba_info_param.phy_tuning[phy_id].trans_emp_amp = 0x6; in mvs_94xx_config_reg_from_hba()
209 mvi->hba_info_param.phy_tuning[phy_id].trans_amp = 0x1A; in mvs_94xx_config_reg_from_hba()
210 mvi->hba_info_param.phy_tuning[phy_id].trans_amp_adj = 0x3; in mvs_94xx_config_reg_from_hba()
213 temp = (u8)(*(u8 *)&mvi->hba_info_param.ffe_ctl[phy_id]); in mvs_94xx_config_reg_from_hba()
215 switch (mvi->pdev->revision) { in mvs_94xx_config_reg_from_hba()
218 mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7; in mvs_94xx_config_reg_from_hba()
219 mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0x7; in mvs_94xx_config_reg_from_hba()
225 mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7; in mvs_94xx_config_reg_from_hba()
226 mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0xC; in mvs_94xx_config_reg_from_hba()
231 temp = (u8)(*(u8 *)&mvi->hba_info_param.phy_rate[phy_id]); in mvs_94xx_config_reg_from_hba()
234 mvi->hba_info_param.phy_rate[phy_id] = 0x2; in mvs_94xx_config_reg_from_hba()
237 mvi->hba_info_param.phy_tuning[phy_id]); in mvs_94xx_config_reg_from_hba()
239 mvi->hba_info_param.ffe_ctl[phy_id]); in mvs_94xx_config_reg_from_hba()
241 mvi->hba_info_param.phy_rate[phy_id]); in mvs_94xx_config_reg_from_hba()
246 void __iomem *regs = mvi->regs; in mvs_94xx_enable_xmt()
275 delay--; in mvs_94xx_phy_reset()
297 u8 revision = 0; in mvs_94xx_phy_enable() local
299 revision = mvi->pdev->revision; in mvs_94xx_phy_enable()
300 if (revision == VANIR_A0_REV) { in mvs_94xx_phy_enable()
304 if (revision == VANIR_B0_REV) { in mvs_94xx_phy_enable()
319 void __iomem *regs = mvi->regs_ex - 0x10200; in mvs_94xx_sgpio_init()
326 mw32(MVS_SGPIO_CTRL + MVS_SGPIO_HOST_OFFSET * mvi->id, in mvs_94xx_sgpio_init()
329 mw32(MVS_SGPIO_CFG1 + MVS_SGPIO_HOST_OFFSET * mvi->id, in mvs_94xx_sgpio_init()
338 mw32(MVS_SGPIO_CFG2 + MVS_SGPIO_HOST_OFFSET * mvi->id, in mvs_94xx_sgpio_init()
343 mw32(MVS_SGPIO_CFG0 + MVS_SGPIO_HOST_OFFSET * mvi->id, in mvs_94xx_sgpio_init()
348 (12 - 1) << MVS_SGPIO_CFG0_AUT_BITLEN_SHIFT in mvs_94xx_sgpio_init()
351 mw32(MVS_SGPIO_DCTRL + MVS_SGPIO_HOST_OFFSET * mvi->id, in mvs_94xx_sgpio_init()
354 mw32(MVS_SGPIO_DSRC + MVS_SGPIO_HOST_OFFSET * mvi->id, in mvs_94xx_sgpio_init()
355 ((mvi->id * 4) + 3) << (8 * 3) | in mvs_94xx_sgpio_init()
356 ((mvi->id * 4) + 2) << (8 * 2) | in mvs_94xx_sgpio_init()
357 ((mvi->id * 4) + 1) << (8 * 1) | in mvs_94xx_sgpio_init()
358 ((mvi->id * 4) + 0) << (8 * 0)); in mvs_94xx_sgpio_init()
364 void __iomem *regs = mvi->regs; in mvs_94xx_init()
367 u8 revision; in mvs_94xx_init() local
369 revision = mvi->pdev->revision; in mvs_94xx_init()
371 if (mvi->flags & MVF_FLAG_SOC) { in mvs_94xx_init()
386 if (mvi->flags & MVF_FLAG_SOC) { in mvs_94xx_init()
402 if (revision == VANIR_A0_REV) { in mvs_94xx_init()
407 if (revision == VANIR_A0_REV || revision == VANIR_B0_REV) in mvs_94xx_init()
414 if (revision == VANIR_B0_REV) { in mvs_94xx_init()
431 if ((revision == VANIR_A0_REV) || in mvs_94xx_init()
432 (revision == VANIR_B0_REV) || in mvs_94xx_init()
433 (revision == VANIR_C0_REV)) { in mvs_94xx_init()
446 mw32(MVS_CMD_LIST_LO, mvi->slot_dma); in mvs_94xx_init()
447 mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16); in mvs_94xx_init()
449 mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma); in mvs_94xx_init()
450 mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16); in mvs_94xx_init()
453 mw32(MVS_TX_LO, mvi->tx_dma); in mvs_94xx_init()
454 mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16); in mvs_94xx_init()
457 mw32(MVS_RX_LO, mvi->rx_dma); in mvs_94xx_init()
458 mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16); in mvs_94xx_init()
460 for (i = 0; i < mvi->chip->n_phy; i++) { in mvs_94xx_init()
464 cpu_to_le64(mvi->phy[i].dev_sas_addr)); in mvs_94xx_init()
475 if (mvi->flags & MVF_FLAG_SOC) { in mvs_94xx_init()
486 for (i = 0; i < mvi->chip->n_phy; i++) { in mvs_94xx_init()
554 /* change the connection open-close behavior (bit 9) in mvs_94xx_init()
572 if (!mvs_ioremap(mvi, 2, -1)) { in mvs_94xx_ioremap()
573 mvi->regs_ex = mvi->regs + 0x10200; in mvs_94xx_ioremap()
574 mvi->regs += 0x20000; in mvs_94xx_ioremap()
575 if (mvi->id == 1) in mvs_94xx_ioremap()
576 mvi->regs += 0x4000; in mvs_94xx_ioremap()
579 return -1; in mvs_94xx_ioremap()
584 if (mvi->regs) { in mvs_94xx_iounmap()
585 mvi->regs -= 0x20000; in mvs_94xx_iounmap()
586 if (mvi->id == 1) in mvs_94xx_iounmap()
587 mvi->regs -= 0x4000; in mvs_94xx_iounmap()
588 mvs_iounmap(mvi->regs); in mvs_94xx_iounmap()
594 void __iomem *regs = mvi->regs_ex; in mvs_94xx_interrupt_enable()
609 void __iomem *regs = mvi->regs_ex; in mvs_94xx_interrupt_disable()
625 void __iomem *regs = mvi->regs_ex; in mvs_94xx_isr_status()
627 if (!(mvi->flags & MVF_FLAG_SOC)) { in mvs_94xx_isr_status()
638 void __iomem *regs = mvi->regs; in mvs_94xx_isr()
640 if (((stat & MVS_IRQ_SAS_A) && mvi->id == 0) || in mvs_94xx_isr()
641 ((stat & MVS_IRQ_SAS_B) && mvi->id == 1)) { in mvs_94xx_isr()
644 spin_lock(&mvi->lock); in mvs_94xx_isr()
646 spin_unlock(&mvi->lock); in mvs_94xx_isr()
669 void __iomem *regs = mvi->regs; in mvs_94xx_clear_srs_irq()
702 void __iomem *regs = mvi->regs; in mvs_94xx_issue_stop()
714 void __iomem *regs = mvi->regs; in mvs_94xx_non_spec_ncq_error()
728 mvs_release_task(mvi, device->sas_device); in mvs_94xx_non_spec_ncq_error()
733 mvs_release_task(mvi, device->sas_device); in mvs_94xx_non_spec_ncq_error()
743 void __iomem *regs = mvi->regs; in mvs_94xx_free_reg_set()
749 mvi->sata_reg_set &= ~bit(reg_set); in mvs_94xx_free_reg_set()
751 w_reg_set_enable(reg_set, (u32)mvi->sata_reg_set); in mvs_94xx_free_reg_set()
753 w_reg_set_enable(reg_set, (u32)(mvi->sata_reg_set >> 32)); in mvs_94xx_free_reg_set()
763 void __iomem *regs = mvi->regs; in mvs_94xx_assign_reg_set()
768 i = mv_ffc64(mvi->sata_reg_set); in mvs_94xx_assign_reg_set()
770 mvi->sata_reg_set |= bit(i); in mvs_94xx_assign_reg_set()
771 w_reg_set_enable(i, (u32)(mvi->sata_reg_set >> 32)); in mvs_94xx_assign_reg_set()
775 mvi->sata_reg_set |= bit(i); in mvs_94xx_assign_reg_set()
776 w_reg_set_enable(i, (u32)mvi->sata_reg_set); in mvs_94xx_assign_reg_set()
791 buf_prd->addr = cpu_to_le64(sg_dma_address(sg)); in mvs_94xx_make_prd()
793 buf_prd->im_len = cpu_to_le32(*(u32 *)&im_len); in mvs_94xx_make_prd()
808 struct sas_identify_frame *id) in mvs_94xx_get_dev_identify_frame() argument
818 memcpy(id, id_frame, 28); in mvs_94xx_get_dev_identify_frame()
822 struct sas_identify_frame *id) in mvs_94xx_get_att_identify_frame() argument
832 port_id + mvi->id * mvi->chip->n_phy, i, id_frame[i]); in mvs_94xx_get_att_identify_frame()
834 memcpy(id, id_frame, 28); in mvs_94xx_get_att_identify_frame()
837 static u32 mvs_94xx_make_dev_info(struct sas_identify_frame *id) in mvs_94xx_make_dev_info() argument
841 att_dev_info |= id->dev_type; in mvs_94xx_make_dev_info()
842 if (id->stp_iport) in mvs_94xx_make_dev_info()
844 if (id->smp_iport) in mvs_94xx_make_dev_info()
846 if (id->ssp_iport) in mvs_94xx_make_dev_info()
848 if (id->stp_tport) in mvs_94xx_make_dev_info()
850 if (id->smp_tport) in mvs_94xx_make_dev_info()
852 if (id->ssp_tport) in mvs_94xx_make_dev_info()
855 att_dev_info |= (u32)id->phy_id<<24; in mvs_94xx_make_dev_info()
859 static u32 mvs_94xx_make_att_info(struct sas_identify_frame *id) in mvs_94xx_make_att_info() argument
861 return mvs_94xx_make_dev_info(id); in mvs_94xx_make_att_info()
865 struct sas_identify_frame *id) in mvs_94xx_fix_phy_info() argument
867 struct mvs_phy *phy = &mvi->phy[i]; in mvs_94xx_fix_phy_info()
868 struct asd_sas_phy *sas_phy = &phy->sas_phy; in mvs_94xx_fix_phy_info()
869 mv_dprintk("get all reg link rate is 0x%x\n", phy->phy_status); in mvs_94xx_fix_phy_info()
870 sas_phy->linkrate = in mvs_94xx_fix_phy_info()
871 (phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >> in mvs_94xx_fix_phy_info()
873 sas_phy->linkrate += 0x8; in mvs_94xx_fix_phy_info()
874 mv_dprintk("get link rate is %d\n", sas_phy->linkrate); in mvs_94xx_fix_phy_info()
875 phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS; in mvs_94xx_fix_phy_info()
876 phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS; in mvs_94xx_fix_phy_info()
877 mvs_94xx_get_dev_identify_frame(mvi, i, id); in mvs_94xx_fix_phy_info()
878 phy->dev_info = mvs_94xx_make_dev_info(id); in mvs_94xx_fix_phy_info()
880 if (phy->phy_type & PORT_TYPE_SAS) { in mvs_94xx_fix_phy_info()
881 mvs_94xx_get_att_identify_frame(mvi, i, id); in mvs_94xx_fix_phy_info()
882 phy->att_dev_info = mvs_94xx_make_att_info(id); in mvs_94xx_fix_phy_info()
883 phy->att_dev_sas_addr = *(u64 *)id->sas_addr; in mvs_94xx_fix_phy_info()
885 phy->att_dev_info = PORT_DEV_STP_TRGT | 1; in mvs_94xx_fix_phy_info()
901 lrmax = (rates->maximum_linkrate - SAS_LINK_RATE_1_5_GBPS) << 12; in mvs_94xx_phy_set_link_rate()
914 void __iomem *regs = mvi->regs; in mvs_94xx_clear_active_cmds()
926 void __iomem *regs = mvi->regs_ex - 0x10200; in mvs_94xx_spi_read_data()
932 void __iomem *regs = mvi->regs_ex - 0x10200; in mvs_94xx_spi_write_data()
946 void __iomem *regs = mvi->regs_ex - 0x10200; in mvs_94xx_spi_buildcmd()
965 void __iomem *regs = mvi->regs_ex - 0x10200; in mvs_94xx_spi_issuecmd()
973 void __iomem *regs = mvi->regs_ex - 0x10200; in mvs_94xx_spi_waitdataready()
983 return -1; in mvs_94xx_spi_waitdataready()
998 if ((mvi->pdev->revision == VANIR_A0_REV) || in mvs_94xx_fix_dma()
999 (mvi->pdev->revision == VANIR_B0_REV)) in mvs_94xx_fix_dma()
1001 mvi->bulk_buffer_dma : mvi->bulk_buffer_dma1; in mvs_94xx_fix_dma()
1006 if (i == MAX_SG_ENTRY - 1) { in mvs_94xx_fix_dma()
1007 buf_prd->addr = cpu_to_le64(virt_to_phys(buf_prd - 1)); in mvs_94xx_fix_dma()
1011 buf_prd->addr = cpu_to_le64(buf_dma); in mvs_94xx_fix_dma()
1014 buf_prd->im_len = cpu_to_le32(*(u32 *)&im_len); in mvs_94xx_fix_dma()
1020 void __iomem *regs = mvi->regs; in mvs_94xx_tune_interrupt()
1051 return -EINVAL; in mvs_94xx_gpio_write()
1054 return -EINVAL; in mvs_94xx_gpio_write()
1060 for (i = 0; i < mvs_prv->n_host * 4 * 3; i++) { in mvs_94xx_gpio_write()
1063 struct mvs_info *mvi = mvs_prv->mvi[i/(4*3)]; in mvs_94xx_gpio_write()
1065 void __iomem *regs = mvi->regs_ex - 0x10200; in mvs_94xx_gpio_write()
1067 int drive = (i/3) & (4-1); /* drive number on host */ in mvs_94xx_gpio_write()
1070 MVS_SGPIO_HOST_OFFSET * mvi->id); in mvs_94xx_gpio_write()
1081 * on the led type (activity/id/fail) in mvs_94xx_gpio_write()
1092 case 1: /* id */ in mvs_94xx_gpio_write()
1106 MVS_SGPIO_HOST_OFFSET * mvi->id); in mvs_94xx_gpio_write()
1113 if (reg_index + reg_count > mvs_prv->n_host) in mvs_94xx_gpio_write()
1114 return -EINVAL; in mvs_94xx_gpio_write()
1117 struct mvs_info *mvi = mvs_prv->mvi[i+reg_index]; in mvs_94xx_gpio_write()
1118 void __iomem *regs = mvi->regs_ex - 0x10200; in mvs_94xx_gpio_write()
1120 mw32(MVS_SGPIO_DCTRL + MVS_SGPIO_HOST_OFFSET * mvi->id, in mvs_94xx_gpio_write()
1125 return -ENOSYS; in mvs_94xx_gpio_write()